KR100745949B1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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KR100745949B1
KR100745949B1 KR1020060058658A KR20060058658A KR100745949B1 KR 100745949 B1 KR100745949 B1 KR 100745949B1 KR 1020060058658 A KR1020060058658 A KR 1020060058658A KR 20060058658 A KR20060058658 A KR 20060058658A KR 100745949 B1 KR100745949 B1 KR 100745949B1
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gate
active region
region
line
active
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KR1020060058658A
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Korean (ko)
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박승표
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor device is provided to prevent crack from happening on a gate oxide layer at burn-in test and defective from happening after a package burn-in test. A first active region and a second active region are formed on both sides of a sense amplifier region. The first active region consists of plural bar-shaped region and line-shaped regions connecting outer edges of the bar-shaped regions. The second active region consists of plural bar-shaped region and line-shaped regions connecting outer edges of the bar-shaped regions. A first gate(130) is formed between the first and second active regions, and a second gate(137) is formed outside the line-shaped region of the second active region. A bit line contact(140) is formed on the bar-shaped region of the first and second active regions.

Description

반도체 소자{SEMICONDUCTOR DEVICE}Semiconductor device {SEMICONDUCTOR DEVICE}

도 1은 종래기술에 따른 반도체 소자를 도시한 레이아웃.1 is a layout showing a semiconductor device according to the prior art.

도 2a 내지 도 2c는 본 발명에 따른 반도체 소자를 도시한 레이아웃.2A to 2C are layouts showing a semiconductor device according to the present invention.

본 발명은 반도체 소자에 관한 것으로, 센스 앰프 영역의 비트라인 분리신호(BISH)용 트랜지스터의 게이트 패턴이 형성될 영역에 활성 영역을 형성하지 않아 전류가 흐르지 않게 함으로써, 번인 테스트 시 게이트 산화막에 발생하는 크랙(Crack)현상을 방지하고, 패키지 번인 테스트 후 발생하는 불량을 방지하여 소자의 특성을 향상시키는 기술을 개시한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, wherein an active region is not formed in a region where a gate pattern of a bit line isolation signal (BISH) transistor of a sense amplifier region is to be formed, so that no current flows. Disclosed is a technique for preventing cracks and preventing defects occurring after a package burn-in test to improve device characteristics.

도 1a 및 도 1b는 종래 기술에 따른 반도체 소자를 도시한 레이아웃이다.1A and 1B are layouts illustrating a semiconductor device according to the prior art.

도 1a을 참조하면, 활성영역(10) 내부에 박스 인 박스 형태로 소자분리막(20)이 형성된 사각형태의 활성영역(10)이 복수개 구비된다. Referring to FIG. 1A, a plurality of quadrangular active regions 10 in which the device isolation layer 20 is formed in a box-in box form is provided inside the active region 10.

이때, 복수개의 활성영역(10) 외측 에지부를 연결하는 라인 형태(13)가 구비된다. In this case, a line shape 13 connecting the outer edges of the plurality of active regions 10 is provided.

도 1b를 참조하면, 활성영역(10) 및 소자분리막(20)의 중앙부를 지나도록 제 1 게이트(30)를 형성하고, 라인 형태(13)로 연결된 반대편에 제 2 게이트(40)를 형성한다. Referring to FIG. 1B, the first gate 30 is formed to pass through the center of the active region 10 and the device isolation layer 20, and the second gate 40 is formed on the opposite side of the line 13. .

이때, 제 1 게이트(30)는 라인 형태로 형성되고, 제 2 게이트(40)는 제 1 게이트(30)와 같은 방향인 라인 형태로(40a) 형성되되, 라인 형태(40a)와 수직하게 연결된 바 형태(40b)가 복수 개 구비되어 있으며, 바 형태(40b)는 제 2 게이트(40)와 인접한 활성영역(10)에 접속되도록 구비된다. In this case, the first gate 30 is formed in the form of a line, and the second gate 40 is formed in the form of a line 40a in the same direction as the first gate 30, but is vertically connected to the line form 40a. A plurality of bar shapes 40b are provided, and the bar shapes 40b are provided to be connected to the active region 10 adjacent to the second gate 40.

또한, 제 1 게이트(30) 및 제 2 게이트(40)는 게이트 산화막(미도시), 게이트 도전층(미도시) 및 게이트 하드마스크층(미도시)의 적층구조로 형성되며, 번인 테스트 시 활성영역 상에 전류가 흐르게 되면서 게이트 산화막에 크랙(Crack)이 발생하게 된다.In addition, the first gate 30 and the second gate 40 are formed of a stacked structure of a gate oxide layer (not shown), a gate conductive layer (not shown), and a gate hard mask layer (not shown), and are active during burn-in test. As current flows in the region, cracks are generated in the gate oxide layer.

여기서, 제 1 게이트(30)는 비트라인 분리신호(BISH)용 트랜지스터의 게이트 패턴이고, 제 2 게이트(40)는 비트라인 균등화 신호(BLEQ)용 트랜지스터의 게이트 패턴이다. Here, the first gate 30 is a gate pattern of the transistor for bit line separation signal BISH, and the second gate 40 is a gate pattern of the transistor for bit line equalization signal BLEQ.

상술한 종래 기술에 따른 반도체 소자에서, 비트라인 분리신호(BISH)용 트랜지스터의 게이트 패턴의 산화막 두께가 감소하는 경우 번인 테스트(Burn- In Test) 시 Vpp가 더욱 높아지면서 상기 비트라인 분리신호용 게이트의 전계가 증가하게 되어 상기 산화막이 깨지는 현상이 발생되며, 이로 인해 패키지(PKG) 번인 테스트 후 불량이 발생되는 문제점이 있다.In the above-described semiconductor device according to the related art, when the thickness of the oxide layer of the gate pattern of the bit line isolation signal (BISH) decreases, the Vpp becomes higher during the burn-in test, thereby increasing the voltage of the gate of the bit line isolation signal. As the electric field increases, the oxide film is broken, which causes a problem in that a defect occurs after the package PKG burn-in test.

상기 문제점을 해결하기 위하여, 센스 앰프 영역의 비트라인 분리신호(BISH)용 트랜지스터의 게이트 패턴이 형성될 영역에 활성 영역을 형성하지 않아 전류가 흐르지 않게 함으로써, 번인 테스트 시 게이트 산화막에 발생하는 크랙(Crack)현상을 방지하고, 패키지 번인 테스트 후 발생하는 불량을 방지하여 소자의 특성을 향상시키는 반도체 소자를 제공하는 것을 목적으로 한다.In order to solve the above problem, the current does not flow because the active region is not formed in the region where the gate pattern of the bit line separation signal (BISH) transistor of the sense amplifier region is to be formed, thereby preventing cracks occurring in the gate oxide layer during burn-in test ( It is an object of the present invention to provide a semiconductor device which prevents the phenomenon of cracking and improves the characteristics of the device by preventing defects occurring after the package burn-in test.

본 발명에 따른 반도체 소자는 The semiconductor device according to the present invention

센스 앰프 영역의 일측 및 타측에 제 1 활성영역 및 제 2 활성영역이 형성되되,The first active region and the second active region are formed on one side and the other side of the sense amplifier region,

상기 제 1 활성영역은 복수개의 바(Bar) 형태와 이들의 외측 에지부를 연결하는 라인(Line) 형태로 형성되고, The first active region is formed in a shape of a plurality of bars and a line connecting the outer edge thereof.

상기 제 2 활성영역은 복수개의 바 형태와 이들 중에서 이웃하는 두 개의 바 외측 에지부를 연결하는 라인 형태로 형성되고, The second active region is formed in the form of a plurality of bars and a line connecting two neighboring bar outer edges thereof.

상기 제 1 활성영역과 제 2 활성영역 사이에 제 1 게이트가 형성되고, A first gate is formed between the first active region and the second active region,

상기 제 2 활성영역의 라인 형태 외측에 제 2 게이트가 형성되되, 상기 제 2 게이트는 상기 제 1 게이트와 같은 방향의 라인 형태와 그로부터 상기 제 2 활성영역의 라인 형태 중앙부에 교차되는 바 형태가 연결되어 형성되고, A second gate is formed outside the line shape of the second active area, and the second gate is connected to a line shape in the same direction as the first gate and a bar shape intersecting with a line shape central portion of the second active area therefrom. Formed,

상기 제 1 활성영역 및 제 2 활성영역의 바 형태에 비트라인 콘택을 형성하는 것을 특징으로 한다. A bit line contact may be formed in a bar shape of the first active region and the second active region.

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

도 2a 내지 도 2c는 본 발명에 따른 반도체 소자를 도시한 레아아웃이다.2A to 2C are layouts illustrating a semiconductor device according to the present invention.

도 2a를 참조하면, 소자분리용 마스크를 이용하여 반도체 기판을 소정 깊이 식각하여 트렌치를 형성한 후 상기 트렌치를 매립하여 센스 앰프 영역의 일측 및 타측에 제 1 활성영역(115) 및 제 2 활성영역(125)을 정의하는 소자분리막(100)을 형성한다.Referring to FIG. 2A, a trench is formed by etching a semiconductor substrate using a device isolation mask to a predetermined depth, and then the trench is buried to form the first active region 115 and the second active region on one side and the other side of the sense amplifier region. A device isolation film 100 defining 125 is formed.

이때, 제 1 활성영역(115)은 복수개의 바 형태(110a)가 일렬로 형성되고, 바 형태(110a)의 외측 에지부를 연결하는 하나의 라인 형태(110b)로 형성된다. In this case, the plurality of bar shapes 110a are formed in a line, and the first active region 115 is formed in one line shape 110b connecting the outer edge portions of the bar shapes 110a.

또한, 제 2 활성영역(125)은 복수개의 바 형태(120a)가 일렬로 형성되고, 이들 중에서 이웃하는 두 개의 바 형태(120a) 외측 에지부를 연결하는 하나의 라인 형태(120b)로 형성되며, 제 2 활성영역(125)은 복수 개 구비된다.In addition, the second active region 125 is formed in a line form a plurality of bar form (120a), one line form (120b) connecting the outer edge portion of the two adjacent bar form (120a) among them, A plurality of second active regions 125 is provided.

여기서, 제 1 활성영역(115) 및 제 2 활성영역(125)은 각각 라인 형태(110b, 120b)가 외측으로 향하도록 구비되어 있다. Here, the first active region 115 and the second active region 125 are provided so that the line shapes 110b and 120b face outwards, respectively.

도 2b를 참조하면, 제 1 활성영역(115)과 복수개의 제 2 활성영역(125) 사이의 소자분리막(120) 상부에 라인 형태의 제 1 게이트(130)를 형성하여 비트라인 분리신호(BISH)용 트랜지스터의 게이트 패턴을 형성한다.Referring to FIG. 2B, a bit line separation signal BISH is formed by forming a first gate 130 having a line shape on the device isolation layer 120 between the first active region 115 and the plurality of second active regions 125. A gate pattern of the transistor.

이때, 제 1 활성영역(115)과 제 2 활성영역(125)은 제 1 게이트(130)와 소정 거리 이격되어 구비되어 있다. In this case, the first active region 115 and the second active region 125 are spaced apart from the first gate 130 by a predetermined distance.

여기서, 제 1 게이트(130)는 게이트 산화막(미도시), 게이트 도전층(미도시) 및 게이트 하드마스크층(미도시)의 적층구조로 형성되며, 상기 게이트 산화막(미도시) 하부에는 활성 영역이 형성되어 있지 않아 전류가 흐르지 않게 되므로 크랙(Crack)현상이 발생하는 것을 원천적으로 방지할 수 있다. Here, the first gate 130 is formed of a stacked structure of a gate oxide layer (not shown), a gate conductive layer (not shown), and a gate hard mask layer (not shown), and an active region below the gate oxide layer (not shown). Since the current is not flown because it is not formed, it is possible to fundamentally prevent the occurrence of cracks.

또한, 제 2 활성영역(125)의 라인 형태(120b) 외측에 제 2 게이트(137)를 형성하되, 제 2 게이트(137)는 제 1 게이트(130)와 같은 방향의 라인 형태(135a)에 제 2 활성영역(125)의 라인 형태(120b) 중앙부와 교차되는 바 형태(135b)가 연결되어 형성되는 비트라인 균등화 신호(BLEQ)용 트랜지스터의 게이트 패턴을 형성한다.In addition, a second gate 137 is formed outside the line form 120b of the second active region 125, and the second gate 137 is formed on the line form 135a in the same direction as the first gate 130. The gate pattern of the transistor for the bit line equalization signal BLEQ, which is formed by connecting the bar shape 135b that intersects with the center of the line shape 120b of the second active region 125, is formed.

도 2c를 참조하면, 제 1 활성영역(115) 및 제 2 활성영역(125)의 바 형태(110a, 120a) 제 1 게이트(125) 측 에지부에 비트라인 콘택(140)이 구비된다.Referring to FIG. 2C, a bit line contact 140 is provided at an edge portion of the first gate 125 in the bar shapes 110a and 120a of the first active region 115 and the second active region 125.

본 발명에 따른 반도체 소자는 센스 앰프 영역의 비트라인 분리신호(BISH)용 트랜지스터의 게이트 패턴이 형성될 영역에 활성 영역을 형성하지 않음으로써, 번인 테스트 시 게이트 산화막에 발생하는 크랙(Crack)현상을 방지하고, 패키지 번인 테스트 후 발생하는 불량을 방지하여 소자의 특성을 향상시키는 효과가 있다.The semiconductor device according to the present invention does not form an active region in a region where a gate pattern of a bit line isolation signal (BISH) transistor of a sense amplifier region is to be formed, thereby preventing cracks in the gate oxide layer during burn-in test. It is effective in preventing the defects occurring after the package burn-in test and improving the characteristics of the device.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (5)

센스 앰프 영역의 일측 및 타측에 제 1 활성영역 및 제 2 활성영역이 형성되되,The first active region and the second active region are formed on one side and the other side of the sense amplifier region, 상기 제 1 활성영역은 복수개의 바(Bar) 형태와 이들의 외측 에지부를 연결하는 라인(Line) 형태로 형성되고, The first active region is formed in a shape of a plurality of bars and a line connecting the outer edge thereof. 상기 제 2 활성영역은 복수개의 바 형태와 이들 중에서 이웃하는 두 개의 바 외측 에지부를 연결하는 라인 형태로 형성되고, The second active region is formed in the form of a plurality of bars and a line connecting two neighboring bar outer edges thereof. 상기 제 1 활성영역과 제 2 활성영역 사이에 제 1 게이트가 형성되고, A first gate is formed between the first active region and the second active region, 상기 제 2 활성영역의 라인 형태 외측에 제 2 게이트가 형성되되, 상기 제 2 게이트는 상기 제 1 게이트와 같은 방향의 라인 형태와 그로부터 상기 제 2 활성영역의 라인 형태 중앙부에 교차되는 바 형태가 연결되어 형성되고, A second gate is formed outside the line shape of the second active area, and the second gate is connected to a line shape in the same direction as the first gate and a bar shape intersecting with a line shape central portion of the second active area therefrom. Formed, 상기 제 1 활성영역 및 제 2 활성영역의 바 형태에 비트라인 콘택을 형성하는 것을 특징으로 하는 반도체 소자.And forming a bit line contact in a bar shape of the first active region and the second active region. 제 1 항에 있어서, The method of claim 1, 상기 제 1 활성영역 및 제 2 활성영역은 상기 제 1 게이트와 소정 거리 이격되어 구비되는 것을 특징으로 하는 반도체 소자. And the first active region and the second active region are spaced apart from the first gate by a predetermined distance. 제 1 항에 있어서, The method of claim 1, 상기 제 1 게이트 패턴은 비트라인 분리신호(BISH)용 트랜지스터의 게이트 패턴인 것을 특징으로 하는 반도체 소자. And the first gate pattern is a gate pattern of a bit line separation signal (BISH) transistor. 제 1 항에 있어서, The method of claim 1, 상기 제 2 게이트 패턴은 비트라인 균등화 신호(BLEQ)용 트랜지스터의 게이트 패턴인 것을 특징으로 하는 반도체 소자. And the second gate pattern is a gate pattern of a transistor for a bit line equalization signal (BLEQ). 제 1 항에 있어서,The method of claim 1, 상기 비트라인 콘택은 상기 제 1 게이트 측의 상기 제 1 및 2 활성 영역 에지부에 형성되는 것을 특징으로 하는 반도체 소자.And the bit line contacts are formed at edge portions of the first and second active regions on the first gate side.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010061559A (en) * 1999-12-28 2001-07-07 박종섭 FeRAM having bit line structure comprised of depletion mode transistors
KR20040027019A (en) * 2002-09-27 2004-04-01 주식회사 하이닉스반도체 Semiconductor memory device and Method for manufacturing thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010061559A (en) * 1999-12-28 2001-07-07 박종섭 FeRAM having bit line structure comprised of depletion mode transistors
KR20040027019A (en) * 2002-09-27 2004-04-01 주식회사 하이닉스반도체 Semiconductor memory device and Method for manufacturing thereof

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