KR20060135243A - Method for forming a pattern of semiconductor device - Google Patents

Method for forming a pattern of semiconductor device Download PDF

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KR20060135243A
KR20060135243A KR1020050055013A KR20050055013A KR20060135243A KR 20060135243 A KR20060135243 A KR 20060135243A KR 1020050055013 A KR1020050055013 A KR 1020050055013A KR 20050055013 A KR20050055013 A KR 20050055013A KR 20060135243 A KR20060135243 A KR 20060135243A
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film
pattern
reflection film
semiconductor device
forming
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KR1020050055013A
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Korean (ko)
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정창영
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매그나칩 반도체 유한회사
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Publication of KR20060135243A publication Critical patent/KR20060135243A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

A method for forming a pattern in a semiconductor device is provided to reduce a critical dimension difference between an upper and a lower portion of a hole by depositing an anti-reflection film which is easily removed by a developer. An anti-reflection film is applied on a semiconductor substrate with a lower layer formed therein, the anti-reflection film being removed by a developer. A photosensitive film is applied on the anti-reflection film, and then is subjected to an exposure process. The exposed photosensitive film is subjected to a developing process to form a photosensitive film pattern(13a) and simultaneously remove the anti-reflection film exposed by the formation of photosensitive film. The lower layer exposed by removing the anti-reflection film is etched.

Description

반도체 소자의 패턴 형성방법{METHOD FOR FORMING A PATTERN OF SEMICONDUCTOR DEVICE}METHODS FOR FORMING A PATTERN OF SEMICONDUCTOR DEVICE

도 1은 종래 기술에 따라 반도체 소자의 홀(hole)을 형성할 때 홀 형성부위의 상·하부 간에 발생되는 CD(Critical Dimension)차를 나타낸 SEM(Scanning Elecron Microscope) 사진.1 is a scanning electron microscope (SEM) photograph showing a CD (Critical Dimension) difference generated between upper and lower portions of a hole forming portion when forming a hole of a semiconductor device according to the related art.

도 2는 종래 기술에 의해 반도체 소자의 홀 형성시 스페이스 마진(space margin)이 감소되는 것을 보이는 SEM 사진.FIG. 2 is a SEM photograph showing that a space margin is reduced when forming a hole of a semiconductor device by a conventional technique. FIG.

도 3 내지 도 5는 본 발명의 바람직한 실시예에 따른 반도체 소자의 패턴 형성방법을 도시한 공정단면도.3 to 5 are cross-sectional views illustrating a method of forming a pattern of a semiconductor device in accordance with a preferred embodiment of the present invention.

〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

10 : 반도체 기판 11 : 하부층10 semiconductor substrate 11 lower layer

12 : 현상용 BARC 13 : 감광막12: developing BARC 13: photosensitive film

14 : 현상공정 12a : 현상용 BARC 패턴14: developing process 12a: developing BARC pattern

13a : 감광막 패턴 15 : 식각공정13a: Photosensitive Film Pattern 15: Etching Process

16 : 홀16: hole

본 발명은 반도체 소자의 패턴 형성방법에 관한 것으로, 특히 0.13㎛급 반도체 소자의 미세 컨택 홀 형성방법에 관한 것이다.The present invention relates to a method of forming a pattern of a semiconductor device, and more particularly to a method of forming a fine contact hole of a 0.13㎛ class semiconductor device.

반도체 기판 상에 형성되는 회로의 집적도가 증가함에 따라 기판 상의 개별 소자들이 미세화되고 회로의 피처 사이즈(feature size)가 감소되어 미세한 패턴 형성이 요구된다.As the degree of integration of a circuit formed on a semiconductor substrate increases, individual elements on the substrate become smaller and feature size of the circuit is reduced, so that fine pattern formation is required.

이러한, 미세 패턴 형성을 위한 통상적인 포토리소그래피(Photolithography) 공정에서는, 기판 상에 형성된 다양한 재료들로 이루어지는 다중층 위에 감광막을 도포하고 감광막의 소정 부분을 광선에 노출시킨 후, 현상 공정을 거쳐서 감광막 패턴을 형성한다. 이때, 보다 높은 해상도를 갖는 포토리소그래피 공정을 실현하기 위하여 감광막 아래에 반사방지막(BARC; Bottom Anti Reflection Coating)을 미리 형성하여 노광 공정시 발생되는 하지막으로부터의 난반사를 억제하는 것이 필수적이다. BARC 기술은 공정 마진 및 CD(Critical Dimension) 균일도(uniformity)를 개선할 수 있는 방법으로 최근에 주로 적용하고 있다.In a conventional photolithography process for forming a fine pattern, a photoresist film is applied on a multilayer of various materials formed on a substrate, and a predetermined portion of the photoresist film is exposed to light, and then subjected to a photoresist pattern through a developing process. To form. In this case, in order to realize a photolithography process having a higher resolution, it is essential to form a bottom anti reflection coating (BARC) under the photosensitive film in advance to suppress diffuse reflection from the underlying film generated during the exposure process. BARC technology has recently been applied primarily as a way to improve process margins and CD (Critical Dimension) uniformity.

BARC 기술을 사용하면 기판의 두께 차이에 의한 반사율 변화 및 불규칙한 토폴로지(topology)로 인해 발생하는 난반사를 최소화시켜 CD 균일도 개선 및 공정 마진이 향상되는 효과가 있어서 반도체 제조 공정의 막(layer)에 사용되고 있으며, 최근에는 홀(hole)을 형성하는 공정에도 BARC 기술을 채택하고 있다. 일반적으로, 홀 형성공정은 포토리소그래피 공정을 통해 패터닝된 감광막 패턴을 마스크로 이용한 식각공정을 통해 이루어진다. 이때, 감광막 하부의 BARC는 도포된 상태 그대로 남아있어 식각공정시 BARC를 먼저 식각한 후 홀이 형성될 대상물인 다중층을 식각하여아 한다.By using BARC technology, CD uniformity and process margin are improved by minimizing the reflection reflectance caused by the difference in thickness of the substrate and irregular topology, which is used in the semiconductor manufacturing process. Recently, BARC technology has been adopted in the process of forming holes. In general, the hole forming process is performed through an etching process using a photoresist pattern patterned through a photolithography process as a mask. At this time, the BARC of the lower portion of the photoresist film is left in the coated state, so that the BARC is etched first during the etching process, and then the multilayer, which is the object on which the hole is to be formed, is etched.

그러나, 상기와 같이 홀 형성을 위한 포토리소그래피 공정을 진행하게 되면 도 1에서 보는 바와 같이, 감광막의 상부(top)와 하부(bottom) 간의 CD(Critical Dimension) 차(대략, 20nm 정도)가 발생된다. 더불어, 후속으로 BARC 식각공정을 실시하게 되면 감광막 상/하부 간의 CD차(20nm)에 더하여 BARC 상/하부 간의 CD차(대략, 20nm 정도)가 발생되므로, 결국 홀 형성시 40nm 정도의 CD차가 발생된다. 따라서, 식각된 BARC를 통해 다중층을 식각하면 도 2에서 보는 바와 같이, 홀의 스페이스 마진(space margin)이 부족해지는 문제점이 유발된다.However, when the photolithography process for hole formation is performed as described above, as shown in FIG. 1, a difference in the CD (Critical Dimension) between the top and the bottom of the photoresist film (approximately, about 20 nm) is generated. . In addition, when the BARC etching process is subsequently performed, a CD difference between the upper and lower portions of the photoresist film (20 nm) is generated in addition to the CD difference between the upper and lower portions of the BARC (about 20 nm). do. Therefore, when the multilayer is etched through the etched BARC, as shown in FIG. 2, a problem of insufficient space margin of a hole is caused.

따라서, 본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, 반도체 소자의 홀 형성시 반사방지막을 별도로 식각함에 따라 CD차가 증가하는 것을 방지하여 홀의 스페이스 마진을 확보할 수 있는 반도체 소자의 패턴 형성방법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been proposed to solve the above-mentioned problems of the prior art, which prevents the CD difference from increasing by separately etching the anti-reflection film during the formation of the hole of the semiconductor device. The purpose is to provide a pattern forming method.

상기에서 설명한 목적을 달성하기 위한 일측면에 따른 본 발명은, 단층 또는 적층구조의 하부층이 형성된 반도체 기판 상에 현상공정시 사용되는 현상액에 의해 제거되는 반사방지막을 도포하는 단계와, 상기 반사방지막 상에 감광막을 도포하는 단계와, 상기 감광막에 노광공정을 실시하는 단계와, 노광된 상기 감광막에 현상공정을 실시하여 감광막 패턴을 형성하는 동시에 상기 감광막 패턴의 형성으로 인해 노출된 부분의 반사방지막을 제거하는 단계와, 상기 반사방지막이 제거되어 노출된 상기 하부층을 식각하는 단계를 포함하는 반도체 소자의 패턴 형성방법을 제공한다.According to an aspect of the present invention, there is provided a method for coating an anti-reflection film, which is removed by a developer used in a developing process, on a semiconductor substrate on which a lower layer of a single layer or a laminated structure is formed. Applying a photoresist film to the photoresist film, subjecting the photoresist film to an exposure process, and performing a developing process on the exposed photoresist film to form a photoresist pattern, and at the same time, remove the anti-reflection film exposed by the formation of the photoresist pattern. And etching the lower layer exposed by removing the anti-reflection film.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

실시예Example

도 3 내지 도 5는 본 발명의 바람직한 실시예에 따른 반도체 소자의 패턴 형성방법을 도시한 공정단면도들이다. 여기서, 도 3 내지 도 5에 도시된 참조부호들 중 서로 동일한 참조부호는 동일한 기능을 수행하는 동일 구성요소이다. 3 to 5 are process cross-sectional views illustrating a method of forming a pattern of a semiconductor device according to an exemplary embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 3 to 5 are the same components that perform the same function.

먼저, 도 3에 도시된 바와 같이, 소정 타입(type)의 반도체 기판(10) 상에 소정의 반도체 구조물층(미도시)을 개재한 하부층(11)을 형성한다. 여기서, 반도체 구조물층은 트랜지스터와 같은 복수의 능동소자와 저항, 캐패시터, 인덕터 등의 수동소자와 복수의 메모리셀과 금속배선과 금속 플러그 등을 포함한다. First, as shown in FIG. 3, a lower layer 11 is formed on a semiconductor substrate 10 of a predetermined type through a predetermined semiconductor structure layer (not shown). Here, the semiconductor structure layer includes a plurality of active elements such as transistors, passive elements such as resistors, capacitors, and inductors, a plurality of memory cells, metal wirings, metal plugs, and the like.

또한, 여기서 하부층(11)은 일종의 절연막으로 산화막 계열의 물질로 형성한다. 예컨대, 하부층(11)은 HDP(High Density Plasma) 산화막, BPSG(Boron Phosphorus Silicate Glass)막, PSG(Phosphorus Silicate Glass)막, PETEOS(Plasma Enhanced Tetra Ethyle Ortho Silicate)막, PECVD(Plasma Enhanced Chemical Vapor Deposition)막, USG(Un-doped Silicate Glass)막, FSG(Fluorinated Silicate Glass)막, CDO(Carbon Doped Oxide)막 및 OSG(Organic Silicate Glass)막 중 어느 하나를 이용하여 단층막 또는 이들이 적층된 적층막으로 형성한다.In addition, the lower layer 11 is formed of an oxide film-based material as a kind of insulating film. For example, the lower layer 11 may include an HDP (High Density Plasma) oxide film, a BPSG (Boron Phosphorus Silicate Glass) film, a PSG (Phosphorus Silicate Glass) film, a PETEOS (Plasma Enhanced Tetra Ethyle Ortho Silicate) film, and a PECVD (Plasma Enhanced Chemical Vapor Deposition) film. ) Film, USG (Un-doped Silicate Glass) film, Fluorinated Silicate Glass (FSG) film, Carbon Doped Oxide (CDO) film, and Organic Silicate Glass (OSG) film using any one layer or laminated film To form.

이어서, 하부층(11) 상에 현상용 반사방지막(또는, BARC라 함; 12)을 도포한다. 여기서, 현상용 BARC(12)란 감광막(13)의 소정 부위를 제거하기 위한 현상공정시 사용되는 현상액에 의해 감광막(13)과 함께 쉽게 제거될 수 있는 반사방지막을 말한다. 이때, 현상용 BARC(12)의 두께는 하부층(11)과의 식각 선택비(etch selectivity) 및 상기 반도체 기판(10)의 반사율(reflectivity)에 따라 결정된다.Subsequently, a developing antireflection film (or BARC) 12 is applied on the lower layer 11. Here, the developing BARC 12 refers to an antireflection film that can be easily removed together with the photosensitive film 13 by a developer used in a developing process for removing a predetermined portion of the photosensitive film 13. In this case, the thickness of the developing BARC 12 is determined according to the etch selectivity with the lower layer 11 and the reflectivity of the semiconductor substrate 10.

이어서, 경화공정(curing)을 실시하는데, 그 온도는 현상용 BARC(12)의 두께에 따라 결정된다. 이에 따라, 현상용 BARC(12)가 고체상태가 된다.Subsequently, a curing process is performed, the temperature of which is determined according to the thickness of the developing BARC 12. As a result, the developing BARC 12 is in a solid state.

이어서, 현상용 BARC(12) 상에 감광막(13)을 도포한다. 이때, 감광막(13)은 제거가 쉽도록 최소 두께로 도포한다.Next, the photosensitive film 13 is apply | coated on the developing BARC 12. At this time, the photosensitive film 13 is coated with a minimum thickness to facilitate removal.

이어서, 도 4에 도시된 바와 같이, 감광막(13, 도 3 참조)의 소정 부분을 광선에 노출시키는 노광공정을 실시한 후, 광선에 노출된 부분(또는, 광선에 노출되지 않은 부분)의 감광막(13)을 제거하기 위한 현상공정(14)을 실시한다. 이로써, 소정 부위의 감광막(13)이 제거된 감광막 패턴(13a)이 형성되는 동시에, 감광막 패 턴(13a)과 동일한 패턴의 현상용 BARC 패턴(12a)이 형성된다. 이는, 현상공정(14)시 감광막(13)과 함께 현상용 BARC(12)가 쉽게 제거되기 때문이다.Subsequently, as shown in FIG. 4, after performing an exposure step of exposing a predetermined portion of the photosensitive film 13 (see FIG. 3) to the light beam, the photosensitive film of the portion exposed to the light beam (or the portion not exposed to the light beam) ( The developing process 14 for removing 13) is performed. Thereby, the photosensitive film pattern 13a from which the photosensitive film 13 of the predetermined site was removed is formed, and the developing BARC pattern 12a of the same pattern as the photosensitive film pattern 13a is formed. This is because the developing BARC 12 is easily removed together with the photosensitive film 13 during the developing step 14.

이어서, 도 5에 도시된 바와 같이, 스트립(strip) 공정을 실시하여 감광막 패턴(13a, 도 4 참조)을 제거한다.Subsequently, as shown in FIG. 5, a strip process is performed to remove the photoresist pattern 13a (see FIG. 4).

이어서, 현상용 BARC 패턴(12a)을 식각 마스크로 이용한 식각공정(15)을 실시하여 하부층(11)을 식각한다. 이로써, 반도체 기판(10) 또는 반도체 구조물층(미도시)의 일부분을 노출시키는 홀(16)이 형성된다.Subsequently, an etching process 15 using the developing BARC pattern 12a as an etching mask is performed to etch the lower layer 11. As a result, a hole 16 exposing a portion of the semiconductor substrate 10 or a semiconductor structure layer (not shown) is formed.

즉, 본 발명의 바람직한 실시예에 의한 반도체 소자의 패턴 형성방법에 따르면, 감광막 패턴 형성을 위한 현상공정시 쉽게 제거될 수 있는 현상용 반사방지막을 증착하여 반도체 소자의 홀을 형성함으로써, 반사방지막 제거를 위한 별도의 식각공정이 불필요하게 된다. 따라서, 홀 형성부위의 상·하부 CD차를 감소시킬 수 있어 스페이스 마진을 확보할 수 있다. 이는, 반도체 소자의 수율을 증가시킬 수 있게 한다.That is, according to the method for forming a pattern of a semiconductor device according to a preferred embodiment of the present invention, by forming a hole of the semiconductor device by depositing an antireflection film for development that can be easily removed during the development process for forming a photoresist pattern, to remove the antireflection film There is no need for a separate etching process. Therefore, the CD difference between the upper and lower portions of the hole formation portion can be reduced, and a space margin can be secured. This makes it possible to increase the yield of the semiconductor device.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

이상에서 설명한 바와 같이, 본 발명에 의하면 감광막 패턴 형성을 위한 현 상공정시 사용되는 현상액에 의해 쉽게 제거될 수 있는 현상용 반사방지막을 증착하여 반도체 소자의 홀을 형성함으로써, 반사방지막 제거를 위한 별도의 식각공정이 불필요하게 된다. 따라서, 홀 형성부위의 상·하부 CD차를 감소시킬 수 있어 스페이스 마진을 확보할 수 있다. 이는, 반도체 소자의 수율을 증가시킬 수 있게 한다.As described above, according to the present invention, by depositing a development anti-reflection film that can be easily removed by the developer used in the development process for forming the photoresist pattern, forming a hole of the semiconductor device, thereby removing the anti-reflection film The etching process becomes unnecessary. Therefore, the CD difference between the upper and lower portions of the hole formation portion can be reduced, and a space margin can be secured. This makes it possible to increase the yield of the semiconductor device.

Claims (4)

단층 또는 적층구조의 하부층이 형성된 반도체 기판 상에 현상공정시 사용되는 현상액에 의해 제거되는 반사방지막을 도포하는 단계;Applying an anti-reflection film removed by a developer used in a developing process on a semiconductor substrate having a single layer or a lower layer of a laminated structure; 상기 반사방지막 상에 감광막을 도포하는 단계;Applying a photoresist film on the anti-reflection film; 상기 감광막에 노광공정을 실시하는 단계;Performing an exposure process on the photosensitive film; 노광된 상기 감광막에 현상공정을 실시하여 감광막 패턴을 형성하는 동시에 상기 감광막 패턴의 형성으로 인해 노출된 부분의 반사방지막을 제거하는 단계; 및Performing a developing process on the exposed photoresist to form a photoresist pattern, and at the same time removing the antireflection film of the portion exposed due to the formation of the photoresist pattern; And 상기 반사방지막이 제거되어 노출된 상기 하부층을 식각하는 단계Etching the exposed lower layer by removing the anti-reflection film 를 포함하는 반도체 소자의 패턴 형성방법.Pattern formation method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 반사방지막은 상기 하부층과의 식각 선택비 및 상기 기판의 반사율에 따라 그 두께가 결정되는 반도체 소자의 패턴 형성방법.The thickness of the anti-reflection film is determined according to the etching selectivity with the lower layer and the reflectance of the substrate. 제 1 항 또는 제 2 항에 있어서, The method according to claim 1 or 2, 상기 반사방지막을 도포한 후 이를 경화시키는 단계를 더 포함하는 반도체 소자의 패턴 형성방법.The method of forming a pattern of a semiconductor device further comprising the step of applying the anti-reflection film and curing it. 제 3 항에 있어서,The method of claim 3, wherein 상기 반사방지막을 경화시키는 단계는 상기 반사방지막의 두께에 따라 그 온도를 결정하는 반도체 소자의 패턴 형성방법.Curing the anti-reflection film is a pattern forming method of a semiconductor device to determine the temperature according to the thickness of the anti-reflection film.
KR1020050055013A 2005-06-24 2005-06-24 Method for forming a pattern of semiconductor device KR20060135243A (en)

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