KR20060133700A - Method for manufacturing semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to improve insulation characteristics by restraining the generation of voids using a first gate spacer with a reverse taper type structure. A plurality of gate electrodes are formed on a substrate(1). A buffer oxide layer(7) is formed along an upper surface of the resultant structure. A first nitride layer is formed on the buffer oxide layer. A first spacer(8a) with a reverse taper type structure is formed at both sidewalls of each gate electrode by etching the first nitride layer and the buffer oxide layer. A second nitride layer is formed along an upper surface of the resultant structure. A second spacer is formed at each sidewall of the first spacer by etching selectively the second nitride layer.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

FIG. 2 is a diagram illustrating the distance A between a word line bottom and a bit line contact and a depletion interference between the word line bottom and the junction region.

<Explanation of symbols for the main parts of the drawings>

1: substrate

2: gate oxide film

3: polysilicon film

4: tungsten silicide layer

5: hard mask

6: gate electrode (word line)

7: buffer oxide film

8: first nitride film

8a: first spacer

11: second nitride film

11a: second spacer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a spacer for insulating between gate electrodes of a semiconductor device of 90 nm or less class.

In general, a conductive pattern forming process of a semiconductor device such as a DRAM (Dynamic Random Access Memory) device forms a conductive pattern such as a word line or a bit line, and then forms a silicon oxide layer on the conductive pattern. do. Then, a silicon nitride film is formed on the silicon oxide film in the form of a spacer.

Hereinafter, a process of forming word lines and spacers will be described in detail.

 First, in order to improve the characteristics of the device, a stack pattern of a gate insulating film and a gate electrode is formed, and then a silicon oxide film is deposited on the stack pattern by a chemical vapor deposition (CVD) method to form a buffer oxide. After that, a nitride nitride layer and an ion implantation barrier layer are deposited on the buffer oxide layer, and then a predetermined semiconductor structure layer is formed in the peripheral circuit region of the semiconductor substrate using the ion implantation barrier layer. Then, the nitride film for spacers is used as an etch barrier, the ion implantation barrier oxide film is removed using a normal wet etching solution for oxide films, and the nitride film for spacers is etched to form a nitride film spacer on the sidewall of the buffer oxide film.

The reason why the nitride film is used as the spacer of the word line is that as the semiconductor device becomes finer, the spacer between the word lines decreases, which causes a lot of difficulty in securing insulation. Spacers are formed on both side walls of the word line to secure such insulation. Therefore, since the insulating properties between the metals must be sufficiently satisfied by the spacer of the thin film, a nitride film having excellent insulating properties and coating properties is used rather than an oxide film.

Recently, a double nitride film is used as a spacer of a word line to secure insulation characteristics. The spacer forming process using a double nitride film is a process of first depositing a gate spacer nitride film and a cell spacer nitride film sequentially, and then forming a spacer on the sidewall of the word line by simultaneously etching the gate spacer nitride film and the cell spacer nitride film.

As such, when the spacer is formed of a double nitride film, the space between word lines decreases as the degree of integration of the device is increased, and voids are generated therein during the deposition of the double nitride film. Such voids include a landing poly plug; LPP) causes an inter-pattern bridge. In addition, when the space is extremely small, there is a problem that the contact hole does not open when a landing plug contact hole (LPC) is formed.

Accordingly, the present invention has been made to solve the above problems of the prior art, has the following objects.

First of all, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving insulation characteristics by suppressing generation of voids in a manufacturing process for forming a word line spacer with a double nitride film.

In addition, another object of the present invention is to provide a method of manufacturing a semiconductor device capable of solving a problem in which a contact hole is not opened during a subsequent landing plug contact hole forming process after forming a word line spacer with a double nitride film.

In addition, the present invention is a method of manufacturing a semiconductor device that can prevent the substrate is lost by the two-etch process during the manufacturing process for forming the word line spacer with a double nitride film, the leakage current through the lost portion There is another purpose to provide.

According to an aspect of the present invention, there is provided a method including forming a substrate on which a plurality of gate electrodes are formed, forming a buffer oxide film along a step of the gate electrode, and forming a first oxide on the buffer oxide film. Forming a nitride film, etching the first nitride film and the buffer oxide film to form a first spacer having a reverse taper structure from an upper side to a lower side of the gate electrode on both sidewalls of the gate electrode; 1. A method of manufacturing a semiconductor device, comprising: depositing a second nitride film along a step of an upper portion of an entire structure including a spacer; and etching the second nitride film to form a second spacer on a sidewall of the first spacer. To provide.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

First, as shown in FIG. 1A, a gate electrode 6 serving as a word line is formed on the semiconductor substrate 1. Here, the gate electrode 6 has a laminated structure of the gate oxide film 2, the polysilicon film 3, the tungsten silicide layer 4, and the hard mask 5.

Subsequently, the buffer oxide film 7 is deposited along the step formed by the gate electrode 6. At this time, the buffer oxide film 7 is deposited by CVD.

Subsequently, a first nitride film 8, which is a gate spacer nitride film, is deposited on the buffer oxide film 7. In this case, the first nitride film 8 is deposited relatively thinly in order to suppress the generation of voids caused by the decrease of the spacers between the gate electrodes 6. Preferably deposited to a thickness of 150 ~ 250 ~.

Subsequently, as illustrated in FIG. 1B, an etching process 9 is performed to etch the first nitride film 8 (see FIG. 1A) and the buffer oxide film 7 (see FIG. 1A). At this time, the etching process 9 is carried out under the condition that a lot of polymer (polymer) is produced. As a result, the polymer is continuously produced during the etching process 9, and the polymer thus produced is continuously stacked and stacked downward from the top of the gate electrode 6. Accordingly, in the etching process 9, the first nitride film 8 is etched to have a thick reverse taper shape toward the lower portion. As a result, the width of the lower portion of the first spacer 8a is greater than the width of the upper portion from the sidewall of the gate electrode 6. Through this structure, a space between the adjacent gate electrodes 6 can be secured at the top of the gate electrode 6. As a result, the coating property may be increased during the subsequent deposition process of the second nitride film 11 (refer to FIG. 1C) to suppress the formation of voids as much as possible.

In addition, by forming the first spacer 8a in a reverse taper shape, a junction region to be formed through the bottom of the gate electrode 6 and a subsequent implant process, that is, a region opened with the gate electrode 6 (junction region) By minimizing the interference of electrons and holes in the liver, it is possible to stabilize electrical characteristics such as breakdown voltage. That is, when the gap between the bottom of the gate electrode 6 and the junction region is close, ions implanted in the junction region are diffused toward the gate electrode 6 during the heat treatment process performed after the subsequent implant process to degrade the breakdown voltage. The lower portion of the first spacer 8a is formed thick to prevent deterioration of the voltage.

For example, as in the prior art, the substrate is lost during the etching process of the double nitride film, and a leakage current is generated. Likewise, by maintaining the distance between the end of the word line, that is, the junction depletion region, the interference between the junction regions by the implant in the substrate causes unwanted degradation of breakdown voltage. In order to prevent such degradation of the breakdown voltage, a lower portion of the first spacer 8a is formed thick, and as shown in FIG. 1D, a second nitride film (I) is formed on the inner wall of the recess 13 of the substrate 1. 11) is left. As a result, it is possible to minimize electrical / hole interference between the gate electrode 6 and the open area, thereby stabilizing electrical characteristics such as a breakdown voltage.

To this end, the etching process 9 is to suppress the use of oxygen (oxygen) to suppress the production of the polymer to the maximum, using a mixed gas of a gas containing hydrogen (hydrogen) and a gas containing carbon (carbon) Do this to produce a lot of polymer. Here, H ₂ , H ₂ O, CHF ₃ , CH _4, and CH ₂ F ₂ gas are used as the gas containing hydrogen, and C ₄ F ₆ , C ₅ F _8, and C ₄ F as the gas containing carbon. _{8 Use} gas or the like. In addition, the etching process 9 uses a plasma RF power of 50 ~ 400W to continuously stack the polymer toward the bottom. As a result, the lower the etch rate of the first nitride film 8 as possible, the thicker the polymer is deposited toward the bottom. At this time, the etching rate is 10 ~ 20Å per second.

Subsequently, as illustrated in FIG. 1C, the second nitride film 11, which is a cell spacer nitride film, is deposited along the step so as to cover the first spacer 8a.

Subsequently, as illustrated in FIG. 1D, an etching process 12 is performed to etch the second nitride film 11 (see FIG. 1C). As a result, the second spacer 11a is formed on the sidewall of the first spacer 8a. At this time, the substrate 1 recessed in FIG. 1B is recessed again to a predetermined depth, and the second nitride film 11 is etched on the inner wall of the recess 13 to form a spacer 11a.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects can be obtained.

First, in the manufacturing process for forming a word line spacer with a double nitride film, the first nitride film for a gate spacer deposited after the formation of a buffer oxide film is deposited relatively thinly to increase the coating property to suppress the generation of voids to maximize insulation properties. Can be improved.

In addition, the present invention performs a process under the etching conditions that the polymer is generated a lot during the first nitride film etching process to form a first spacer in the form of a reverse taper thicker from the top to the bottom of the gate electrode to the junction region adjacent to the bottom of the gate electrode By minimizing the interference of electrons / holes between the electrical properties such as breakdown voltage can be stabilized.

In addition, the present invention can minimize the loss of the substrate by minimizing the loss of the substrate by performing the process under the etching conditions in which a lot of polymer during the first nitride film etching process.

In addition, the present invention can solve the problem that the contact hole is not opened during the subsequent landing plug contact hole forming process by securing a space between the gate electrodes by depositing the first nitride film relatively thin.

Claims (7)

Forming a substrate on which a plurality of gate electrodes are formed; Forming a buffer oxide film along a step of the gate electrode; Forming a first nitride film on the buffer oxide film; Etching the first nitride film and the buffer oxide film to form a first spacer having an inverse taper structure from an upper side to a lower side of the gate electrode on both sidewalls of the gate electrode; Depositing a second nitride film along a step of an entire structure including the first spacer; And Etching the second nitride film to form a second spacer on a sidewall of the first spacer Method of manufacturing a semiconductor device comprising a. The method of claim 1, The forming of the first spacer may be performed by using an etching process in which a large amount of polymer is produced and is stacked thicker than an upper portion of the gate electrode. The method of claim 2, The etching process is a method of manufacturing a semiconductor device using a mixed gas of a gas containing hydrogen and a gas containing carbon. The method of claim 3, wherein The hydrogen-containing gas is a method of manufacturing a semiconductor device using any one selected from the group of gas consisting of H ₂ , H ₂ O, CHF ₃ , CH ₄ and CH ₂ F ₂ gas. The method of claim 3, wherein The carbon-containing gas is a method of manufacturing a semiconductor device using any one selected from the group of gases consisting of C ₄ F ₆ , C ₅ F ₈ and C ₄ F ₈ gas. The method according to any one of claims 3 to 5, The etching process is a method of manufacturing a semiconductor device using a plasma RF power of 50 ~ 400W. The method of claim 1, The second spacer is formed on the inner wall of the substrate lost during the first spacer forming process.

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