KR20130037519A - Capacitor and method of manufacturing the same - Google Patents

Abstract

PURPOSE: A capacitor and a manufacturing method thereof are provided to prevent the generation of voids in dielectric film formation by forming a thin lower electrode in a cylinder hole. CONSTITUTION: A first sacrificial layer(110) and a second sacrificial layer(120) are formed in the upper part of a semiconductor substrate(100). A first hard mask layer(130), a second hard mask layer and a third hard mask layer are sequentially formed in the upper part of the second sacrificial layer. A photoresist pattern is formed in the upper part of the third hard mask layer. A lower electrode(190) is formed on the semiconductor substrate; and the sidewall and the upper part of the second sacrificial layer. A dielectric film(200) and an upper electrode(210) are deposited on the lower electrode.

Description

Capacitor and method of manufacturing the same

TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly, to a capacitor and a method of manufacturing the same.

In recent years, as the design rule of DRAM decreases, the cell size decreases, and accordingly, the area of the capacitor for storing information is also reduced. Accordingly, various methods for securing the capacitance of the capacitor required for the operation of the device have been proposed, such as reducing the thickness of the dielectric layer, and increasing the effective surface area of the capacitor. In addition, to increase the effective surface area of the capacitor, a method of introducing a three-dimensional storage node such as a cylinder structure, a fin structure, and a hemispherical grain (HSG: HemiSpherical Grain) structure is proposed. It is becoming.

The capacitor of the cylindrical structure forms the height of the lower electrode to about 15000 kPa or more to increase the surface area of the lower electrode. In order to secure the height of the lower electrode, a sacrificial film using a TEOS film or a PSG film and a TEOS film is formed to a thickness of 15000 Å or more. Then, the predetermined region of the sacrificial insulating layer is etched to open the region where the lower electrode is to be formed. By the way, the TEOS film is etched using plasma, and the etched region becomes narrower toward the bottom. In addition, when the PSG film and the TEOS film are stacked, the TEOS film is etched using plasma and the PSG film is etched by using an etching solution.The TEOS film becomes narrower toward the lower portion of the open area, and the PSG film has a density Due to the difference in density, the open area is widened. In addition, since the interfacial adhesion between the PSG film and the TEOS film is not good, the phenomenon of collapsing by ultrasonic waves during wet etching occurs. Also, a wet beak phenomenon occurs due to the difference in etching rate between the PSG film and the TEOS film during wet etching. The narrowing of the open area toward the lower part and the widening of the lower part of the open area form voids during the deposition of the dielectric film, which is a subsequent process, thereby reducing the reliability of the DRAM device.

On the other hand, a polysilicon film is formed thick or a Ti / TiN film is used to form a lower electrode having a low resistance in the cylinder structure. A capacitor having a cylinder structure using Ti / TiN as a lower electrode is disclosed in Korean Patent No. 10-0695497. However, in this case, the dielectric film is formed thin so that the height of the cylinder is increased again to secure an appropriate capacitance, about 15 pF or more. Therefore, a new material for the bottom electrode is needed.

The present invention provides a capacitor of a cylinder structure and a method of manufacturing the same.

The present invention provides a capacitor capable of forming a sacrificial film in a vertical profile and a method of manufacturing the same.

The present invention provides a capacitor and a method of manufacturing the same that can secure a sufficient capacitance while forming an electrode thin.

A capacitor according to an aspect of the present invention includes a sacrificial film formed on the semiconductor substrate to expose a predetermined region of the semiconductor substrate; Sidewalls and an upper portion of the sacrificial layer, and a lower electrode formed on the semiconductor substrate; And a dielectric film and an upper electrode laminated on the lower electrode, wherein the sacrificial film is formed by laminating a carbon-containing film and a silicon-containing film, and the lower electrode is formed of a graphene film.

The carbon-containing film includes an a-C: H film or a spin on carbon (SOC) film, and the silicon-containing film includes silicon oxide.

The semiconductor device may further include a seed layer formed between the sacrificial layer sidewall and the lower electrode, and the seed layer may include a silicon nitride layer.

The dielectric layer is formed of NO (Nitride-Oxide), ONO (Oxide-Nitride-Oxide), ZAZ (ZrO ₂ -Al ₂ O ₃ -ZrO ₂ ) or ZZA (ZrO ₂ -ZrO ₂ -Al ₂ O ₃ ).

A capacitor manufacturing method according to another aspect of the present invention comprises the steps of forming a sacrificial film by laminating a carbon-containing film and a silicon-containing film on a semiconductor substrate; Etching a predetermined region of the sacrificial layer to form a cylinder hole exposing the semiconductor substrate; Forming a seed film on sidewalls of the cylinder hole; Forming a graphene film on the seed film sidewalls and the semiconductor substrate; And forming a dielectric film and an upper electrode on the graphene film.

The method may further include forming a plurality of hard mask layers on the sacrificial layer, wherein the plurality of hard mask layers are formed by stacking a first silicon-containing film, a carbon-containing film, and a second silicon-containing film. The first silicon-containing film may include silicon nitride, the carbon-containing film may include a-C: H film or spin on carbon (SOC), and the second silicon-containing film may include silicon oxide or silicon nitride. The first and second silicon-containing films are etched using a fluorine-containing gas, and the carbon-containing film is etched using an oxygen-containing gas.

The carbon-containing film includes an a-C: H film or a spin on carbon (SOC) film, and the silicon-containing film includes silicon oxide. The silicon-containing film is etched using a fluorine-containing gas and the carbon-containing film is etched using an oxygen-containing gas. The silicon-containing film and the carbon-containing film are etched by generating a plasma.

The graphene film is formed using a hydrocarbon compound of CxHy, at a temperature of 1000 to 1300 ℃ or more and a pressure of 10 to 100 mTorr.

The graphene film is a capacitor formed by applying a CxHy hydrocarbon compound and applying a plasma source of 2000W to 5000W or 500W to 2000W and a bias power of 1W to 3000W at a temperature of 25 ° C to 400 ° C and a pressure of 0.5mTorr to 20mTorr. Manufacturing method.

The capacitor according to the embodiments of the present invention uses a graphene film having better resistance and conductivity than polysilicon or Ti / TiN as a lower electrode. Therefore, even if the thickness is formed thin without increasing the height of the lower electrode, sufficient capacitance can be ensured.

In addition, a sacrificial film may be formed by stacking a carbon-containing film and a silicon-containing film, and the silicon-containing film may be etched using a fluorine-containing gas and the carbon-containing film may be etched using an oxygen-containing gas to form a sacrificial film having a laminated structure in a vertical profile. . Therefore, a small cylinder hole can be formed even if the area of the cell is reduced.

As a result, a small cylinder hole can be formed, and a lower electrode can be formed thinly therein, so that voids can be suppressed when the dielectric film is formed, thereby improving the reliability of the DRAM device.

1 to 9 are cross-sectional views sequentially illustrating a capacitor manufacturing method according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. In the drawings, the thickness is enlarged to clearly illustrate the various layers and regions, and the same reference numerals denote the same elements in the drawings. In addition, if a part such as a layer, film, area, etc. is expressed as “upper” or “on” another part, each part is different from each part as well as being “right up” or “directly above” another part. This includes the case where there is another part between parts.

1 to 9 are cross-sectional views sequentially illustrating a method of manufacturing a capacitor according to an embodiment of the present invention.

Referring to FIG. 1, a first sacrificial layer 110 and a second sacrificial layer 120 are formed on a semiconductor substrate 100 on which a predetermined lower structure is formed. Transistors, bit lines, and the like are formed in the semiconductor substrate 100 to implement DRAM devices, and the transistors and the bit lines are separated by an insulating film. That is, a gate is formed on the semiconductor substrate 100, and a source and a drain are formed in the semiconductor substrate 100 on both sides of the gate electrode to manufacture a transistor. After the interlayer insulating film is formed over the entire layer including the transistor, a bit line connected to a predetermined region of the transistor, that is, a drain, is formed on the interlayer insulating film. On the other hand, the first sacrificial layer 110 is formed using a carbon film, such as an a-C: H film or a spin on carbon (SOC) film that is difficult to etch in fluorine (F) that is an etching main reactant. In addition, the second sacrificial layer 120 is formed of a material that is difficult to etch in the oxygen (O) group, which is an etching reactant used when etching the carbon layer. For example, the second sacrificial layer 120 is formed using a silicon oxide layer. Here, the first and second sacrificial films 110 and 120 are formed to have a height of the lower electrode in order to provide a region in which the cylindrical lower electrode is to be formed.

Referring to FIG. 2, the first hard mask layer 130, the second hard mask layer 140, and the third hard mask layer 150 are sequentially formed on the second sacrificial layer 120, and then over the second sacrificial layer 120. The photoresist pattern 160 is formed. The first hard mask layer 130 is formed of a material having a different etching rate from that of the first sacrificial layer 110 and an etching rate that is substantially the same as or similar to that of the second sacrificial layer 120, for example, silicon nitride. It can be formed into a film. The second hard mask layer 140 may be formed of a material having a different etching rate from the first hard mask layer 130 with respect to a specific etching reactant. For example, the second hard mask layer 140 may be formed of a carbon film such as an aC: H film or a spin on carbon (SOC). Form. In addition, the third hard mask layer 150 may be formed of a material having a different etching rate from that of the second hard mask layer 140 with respect to a specific etching reactant, for example, a silicon oxide layer or a silicon nitride layer. After the photoresist film is applied on the third hard mask layer 150, the photoresist pattern 160 is formed by patterning the photoresist film using a predetermined mask. The photoresist pattern 160 is formed to expose a region where the lower electrode of the cylinder structure is formed.

Referring to FIG. 3, the third hard mask layer 150 is etched using the photoresist pattern 160 as an etch mask. Here, the third hard mask layer 150 is etched using a material having an etch rate different from that of the second hard mask layer 140. For example, the third hard mask layer 150 is etched using SF ₆ , NF ₃ , CxFy, or CxHyFz gas. In this case, the third hard mask layer 150 may be etched by adding one or more of O ₂ , N ₂ , Ar, and He, which are plasma activation gases. That is, the third hard mask film 150 is etched by plasma-forming a fluorine-containing gas.

Referring to FIG. 4, the second hard mask layer 140 is etched using the patterned third hard mask layer 150 as an etching mask. Here, the second hard mask layer 140 is etched using a material having an etch rate different from that of the third hard mask layer 150 and the first hard mask layer 130, for example, using O ₂ or O ₃ gas. Etch it. In this case, the second hard mask layer 140 may be etched by adding one or more of N ₂ , Ar, and He, which are plasma activation gases. That is, the second hard mask layer 140 may etch the oxygen-containing gas into a plasma. At this time, the polymer-based photoresist pattern 160 is removed when the second hard mask layer 140 is etched.

Referring to FIG. 5, the first hard mask layer 130 and the second sacrificial layer 120 are etched using the patterned second hard mask layer 140 as an etching mask. Here, the first hard mask layer 130 and the second sacrificial layer 120 are etched using at least one of SF ₆ , NF ₃ , CxFy, or CxHyFz. In this case, the first hard mask layer 130 and the second sacrificial layer 120 may be etched by adding one or more of O ₂ , N ₂ , Ar, and He, which are plasma activation gases. That is, the first hard mask layer 130 and the second sacrificial layer 120 may be etched by plasma-forming a fluorine-containing gas. In this case, the third hard mask layer 150 may be removed when the first hard mask layer 130 and the second sacrificial layer 120 are etched. Meanwhile, when etching the first hard mask layer 130 and the second sacrificial layer 120, the chamber pressure is adjusted in a range of 0.5 mTorr to 20 mTorr to improve the straightness of the etching gas. In addition, the plasma source may apply a 2000W to 5000W to form a remote plasma, such as a helicon plasma, so that the semiconductor substrate 100 is not damaged by the plasma, or may use a direct plasma by applying 500W to 2000W. It may be. In addition, a bias power of 1 W to 3000 W is applied to improve the linearity of the ions decomposed by the plasma so that the semiconductor substrate 100 can react, and at this time, the substrate to further activate the reaction in the semiconductor substrate 100. The temperature is adjusted to 25 ~ 400 ℃. Here, an electrostatic chuck may be used to further improve the straightness of the ions decomposed by the plasma. That is, the process may be performed after placing the semiconductor substrate 100 on the electrostatic chuck.

Referring to FIG. 6, the first sacrificial layer 110 is etched using the patterned first hard mask layer 130 as an etching mask. Here, the first sacrificial layer 110 may be etched using O ₂ or O ₃ gas, and may be etched by adding one or more of N ₂ , Ar, and He, which are plasma activation gases. That is, the first sacrificial layer 110 may be etched by plasma-forming an oxygen-containing gas. In this way, a cylinder hole 170 for forming the lower electrode of the capacitor exposing the predetermined region of the semiconductor substrate 100 is formed. At this time, since the second sacrificial layer 120 is not etched by the oxygen-containing gas, when the first sacrificial layer 110 is etched, the second sacrificial layer 120 maintains the vertical profile. Thus, the cylinder hole 170 maintains a vertical profile. Meanwhile, the second hard mask layer 140 is removed together when the first sacrificial layer 110 is etched. In order to form the cylinder holes 170, the etching holes, ie, fluorine-containing gases are used to etch silicon-containing films, and oxygen-containing gases are used to etch the carbon-containing films. Profiles of the upper and lower portions of the can be controlled respectively, and thus can be formed into a vertical profile.

Referring to FIG. 7, the seed layer 180 is formed on the entire surface including the sidewall of the cylinder hole 170. That is, the seed film 180 is formed on the sidewall of the cylinder hole 170, the first hard mask film 130, and the semiconductor substrate 100. The seed film 180 is formed to insulate the graphene film to be subsequently grown and the sidewalls of the cylinder hole 170 and to use as a seed of the graphene film, for example, by using a silicon nitride film. Here, the substrate temperature is maintained at 700 ° C. or higher to form the seed film 180, and the deposition is performed at a low pressure of 100 mTorr or less so that the seed film 180 can be smoothly deposited to the lower side of the cylinder hole 170. SiH ₄ and NH ₃ are deposited at an appropriate ratio in an N ₂ atmosphere. In addition, to lower the deposition temperature, the chamber pressure is adjusted to 0.5 mTorr to 20 mTorr, and the plasma source may be applied to 2000 W to 5000 W to prevent the substrate from being damaged by plasma, thereby forming a remote plasma such as a helicon plasma. It is also possible to form a direct plasma by applying to 2000W. In addition, the bias power is adjusted to 1W to 3000W to improve the linearity of the ions decomposed by the plasma to react on the substrate. At this time, the substrate temperature is 25 ° C to 400 ° C to further activate the reaction on the substrate. Adjust Here, an electrostatic chuck may be used to further improve the straightness of the ions decomposed by the plasma.

Referring to FIG. 8, the seed layer 180 is blanket-etched to leave the seed layer 180 only on the sidewall of the cylinder hole 170, and the seed layer formed on the semiconductor substrate 100 and the first hard mask layer 130. Remove 180. Subsequently, the graphene film 190 used as the lower electrode of the capacitor is formed on the entire top including the seed film 180 and the first hard mask film 130. That is, the graphene film 190 is formed by seeding the seed film 180 and the first hard mask film 130. The graphene film 190 uses a hydrocarbon compound of CxHy, and when the thermal CVD process is used, the graphene film 190 is evenly formed on the sidewalls and the bottom of the cylinder hole 170 and the first hard mask film 130. In order to maintain a substrate temperature of 1000 ° C. or higher, for example, 1000 to 1300 ° C., and a chamber pressure of 100 mTorr or less, for example, 10 mTorr to 100 mTorr. In addition, when plasma CVD is used, the chamber pressure is controlled in a range of 0.5 mTorr to 20 mTorr to lower the deposition temperature, and the plasma source is applied at 2000W to 5000W to prevent plasma damage to the substrate to form a remote plasma such as a helicon plasma. Alternatively, the plasma may be applied at 500W to 2000W to form a direct plasma. In addition, the bias power is controlled in the range of 1W to 3000W to improve the linearity of the ions decomposed by the plasma so as to react on the substrate. At this time, the substrate temperature is adjusted to 25 ° C to 400 ° C to further activate the reaction in the substrate. .

Referring to FIG. 9, the dielectric film 200 is formed on the graphene film 190, and the upper electrode 210 is formed on the dielectric film 200 to fill the cylinder hole 170. The dielectric film 200 may use an oxide-based, nitride-based, or a plurality of stacked structures. For example, the dielectric film 200 includes hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₃ ), radium oxide (La ₂ O ₅ ), tantalum oxide (Ta ₂ O ₅ ), and strontium titanium oxide (SrTiO ₃ ). At least one material, but not limited to NO-Nitride-Oxide (NO), NO-Oxide-Nitride-Oxide (ONO), ZAZ (ZrO ₂ -Al ₂ O ₃ -ZrO ₂ ), or ZZA (ZrO ₂ -ZrO ₂ -Al ₂ O ₃ ) lamination can be used. In addition, the upper electrode 210 may be formed of a conductive material such as a polysilicon film or a metal film. However, the upper electrode 210 may be formed of a graphene film. In this case, the seed film may be formed on the dielectric film 200 using silicon nitride, for example, and then the graphene film may be formed. In this case, the graphene film used as the upper electrode 210 may be formed under the same conditions as the graphene film 190 used as the lower electrode.

As described above, the capacitor and the method of manufacturing the same according to the present invention can increase the capacitance while forming the lower electrode to a thin thickness by using the graphene film as the lower electrode. This is because the resistance or conductivity of the graphene film is superior to that of silicon or metal. For example, P + resistance of the doped polysilicon is ^{500 × 10 -6 Ω-㎝,} Ti / TiN, while the resistance of ^{90 ~ 300 × 10 -6 Ω-} ㎝ yes resistance of lower resistance than the metal pin, For example, it has a resistance of 35% or more lower than that of copper so that when an electron is charged in the dielectric film between the lower electrode and the upper electrode, it is charged without loss due to the resistance. Therefore, even if it is formed thinner than polysilicon or Ti / TiN, the role of the electrode is possible, and the margin of the critical dimension (CD) is high, so that not only the deposition of the dielectric film can be made smooth, but also the high deposition capacitor Can lower the height.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

100: semiconductor substrate 110, 120: first and second sacrificial films
130, 140, 150: hard mask film 160: photosensitive film pattern
170: cylinder hole 180: seed film
190: graphene film 200: dielectric film
210: upper electrode

Claims (16)

A sacrificial film formed on the semiconductor substrate to expose a predetermined region of the semiconductor substrate;
Sidewalls and an upper portion of the sacrificial layer, and a lower electrode formed on the semiconductor substrate; And
A dielectric film and an upper electrode stacked on the lower electrode;
The sacrificial film is formed by laminating a carbon-containing film and a silicon-containing film,
The lower electrode is a capacitor formed of a graphene film.
The capacitor of claim 1, wherein the carbon-containing film comprises an aC: H film or a spin on carbon (SOC) film, and the silicon-containing film comprises silicon oxide.
The capacitor of claim 1, further comprising a seed layer formed between the sacrificial layer sidewall and the lower electrode.
The capacitor of claim 3, wherein the seed layer comprises a silicon nitride layer. The method of claim 1, wherein the dielectric layer is NO (Nitride-Oxide), ONO (Oxide-Nitride-Oxide), ZAZ (ZrO ₂ -Al ₂ O ₃ -ZrO ₂ ) or ZZA (ZrO ₂ -ZrO ₂ -Al ₂ O ₃ ) formed capacitor.
The capacitor of claim 1, wherein the upper electrode is formed of polysilicon, a metal, or a graphene film.
Stacking a carbon-containing film and a silicon-containing film on the semiconductor substrate to form a sacrificial film;
Etching a predetermined region of the sacrificial layer to form a cylinder hole exposing the semiconductor substrate;
Forming a seed film on sidewalls of the cylinder hole;
Forming a graphene film on the seed film sidewalls and the semiconductor substrate;
Capacitor manufacturing method comprising the step of forming a dielectric film and the upper electrode on the graphene film.
The method of claim 7, further comprising forming a plurality of hard mask layers on the sacrificial layer.
9. The method of manufacturing a capacitor according to claim 8, wherein the plurality of hard mask films are formed by laminating a first silicon-containing film, a carbon-containing film, and a second silicon-containing film.
10. The method of claim 9, wherein the first silicon-containing film comprises silicon nitride, the carbon-containing film comprises an aC: H film or spin on carbon (SOC), and the second silicon-containing film is silicon oxide or silicon nitride. Capacitor manufacturing method comprising a.
The method of claim 10, wherein the first and second silicon-containing films are etched using a fluorine-containing gas, and the carbon-containing film is etched using an oxygen-containing gas.
The method of claim 7, wherein the carbon-containing film comprises an aC: H film or a spin on carbon (SOC) film, and the silicon-containing film comprises silicon oxide.
The method of claim 12, wherein the silicon-containing film is etched using a fluorine-containing gas and the carbon-containing film is etched using an oxygen-containing gas.
The method of claim 13, wherein the silicon-containing film and the carbon-containing film generate a plasma to be etched.
The method of claim 7, wherein the graphene film is formed using a hydrocarbon compound of CxHy at a temperature of 1000 to 1300 ° C. or higher and a pressure of 10 to 100 mTorr.
According to claim 7, wherein the graphene film using a hydrocarbon compound of CxHy, the plasma source to 2000W to 5000W or 500W to 2000W and the bias power of 1W to 3000W at a temperature of 25 ℃ to 400 ℃ and a pressure of 0.5mTorr to 20mTorr Capacitor manufacturing method to form by applying.

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