KR20060119065A - Fuse box of semiconductor devices and method for forming the same - Google Patents

Fuse box of semiconductor devices and method for forming the same Download PDF

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KR20060119065A
KR20060119065A KR1020050041609A KR20050041609A KR20060119065A KR 20060119065 A KR20060119065 A KR 20060119065A KR 1020050041609 A KR1020050041609 A KR 1020050041609A KR 20050041609 A KR20050041609 A KR 20050041609A KR 20060119065 A KR20060119065 A KR 20060119065A
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fuse
metal
line
fuses
forming
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KR1020050041609A
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KR100702303B1 (en
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최형석
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

A fuse box of a semiconductor device and a forming method thereof are provided to prevent characteristic deterioration of a fuse and a crack of the fuse due to a stress by using a metal fuse layer. A plurality of fuses(11) are arranged on a semiconductor substrate in line/space patterns. A plurality of metal fuse layers(13) are formed to overlap with one sides of an n-th line among the fuses by a predetermined distance. The plurality of metal fuse layers are formed to overlap with another sides of an (n+1)-th line among the fuses by a predetermined distance. Each of the metal fuse layers is formed by tungsten. The predetermined distance is 1/2 through 4/5.

Description

반도체소자의 퓨즈박스 및 그 형성방법{Fuse box of semiconductor devices and method for forming the same }Fuse box of semiconductor devices and method for forming the same}

도 1 및 도 2 는 본 발명의 실시예에 따른 반도체소자의 퓨즈박스 형성방법을 도시한 평면도.1 and 2 are a plan view showing a fuse box forming method of a semiconductor device according to an embodiment of the present invention.

도 3 은 상기 도 2 의 ⓐ-ⓐ 절단면을 따라 도시한 단면도.3 is a cross-sectional view taken along the line ⓐ-ⓐ of FIG. 2.

도 4 는 상기 도 2 의 ⓑ-ⓑ 절단면을 따라 도시한 단면도.4 is a cross-sectional view taken along the line ⓑ-ⓑ of FIG. 2;

본 발명은 반도체소자의 퓨즈박스 및 그 형성방법에 관한 것으로, 특히 퓨즈 블로잉 ( fuse blowing ) 을 통한 리페어 공정을 위하여 퓨즈박스를 형성할 때 상기 퓨즈박스의 에지부에서 유발되는 크랙을 방지하는 동시에 퓨즈 블로잉 공정시 이웃하는 퓨즈의 특성 열화를 방지할 수 있도록 하는 기술에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fuse box of a semiconductor device and a method of forming the same. In particular, when forming a fuse box for a repair process through fuse blowing, a fuse at the edge of the fuse box is prevented and a fuse is formed. The present invention relates to a technique for preventing the deterioration of characteristics of neighboring fuses during a blowing process.

일반적으로, 리페어 공정은 프리 리페어 테스트 ( pre repair test ), 리페어 ( Repair ), 기존 및 포스트 리페어 테스트 ( post repair test ) 등으로 진행한다. In general, the repair process includes a pre repair test, a repair, a conventional and post repair test, and the like.

상기 프리 리페어 테스트 ( pre repair test ) 공정시 페일이 발생하는 메인 셀에 대하여 퓨즈 세트의 퓨즈 블로잉을 통해 페일이 발생한 메인 셀의 어드레스를 리던던시 셀 ( redundancy cell ) 로 대체하게 된다. In the pre repair test process, an address of a main cell in which a fail occurs is replaced with a redundancy cell through fuse blowing of a fuse set for a main cell in which a fail occurs.

셀 효율성을 향상시키기 위하여 더미 퓨즈 ( dummy fuse ) 와 인에이블 퓨즈 ( enable fuse ) 를 사용하지 않는 방법을 이용하면서 로우 어드레스 ( row address ( X-Address ))를 코딩된 퓨즈 형태로 대체되도록 하는 방법을 이용하고 있다. In order to improve cell efficiency, row address (X-Address) can be replaced by coded fuse while using dummy and enable fuse. I use it.

도시되지 않았으나, 종래기술에 따른 반도체소자의 퓨즈박스를 설명하면 다음과 같다. Although not shown, the fuse box of the semiconductor device according to the prior art will be described.

먼저, 하부구조물이 형성된 반도체기판 상의 소정 영역에 다수의 퓨즈를 패터닝한다. First, a plurality of fuses are patterned in predetermined regions on a semiconductor substrate on which a substructure is formed.

이때, 상기 퓨즈는 셀부의 캐패시터 형성공정시 형성되는 플레이트전극 형성공정시 증착하고 후속 패터닝 공정으로 형성한 것으로, 다수의 퓨즈가 라인/스페이스 형태로 형성된 것이다. In this case, the fuse is deposited during the plate electrode forming process formed during the capacitor forming process of the cell unit and formed by a subsequent patterning process, and a plurality of fuses are formed in a line / space form.

그 다음, 전체표면상부에 제1층간절연막을 형성하고 이를 통한 비아콘택플러그로 상기 퓨즈에 접속되는 제1금속배선을 형성한다. Then, a first interlayer insulating film is formed over the entire surface, and a first metal wiring connected to the fuse is formed by via contact plugs.

그리고, 전체표면상부에 제2층간절연막을 형성한다. 이때, 상기 제2층간절연막은 상기 제1금속배선 상부를 완전히 도포할 수 있는 두께로 증착하여 형성한 것이다. Then, a second interlayer insulating film is formed over the entire surface. In this case, the second interlayer insulating film is formed by depositing a thickness capable of completely coating the upper portion of the first metal wiring.

그 다음 상기 제1금속배선에 제2금속배선을 콘택시키기 위한 비아 콘택 플러그를 형성한다. A via contact plug is then formed in the first metal wiring to contact the second metal wiring.

이때, 상기 비아콘택플러그는 비아콘택마스크를 이용한 사진식각공정으로 상기 제2층간절연막을 식각하여 형성한 것이다. In this case, the via contact plug is formed by etching the second interlayer insulating layer by a photolithography process using a via contact mask.

그 다음, 상기 제2비아콘택플러그에 접속되는 제2금속배선을 형성함으로써 상기 퓨즈의 바깥쪽을 완전히 감싸는 가아드링 ( guard ring )을 형성한다. Next, a guard ring is formed to completely surround the outer side of the fuse by forming a second metal wiring connected to the second via contact plug.

그리고, 전체표면상부에 제3층간절연막을 형성하고 마스크를 이용한 식각공정으로 상기 퓨즈들이 구비되는 영역인 퓨즈박스 영역 상측의 제3,2,1층간절연막을 식각하여 퓨즈박스를 형성한다. In addition, a third interlayer insulating film is formed on the entire surface, and a third, second and first interlayer insulating film on the upper side of the fuse box region, which is an area where the fuses are provided, is etched using a mask to form a fuse box.

이때, 상기 제3,2,1층간절연막의 식각공정은 상기 퓨즈 상측에 소정두께의 제1층간절연막이 남도록 실시한다.In this case, the etching process of the third, second and first interlayer insulating films may be performed such that a first interlayer insulating film having a predetermined thickness remains on the fuse.

그러나, 상기 퓨즈박스 외측의 적층구조를 이루는 각 층간의 스트레스로 인하여 상기 퓨즈박스의 에지부에 크랙이 유발되어 퓨즈가 단선되는 현상이 발생되고 그에 따른 반도체소자의 리페어 공정을 어렵게 하는 문제점이 있다. However, due to the stress between the layers forming the laminated structure on the outer side of the fuse box, cracks are caused at the edges of the fuse box, causing the fuse to be disconnected, thereby making it difficult to repair the semiconductor device.

또한, 레이저 빔을 이용한 블로잉 공정시 이웃하는 퓨즈의 특성이 변화되거나 열화되는 현상이 발생되어 그에 따른 반도체소자의 리페어 공정을 어렵게 하는 문제점이 있다. In addition, there is a problem in that the blowing process using the laser beam changes or deteriorates the characteristics of neighboring fuses, thereby making it difficult to repair the semiconductor device.

본 발명은 상기한 종래기술에 따른 문제점을 해결하기 위하여, The present invention to solve the above problems according to the prior art,

라인/스페이스 형태를 갖는 다수의 퓨즈 상에 일측 및 타측에 번갈아 중첩되도록 배열되어 이웃하는 금속층이 구비되는 구조로 레이저 빔을 이용한 퓨즈 블로잉 공정시 이웃하는 퓨즈의 특성 열화를 방지하고 스트레스에 의한 퓨즈의 크랙 유 발을 방지할 수 있도록 하는 반도체소자의 퓨즈박스 및 그 형성방법을 제공하는데 그 목적이 있다. It is arranged to alternately overlap one side and the other side on a plurality of fuses having a line / space form and has a neighboring metal layer. This prevents deterioration of characteristics of neighboring fuses during a fuse blowing process using a laser beam and prevents the fuse from being stressed. It is an object of the present invention to provide a fuse box of a semiconductor device and a method of forming the same that can prevent crack induction.

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 퓨즈박스는, In order to achieve the above object, the fuse box of the semiconductor device according to the present invention,

반도체기판 상에 라인/스페이스 형태로 구비되는 다수의 퓨즈와,A plurality of fuses provided in the form of line / space on the semiconductor substrate,

상기 퓨즈 중에서 n 번째 라인 일측으로부터 소정길이로 중첩되어 구비되는 금속 퓨즈층과, ( 단, n 은 자연수 ) A metal fuse layer provided to overlap a predetermined length from one side of an n-th line among the fuses, where n is a natural number

상기 퓨즈 중에서 n+1 번째 라인 타측으로부터 소정길이로 중첩되어 구비되는 금속 퓨즈층과, ( 단, n 은 자연수 ) A metal fuse layer provided to overlap a predetermined length from the other side of the n + 1th line among the fuses, where n is a natural number

상기 금속 퓨즈층은 텅스텐으로 형성된 것과,The metal fuse layer is formed of tungsten,

상기 소정깊이는 1/2 ∼ 4/5 인 것을 특징으로 한다. The predetermined depth is characterized in that 1/2 to 4/5.

또한, 이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 퓨즈박스 형성방법은, In addition, the method for forming a fuse box of a semiconductor device according to the present invention in order to achieve the above object,

하부구조물이 형성된 반도체기판에 폴리실리콘으로 다수의 퓨즈를 패터닝하는 공정과,Patterning a plurality of fuses with polysilicon on the semiconductor substrate on which the substructure is formed;

상기 퓨즈 상측의 금속배선 형성공정시 사용되는 콘택플러그 형성공정으로 상기 퓨즈에 중첩되는 금속 퓨즈층을 형성하되, Forming a metal fuse layer overlapping the fuse by a contact plug forming process used in the metal wiring forming process above the fuse;

상기 금속 퓨즈층은 상기 퓨즈 중에서 n 번째 라인 일측으로부터 소정길이로 중첩되어 형성되며 n+1 번째 라인 타측으로부터 소정길이로 중첩되어 형성되는 공정을 포함하는 것과, ( 단, n 은 자연수 ) The metal fuse layer includes a step of overlapping a predetermined length from one side of the n-th line of the fuse and overlapping a predetermined length from the other side of the n + 1th line, provided that n is a natural number.

상기 소정깊이는 1/2 ∼ 4/5 인 것과,The predetermined depth is 1/2 to 4/5,

상기 금속 퓨즈층의 형성공정후 금속배선 형성공정 및 사진식각공정으로 퓨즈영역을 형성하는 공정을 더 포함하는 것을 특징으로 한다. And forming a fuse region by a metal wiring forming process and a photolithography process after the forming process of the metal fuse layer.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1 및 도 2 는 본 발명의 실시예에 따른 반도체소자의 퓨즈박스 형성방법을 도시한 평면도이다. 1 and 2 are plan views illustrating a fuse box forming method of a semiconductor device according to an exemplary embodiment of the present invention.

도 1 을 참조하면, 하부구조물이 형성된 반도체기판(미도시) 상의 소정 영역에 라인/스페이스 형태를 갖는 다수의 퓨즈(11)를 패터닝한다. Referring to FIG. 1, a plurality of fuses 11 having a line / space shape are patterned in a predetermined area on a semiconductor substrate (not shown) on which a lower structure is formed.

이때, 상기 퓨즈(11)는 셀부의 캐패시터 형성공정시 형성되는 플레이트전극(미도시) 형성공정시 증착하고 후속 패터닝 공정으로 형성한 것으로, 플레이트전극 물질인 폴리실리콘으로 형성된 것이다. In this case, the fuse 11 is formed by a plate electrode (not shown) formed during the capacitor forming process of the cell unit and formed by a subsequent patterning process. The fuse 11 is formed of polysilicon, which is a plate electrode material.

도 2 를 참조하면, 전체표면상부에 제1층간절연막(미도시)을 형성하고 이를 통하여 하부구조물에 접속되는 비아콘택플러그(미도시)를 형성한다. Referring to FIG. 2, a first interlayer insulating film (not shown) is formed on the entire surface, and a via contact plug (not shown) connected to the lower structure is formed thereon.

동시에, 상기 퓨즈(11)의 상측에 상기 비아콘택플러그를 형성하는 방법으로 금속 퓨즈층(13)을 패터닝한다. 여기서, 상기 금속 퓨즈층(13)은 텅스텐으로 형성한 것이다. At the same time, the metal fuse layer 13 is patterned by forming the via contact plug on the fuse 11. The metal fuse layer 13 is formed of tungsten.

이때, 상기 금속 퓨즈층(13)은 다수의 라인/스페이스 퓨즈(11) 중에서 ( n ) ( n 은 자연수 ) 번째의 퓨즈의 일측으로부터 1/2 ∼ 4/5 만큼 중첩되고, ( n+1 ) ( n 은 자연수 ) 번째 퓨즈의 타측으로부터 1/2 ∼ 4/5 만큼 중첩되도록 형성하여, 폴리실리콘으로 형성된 퓨즈가 서로 이웃하지 않는 평면구조를 갖도록 한다. In this case, the metal fuse layer 13 is overlapped by 1/2 to 4/5 from one side of the (n) (n is a natural number) th fuse among the plurality of line / space fuses 11, and (n + 1) (n is a natural number) so as to overlap by 1/2 to 4/5 from the other side of the fuse, so that the fuse formed of polysilicon has a planar structure that does not neighbor each other.

후속 공정으로, 제1금속배선(미도시), 제2층간절연막(미도시), 제2금속배선(미도시) 및 보호막인 제3층간절연막(미도시)을 형성한 다음, 마스크를 이용한 사진식각공정으로 퓨즈박스(미도시)를 형성한다. In a subsequent process, a first interlayer dielectric layer (not shown), a second interlayer dielectric layer (not shown), a second interlayer dielectric layer (not shown) and a third interlayer dielectric layer (not shown) as a protective film are formed, and then photographs using a mask. A fuse box (not shown) is formed by an etching process.

도 3 은 상기 도 2 의 ⓐ-ⓐ 절단면을 따라 도시한 단면도로서, 퓨즈(11)와 금속 퓨즈층(13)만을 도시한 것이다. 3 is a cross-sectional view taken along the line ⓐ-ⓐ of FIG. 2, showing only the fuse 11 and the metal fuse layer 13.

도 4 는 상기 도 2 의 ⓑ-ⓑ 절단면을 따라 도시한 단면도로서, 하나의 퓨즈(11)를 장축 방향으로 절단하여 도시한 것이다. 4 is a cross-sectional view taken along the line ⓑ-ⓑ of FIG. 2, and shows one fuse 11 cut along the major axis.

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 퓨즈박스 및 그 형성방법은, 플레이트전극용 폴리실리콘으로 형성되는 퓨즈 상에 중첩되도록 금속 퓨즈층이 구비되되, 폴리실리콘이 서로 이웃하지 않도록 금속 퓨즈층이 구비되어 레이저 빔을 이용한 블로잉 공정시 이웃하는 퓨즈의 특성 열화를 방지하고 스트레스에 의한 퓨즈의 크랙을 방지할 수 있도록 함으로써 반도체소자의 리페어 공정을 용이하게 실시할 수 있도록 하는 효과를 제공한다. As described above, the fuse box and the method of forming the semiconductor device according to the present invention include a metal fuse layer so as to overlap on a fuse formed of polysilicon for plate electrodes, and the metal fuse layer so that the polysilicon does not neighbor each other. This is provided to prevent the deterioration of the characteristics of the neighboring fuse during the blowing process using the laser beam and to prevent the crack of the fuse due to the stress to provide an effect to facilitate the repair process of the semiconductor device.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (6)

반도체기판 상에 라인/스페이스 형태로 구비되는 다수의 퓨즈와,A plurality of fuses provided in the form of line / space on the semiconductor substrate, 상기 퓨즈 중에서 n 번째 라인 일측으로부터 소정길이로 중첩되어 구비되는 금속 퓨즈층과, A metal fuse layer provided to overlap a predetermined length from one side of an n-th line among the fuses; 상기 퓨즈 중에서 n+1 번째 라인 타측으로부터 소정길이로 중첩되어 구비되는 금속 퓨즈층을 특징으로 하는 반도체소자의 퓨즈박스. ( 단, n 은 자연수 ) The fuse box of the semiconductor device, characterized in that the metal fuse layer is provided to overlap a predetermined length from the other side of the n + 1th line. Where n is a natural number 제 1 항에 있어서,The method of claim 1, 상기 금속 퓨즈층은 텅스텐으로 형성된 것을 특징으로 하는 반도체소자의 퓨즈박스.The fuse box of the semiconductor device, characterized in that the metal fuse layer is formed of tungsten. 제 1 항에 있어서,The method of claim 1, 상기 소정깊이는 1/2 ∼ 4/5 인 것을 특징으로 하는 반도체소자의 퓨즈박스.The predetermined depth is a fuse box of a semiconductor device, characterized in that 1/2 to 4/5. 하부구조물이 형성된 반도체기판에 폴리실리콘으로 다수의 퓨즈를 패터닝하는 공정과,Patterning a plurality of fuses with polysilicon on the semiconductor substrate on which the substructure is formed; 상기 퓨즈 상측의 금속배선 형성공정시 사용되는 콘택플러그 형성공정으로 상기 퓨즈에 중첩되는 금속 퓨즈층을 형성하되, Forming a metal fuse layer overlapping the fuse by a contact plug forming process used in the metal wiring forming process above the fuse; 상기 금속 퓨즈층은 상기 퓨즈 중에서 n 번째 라인 일측으로부터 소정길이로 중첩되어 형성되며 n+1 번째 라인 타측으로부터 소정길이로 중첩되어 형성되는 공정을 포함하는 것을 특징으로 하는 반도체소자의 퓨즈박스 형성방법. ( 단, n 은 자연수 ) And the metal fuse layer is formed by overlapping a predetermined length from one side of an n-th line among the fuses and overlapping a predetermined length from the other side of the n + 1th line. Where n is a natural number 제 4 항에 있어서, The method of claim 4, wherein 상기 금속 퓨즈층의 형성공정후 금속배선 형성공정 및 사진식각공정으로 퓨즈영역을 형성하는 공정을 더 포함하는 것을 특징으로 하는 반도체소자의 퓨즈박스 형성방법.And forming a fuse region by a metal wiring forming process and a photolithography process after the forming of the metal fuse layer. 제 4 항에 있어서,The method of claim 4, wherein 상기 소정깊이는 1/2 ∼ 4/5 인 것을 특징으로 하는 반도체소자의 퓨즈박스 형성방법.And a predetermined depth is 1/2 to 4/5.
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