KR20060113294A - Method for forming a metal line in semiconductor device - Google Patents

Abstract

A method for forming a metal interconnection in a semiconductor device is provided to stably form a metal interconnection made of a low dielectric layer regardless of ashing damage in a photoresist ashing process, by burying a metal layer in a via hole and/or a trench so that a metal interconnection is formed, by eliminating a low dielectric layer damaged by selective ashing and by re-depositing a new low dielectric layer in a portion from which the low dielectric layer is removed. An etch stop layer(111) and a first insulation layer are sequentially deposited on a substrate(110). The first insulation layer is etched by a photolithography process to form a hole. A metal interconnection is formed to fill the hole. The first insulation layer is selectively wet-etched by using a DHF(diluted HF) solution to protrude the metal interconnection. A second insulation layer is formed in a portion from which the first insulation layer is eliminated.

Description

METHOD FOR FORMING A METAL LINE IN SEMICONDUCTOR DEVICE

1A and 1B are cross-sectional photographs of a scanning electron microscope (SEM) cross-sectional view illustrating a collapse of a low dielectric film generated when a metal wiring formation method of a semiconductor device according to the related art is applied.

2A to 2G are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to a preferred embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

110: substrate

111, 118: etch stop film

112, 117, 119, 124: IMD film

113, 120: barrier metal layer

114: lower wiring

115, 122: damaged area

121: upper wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices using a porous low dielectric film having a low dielectric constant.

Recently, various researches are underway to reduce signal propagation delays centering on logic devices requiring high integration and high performance among semiconductor devices. This is because the speed of the high density chip is determined by the RC time delay on the high density chip, where 'R' is the wiring resistance and 'C' is the capacitance of the insulating film. Speed up. This requires the development of low resistance conductors and the development of materials with low dielectric constants.

In the case of a conductor is required to replace the existing aluminum to a copper conductor, copper has been known to have a much higher electrical conductivity than aluminum. However, in the case of copper, vacuum deposition and dry etching have been difficult, and thus it has not been used in the semiconductor process. However, recently, copper has been used as a wiring material by using an electroplating technique and a buried process. In addition, MCM (Multi-Chip-Module) or logic chip manufacturing can improve performance.

In this copper wiring process with this background, semiconductor low dielectric materials should be accompanied at the same time. Copper conductors can improve the performance of devices by about 50%, and ultra low dielectric materials can improve device performance by more than 40%. The SEMATECH research report reveals that this can be done. Materials with low dielectric constants have a low dissipation factor and high breakdown voltage over a wide frequency range, which can contribute to increased circuit density and higher system speed. In this case, we start from a theoretical background where the signal propagation rate is inversely proportional to the square root of the dielectric constant. Signal transmission speed (V, m / sec) can be represented by the following equation (1).

Where 'c' is 3,108m / sec and 'ε' is the dielectric constant.

In addition, the use of low dielectric constant materials can reduce cross-talk and thus increase circuit density. This enables high integration and miniaturization, which can ultimately lead to cost reductions and dramatic improvements in chip performance.

As a low dielectric constant material, a carbon-containing SiOC film is widely used. However, the carbon in the SiOC film reacts with oxygen radicals by the O ₂ plasma used in the photoresist ashing process, that is, the strip process for removing the photoresist pattern after the etching process, so that the carbon is lost. In addition, as the dielectric constant increases, the low dielectric film collapses as shown in FIGS. 1A and 1B.

1A is a SEM cross-sectional view of a semiconductor device before an ashing process, and FIG. 1B is a SEM cross-sectional picture after an ashing process. As shown in FIG. 1A, it can be seen that the low dielectric film 10 is stably formed without collapsing between the copper wirings 12 before the ashing process. However, as shown in FIG. 1B, the low dielectric film is shown after the ashing process. It can be seen that (10) collapsed as in the 'A' site. Meanwhile, '11' is a barrier metal layer.

In order to prevent the collapse of the low dielectric film due to carbon loss, He / N ₂ and H ₂ / N ₂ plasma are used instead of O ₂ plasma in the ashing process. However, in this case, not only the existing gas supply line installed in the chamber needs to be replaced, but also there is a limit in completely preventing damage to the SiOC film. In addition, some carbon atoms are lost by the plasma reaction. In particular, as the porous low dielectric film becomes larger, the loss becomes larger, which means that the low dielectric film becomes porous, so that the density becomes smaller, and the area exposed to the plasma becomes wider. Because it is falling apart.

Accordingly, the present invention has been proposed to solve the above problems, and provides a method for forming metal wirings of a semiconductor device capable of forming metal wirings stably using a low dielectric film regardless of damage caused by ashing during a photoresist ashing process. Its purpose is to.

According to an aspect of the present invention, there is provided a method including sequentially depositing an etch stop layer and a first insulating layer on a substrate, and forming holes by etching the first insulating layer through a photolithography process. Forming a metal wiring so as to fill the hole, selectively etching away the first insulating film to protrude the metal wiring, and forming a second insulating film at a portion where the first insulating film is removed. It provides a method for forming metal wiring of a semiconductor device comprising a.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

Example

2A to 2G are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device in accordance with a preferred embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 2A to 2G are the same components having the same function.

First, referring to FIG. 2A, a semiconductor substrate 110 having a predetermined semiconductor structure layer (not shown) is provided. The semiconductor structure layer may include a transistor, a memory cell, a capacitor, a junction layer, a conductive layer, a wiring, and the like.

Subsequently, an etch stop layer 111 is deposited on the substrate 110. In this case, the etch stop layer 111 may be formed of a single layer or a stack of any one of Ta, TaN, TaC, TaAlN, TaSiN, TaSi ₂ , Ti, TiN, TiSiN, WN, WBN, WC, Co, and CoSi ₂ . They are deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD).

Next, an intermetal dielectric (IMD) film 112 is formed on the etch stop film 111. At this time, the IMD film 112 is a carbon doped oxide (CDO), an ultra low dielectric film (k <3.0) or a porous film containing carbon (HSSQ (Hydro silsesquioxane) film or MSSQ (Methyl silsesquioxane) film) To form. The ultra low dielectric film, the HSSQ film, and the MSSQ film may be a low dielectric film formed by a spin on method, for example, the low dielectric film may be a SiOC film. In addition, a thermal oxide film containing carbon or a Tetra Ethyle Ortho Silicate (TEOS) film may be used. The IMD film 112 is formed as a single film using the film described above, or a complex structure in which the film is stacked at least two or more layers.

Subsequently, the IMD film 112 may be cured at a temperature range of at least 400 ° C or higher.

Subsequently, the IMD film 112 may be planarized through a planarization process. In this case, the planarization process may be performed by a chemical mechanical polishing (CMP) method.

Subsequently, a dual damascene process or a single damascene process is performed to etch the IMD film 112 to form via holes or trenches (not shown). Hereinafter, for convenience of description, it will be referred to as a trench.

The dual damascene process or the single damascene process is carried out using a photolithography process, in which the inner wall of the trench is shown as '115' during the ashing process to remove the photoresist pattern (not shown) used as an etch mask. Damaged areas are formed in each of the ashing. On the other hand, the ashing process is performed using O ₂ , He / N ₂ or H ₂ / N ₂ plasma.

Subsequently, the barrier metal layer 113 is deposited along the steps of the entire top surface of the trench. At this time, the barrier metal layer 113 is used to prevent diffusion of copper atoms by subsequent thermal processes, or to increase the contact force between them when the underlying layer is a metal layer, such as Ta, TaN, TaC, TaAlN, TaSiN, TaSi ₂ , Ti, TiN, It is formed by a single layer or lamination using any one of TiSiN, WN, WBN, WC, Co and CoSi ₂ . They are deposited by PVD, CVD or ALD methods.

Subsequently, a seed layer (not shown) is formed on the barrier metal layer 113. At this time, the seed layer is a copper and copper alloy film produced by PVD, CVD or ALD method, wherein the copper alloy film is Mg, Sn, Al, Pd, Ti, Nb, Hf, Zr, Sr, Mn, Cd, Zn or Ag And the like.

Subsequently, a copper layer is deposited over the entire structure where the seed layer is formed so that the trench is embedded. In this case, the copper layer may be formed by CVD, ALD or electroless plating in addition to the electroplating method.

Next, a CMP process is performed to planarize the copper layer. As a result, an isolation lower wiring 114 is formed in the trench. Here, the lower wiring 114 may be formed of any conductive material such as Al, W, Pt, or the like instead of the copper metal.

Subsequently, as illustrated in FIG. 2B, the wet etching process 116 using DHF (Diluted HF, H ₂ 0: HF in a ratio of 500: 1 or 200: 1) is performed to selectively remove the IMD film 112. Remove As a result, the etch stop layer 111 is exposed and the barrier metal layer 113 is exposed.

Next, as shown in FIG. 2C, the IMD film 117 is deposited to cover the entire structure including the exposed barrier metal layer 113, that is, the protruding lower interconnect 114. In this case, the IMD film 117 is formed by the same method using the same material as the IMD film 112 (see FIG. 2A).

Subsequently, an entire surface etching process such as a CMP process or an etch back process is performed to etch planarize the IMD film 117. As a result, the upper surface of the lower wiring 114 is exposed.

Subsequently, as shown in FIG. 2D, an etch stop layer 118 is deposited over the entire planarized structure. In this case, the etch stop layer 118 is formed of the same material as the etch stop layer 111.

Next, as shown in FIG. 2E, an IMD film 119 is deposited on the etch stop layer 111. At this time, the IMD film 119 is formed in a single layer or stacked using the same film as the IMD film 117.

Subsequently, a dual damascene process is performed in a pre-via or post-via manner to form via holes (not shown) and trenches (not shown). On the other hand, '122' is a damage region formed in the inner wall of the trench and the via hole during the ashing process performed during the dual damascene process.

The barrier metal layer 120 is then deposited along the steps of the top surface of the entire structure where trenches and via holes are formed. In this case, the barrier metal layer 120 is formed of the same material as the barrier metal layer 113.

Subsequently, after forming the seed layer on the barrier metal layer 120, a copper layer is deposited on the entire structure where the seed layer is formed so as to completely fill the trench and the via hole, and the copper layer is planarized by performing a CMP process. As a result, an upper wiring 121 is formed inside the trench.

Subsequently, as shown in FIG. 2F, a wet etching process 123 using DHF (Diluted HF, H ₂ 0: HF in a ratio of 500: 1 or 200: 1) is performed to selectively perform IMD film 119 (FIG. 2e). As a result, the etch stop layer 118 is exposed and the barrier metal layer 120 is exposed.

Next, as shown in FIG. 2G, an IMD film 124 is deposited to cover the entire structure structure including the exposed barrier metal layer 120, that is, the protruding upper wiring 121. In this case, the IMD film 124 is formed by the same method using the same material as the IMD film 112 (see FIG. 2A).

Subsequently, an entire surface etching process such as a CMP process or an etch back process is performed to etch planarize the IMD film 124.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, a metal layer is embedded in a via hole and / or trench to form a metal wiring, and selectively removes the low dielectric film damaged by ashing, and then removes a new low By re-depositing the dielectric film, metal wiring can be formed using the low dielectric film stably regardless of damage caused by ashing during the photoresist ashing process.

Claims (8)

Sequentially depositing an etch stop layer and a first insulating layer on the substrate; Etching the first insulating layer through a photolithography process to form a hole; Forming metal wirings to fill the holes; Selectively etching away the first insulating layer to protrude the metal wiring; And Forming a second insulating film on a portion where the first insulating film is removed; Metal wiring forming method of a semiconductor device comprising a. The method of claim 1, The first insulating layer is a metal wiring forming method of a semiconductor device to remove by performing a wet etching process using a DHF solution. The method according to claim 1 or 2, And the first and second insulating layers are formed of a porous HSSQ film or an MSSQ film. The method of claim 3, wherein And the first and second insulating layers are cured at a temperature of at least 400 ° C. 9. The method of claim 1 or 2, wherein the forming of the metal wire is performed. Depositing a barrier metal layer along a step on top of the entire structure formed by the holes; Depositing a metal material to fill the hole; And Planarizing the metal material and the barrier metal layer Metal wiring forming method of a semiconductor device comprising a. The method of claim 1 or 2, wherein the forming of the second insulating film, Depositing the second insulating film on an entire structure including a portion from which the first insulating film is removed; And Planarizing the second insulating layer to expose an upper portion of the metal wiring; Metal wiring forming method of a semiconductor device comprising a. The method of claim 6, The planarization process is a metal wiring formation method of a semiconductor device performed by a CMP process or an etch back process. The method according to claim 1 or 2, The hole is a metal wiring forming method of a semiconductor device formed by a dual damascene or a single damascene process.

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