KR20060107689A - Programming method of non-volatile memory device having multi-level cell - Google Patents

Abstract

According to the present invention, when ISPP step voltages are adjusted differently when programming the least significant bit (LSB) and when programming the most significant bit (MSB), the multi-level of the cell program threshold voltage distribution can be narrowly adjusted without increasing the program time. A program method of a NAND flash memory device having cells.

Multi-level cells, programs, flash

Description

Programming method of non-volatile memory device having multi-level cell

1 and 2 are diagrams illustrating a threshold voltage distribution and a program method of a programmed cell of a NAND flash memory device having a conventional multi-level cell.

3 is a diagram illustrating a NAND flash memory device having multi-level cells according to a preferred embodiment of the present invention.

4 is a diagram illustrating a threshold voltage distribution and a program method of a programmed cell of a NAND flash memory device having a multi-level cell of FIG. 3.

FIG. 5 is a flowchart illustrating a program method of a NAND flash memory device having a multi-level cell of FIG. 3.

<Description of Symbols for Main Parts of Drawings>

100: memory cell array 200: page buffer

MC: memory cell DSL: drain select line

SSL: source selection line CSL: common source line

The present invention relates to a method of programming a nonvolatile memory device having a multi-level cell, and more particularly, to a method of programming a NAND flash memory device having a multi-level cell capable of narrowly adjusting a threshold voltage distribution of a programmed cell.

 Nonvolatile memory devices that can be electrically programmed and erased perform a program and erase function by changing a threshold voltage of a cell while electrons are moved by a strong electric field in a thin tunnel oxide film.

Recently developed NAND flash memory having a multi-level cell (multi-level cell), unlike the conventional single level cell (single level cell) stores two bits in one cell. However, a NAND flash memory having a multi-level cell has a very narrow threshold voltage (Vth) distribution compared to a single-level cell, which is difficult in terms of reliability and process margin. In addition, programming time and reading time are long because several states must be programmed and read out at one time.

A NAND flash memory having a multi-level cell developed in the related art performs a program using a threshold voltage distribution of four states as shown in FIGS. 1 and 2.

In the program method of the NAND flash memory device having the multi-level cells shown in FIG. 1, three programs are executed at the time of one page programming to implement a threshold voltage level of four states, and the multi-level cells shown in FIG. The NAND type flash memory device has a program method that executes two programs in one page program to implement a threshold voltage level of four states.

In the NAND flash memory device having the multi-level cells shown in Figs. 1 and 2, the threshold voltage distribution of the programmed cell is, for example, the interval between PV1 and PV1 ', the interval between PV2 and PV2', and the PV3 and PV3 '. Have a gap between them. However, when the interval between PV1 and PV1 ', the interval between PV2 and PV2', and the interval between PV3 and PV3 'become wider, the interval between PV' and PV2 and the interval between PV2 'and PV2 become narrower, resulting in cell operation. Very bad effect on reliability (difficult to set read voltages VR1, VR2, VR3). Thus, efforts are needed to reduce the threshold voltage distribution of the programmed cells.

The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a method of programming a NAND flash memory device having a multi-level cell capable of narrowly adjusting a threshold voltage distribution of a programmed cell.

In order to achieve the above object, a NAND flash memory device according to a preferred embodiment of the present invention comprises the steps of: (a) programming the least significant bit of two bits by applying a first program bias voltage to the first word line; (b) verifying a pass / fail of the program by applying a first program verify voltage to the first word line; (c) reprogramming the least significant bit of the two bits by applying a second program bias voltage to the first word line after adding the first program bias voltage to a first program bias voltage if the program is a fail; (d) performing step (b) again to read the most significant bit programmed in the memory cell of the first word line if the program is a pass; (e) programming the most significant bit of two bits by applying the first program bias voltage to a second word line; (f) verifying a pass / fail of the program by applying a second or third program verify voltage corresponding to the read most significant bit to the second word line; (g) reprogramming the least significant bit of the two bits by applying a third program bias voltage to the second word line after the first program bias voltage plus a second second voltage; And (h) performing step (f) again to terminate the program if the program is a pass.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

3 illustrates a NAND flash memory device having a multi-level cell according to a preferred embodiment of the present invention.

Referring to FIG. 3, a NAND flash memory device having a multi-level cell includes a memory cell array 100 and a page buffer 200.

The memory cell array 100 includes a plurality of memory cells MC0 to MCn, a drain select transistor DST, a source select transistor SST, N word lines WL0 to WLn, and N bit lines BL0 to BLn. ). The number of memory cells MC0 to MCn connected in series between the drain select transistor DST and the source select transistor SST is 16, 32, and 64 in consideration of devices and densities. This is called a string. The memory cells (eg, M1) are controlled by one word line WL1 and form one page P2. In the present invention, N pages P1 to Pn exist.

The page buffer 200 is used to program data in the memory cells MC0 to MCn or to read and verify data programmed in the memory cells. The page buffer 200 is connected to a pair of bit lines and provided in plurality.

4 illustrates threshold voltage distributions of programmed cells of a NAND flash memory device having multi-level cells.

As shown in Fig. 4, first, when programming page 0 (P1), only the least significant bit (LSB) of two bits is programmed (from "11" state to "10" state), and secondly, page 1 ( When programming P2), program only the most significant bit (MSB) (from "10" to "00" or from "11" to "01"). The program time takes longer when programming the most significant bit (MSB) than when programming the least significant bit (LSB). It is the time to program the most significant bit (MSB) to determine the program time of this multi-level cell. Therefore, when programming the least significant bit (LSB), the programming time is relatively short. Therefore, even if the ISPP (Incremental Step Pulse Program) step voltage, that is, the program voltage is smaller than when programming the most significant bit (MSB), the specification of the program time is required. Can be satisfied.

5 is a flow diagram illustrating a program method of a NAND flash memory device having multi-level cells.

Hereinafter, a program operation of a NAND flash memory device having a multilevel cell according to a preferred embodiment of the present invention will be described with reference to FIGS. 3 to 5. Here, a method of programming 2-bit data on pages 0 and 1 (P1 and P2) will be described.

First, when programming page 0 (P1), that is, when programming the least significant bit (LSB) 11-> 10 (S11), an ISPP stub pulse is first set (S12).

Next, the set ISPP step pulse, that is, the program voltage is applied to the word line WLO (S13), and the program data input from the outside is transferred to the selected bit line through the page buffer 200, and then transferred through the selected bit line. Program data is programmed in the corresponding memory cell MC0.

Thereafter, the program is verified using the page buffer 200 (S14), and the program is verified at the threshold voltage PV1 (0, 3V) level shown in FIG. At this time, if the memory cell is not programmed, that is, if the verification is failing, the program voltage is increased by adding about 0.15 V (0.1 V to 0.2 V) to the ISPP step pulse (S15), and the increased program voltage is reset. The word line is applied to the WLO (S12). Then, the program is re-verified at the threshold voltage level PV1 (˜0.3 V) (S13). In the same manner as described above, the program voltage is increased by 0.15V, and the program is repeatedly executed and the program is verified. At this time, if all the cells MC0 in the page 0 (P1) pass the verification at the threshold voltage PV1 level, that is, when the threshold voltage level PV1 (~ 0.3V) passes, the page 0 (P1) Program is terminated and the next page 1 (P2) is programmed.

Here, the program voltage is applied to the word line by increasing 0.15V, but this program voltage is applied to the word line as small as possible within the range of 0.1V to 0.2V. This reduces the threshold voltage distribution of the programmed cell as much as possible without exceeding the specification of the program time (about 1200us).

Next, when programming page 1, that is, when programming the most significant bits 10-> 00, 11-> 01 (S16), first read the state of the memory cell MC0 of page 0 (S17). In operation S16, it is determined whether the logic value “11” or the logic value “10” is programmed in the memory cell MC0.

Then, the ISPP step pulse is set (S18), the set ISPP step pulse, that is, the program voltage is applied to the word line WL1 of the page 1 (P2) (S19), and the program data input from the outside is transferred to the page buffer 200. Transfers to the selected bit line through the program, and program data transferred through the selected bit line to the corresponding memory cell (MC0).

Thereafter, the program is verified using the page buffer 200 (S20). At this time, the program verification is performed at the threshold voltage level PV2 (~ 1.5V) or the threshold voltage level PV3 (~ 2.7) shown in FIG. Here, when the logic value "10" is read to program the logic value "00", the program is verified at the threshold voltage level (PV2; ~ 1.5V), and the logic value "11" is read to read the logic value "01". When programming, verify the program at the threshold voltage level (PV3; ~ 2.7V).

At this time, if the memory cell is not programmed, that is, if the verification is failing, the program voltage is increased by adding a program bias of + 0.2V (0.2V to 0.3V) to the ISPP step pulse (S15), and the increased program The voltage is applied to the word line WL1 again (S19).

Then, verify the program again at the threshold voltage level (PV2; ~ 1.5V). As described above, the program voltage is increased by 0.2V to repeatedly execute the program and verify the program. At this time, if all the cells MC1 in the page 1 P2 pass the verification at the threshold voltage level PV2 (~ 1.5V), that is, when the threshold voltage level PV2 (~ 1.5V) passes, The program of page 1 (P2) ends.

In this case, when programming the most significant bit (MSB), the logic value "00" and the logic value "01" must be programmed at the same time, resulting in a very long program time. Longer time). Therefore, the program time may be reduced by applying the program voltage to the word line by increasing the program voltage in the range of 0.2V to 0.3V, which is higher than when programming the least significant bit LSB.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, if the ISPP step voltage is adjusted differently when programming the least significant bit (LSB) and when programming the most significant bit (MSB), the cell program threshold voltage distribution without increasing the program time, that is, shown in FIG. The interval between PV1 and PV ', the interval between PV2 and PV2', and the interval between PV3 and PV3 'can be narrowly adjusted. In this way, the interval between P2 'and PV3 between P1' and PV2 is reduced, so that the read voltages VR1, VR2, and V3 can be easily set, thereby improving the read margin.

As described above, according to the present invention, first, it is possible to reduce the threshold voltage distribution of a programmed cell without increasing the program time of the NAND flash memory device having a multi-level cell.

Second, as the distribution of the logic value "10" decreases, the margin between the logic value "10" and the logic value "00" increases, thereby improving reliability.

Third, program time management is facilitated through optimization of ISPP step pulses of NAND flash memory devices having multi-level cells.

Fourth, the yield of the NAND type flash memory device having a multi-level cell can be improved by improving the threshold voltage distribution of the programmed cell and improving reliability.

Claims (7)

In a NAND flash memory device having a multi-level cell, (a) programming a least significant bit of two bits by applying a first program bias voltage to the first word line; (b) verifying a pass / fail of the program by applying a first program verify voltage to the first word line; (c) reprogramming the least significant bits of the two bits by applying a second program bias voltage to the first word line, the second program bias voltage of which the first program bias voltage is added to the first program bias voltage; (d) performing step (b) again to read the most significant bit programmed in the memory cell of the first word line if the program is a pass; (e) programming the most significant bit of two bits by applying the first program bias voltage to a second word line; (f) verifying a pass / fail of the program by applying a second or third program verify voltage corresponding to the read most significant bit to the second word line; (g) reprogramming the least significant bits of the two bits by applying a third program bias voltage to the second word line, wherein the third program bias voltage is added to the first program bias voltage plus a predetermined second voltage; (h) performing the step (f) again to terminate the program if the program is a pass. The method of claim 1, Step (b) and Step (c) is repeatedly performed until the program by the first program verify voltage is passed, the program method of a non-volatile memory device having a multi-level cell. The method of claim 1, Step (f) and step (g) is repeatedly performed until the program by the second or third program verify voltage is passed, characterized in that the program method of a non-volatile memory device having a multi-level cell. The method of claim 1, In the step (f), if the read least significant bit is a logic value "11", the second program verify voltage is applied to the second word line, and if the read least significant bit is a logic value "10", the third program And applying a verify voltage to the second word line.  The method of claim 1, And wherein the first voltage is less than the second voltage. The method of claim 1, And the first voltage is in a range of 0.1 to 0.2 volts. The method of claim 1, And said second voltage is in a range of 0.2 to 0.3 volts.

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