KR20060104530A - Apparatus and method of driving plasma display panel - Google Patents

Abstract

The present invention relates to a driving apparatus for a plasma display panel and a driving method thereof capable of reducing costs by reducing the number of power supplies required for driving the plasma display panel.

The driving apparatus of the plasma display panel according to the present invention supplies a setup voltage and a scan reference voltage to the scan electrodes of the panel capacitors, and alternately supplies a positive first voltage to the scan electrodes and the sustain electrodes of the panel capacitors. A scan driver for controlling a second voltage having a polarity to be supplied to the scan electrode of the panel capacitor; And a sustain driver to alternately supply the second voltage to the scan electrode and the sustain electrode of the panel capacitor, and to control the first voltage to be supplied to the sustain electrode of the panel capacitor.

Description

Driving apparatus for plasma display panel and driving method thereof {APPARATUS AND METHOD OF DRIVING PLASMA DISPLAY PANEL}

FIG. 1 is a diagram illustrating a subfield pattern of an 8 bit default code for implementing 256 gray levels in a plasma display panel.

2 is a view showing driving waveforms of a conventional plasma display panel.

3 is a view showing a driving apparatus of a conventional plasma display panel.

4 is a diagram illustrating a driving apparatus of a plasma display panel according to an exemplary embodiment of the present invention.

FIG. 5 is a diagram illustrating a driving waveform generated by the driving apparatus shown in FIG. 4.

FIG. 6 is a diagram illustrating on / off timing of switches for forming a driving waveform shown in FIG. 5.

7 to 17 are diagrams illustrating current paths according to on / off timings of the switches illustrated in FIG. 6.

<Description of Symbols for Main Parts of Drawings>

2, 52: scan driver 4, 54: sustain driver

6: sustain pulse supply part 8, 58: setup voltage supply part

10: set down voltage supply control unit 12: scan sustain voltage supply unit

14, 64: scan reference voltage supply 16, 66: scan IC

18, 32, 68, 78: energy recovery / supply unit 20, 34: sustain voltage supply unit

22, 36, 72, 74: base voltage supply unit 60: set-down voltage supply control unit

62: scan voltage supply control unit 70: first voltage supply unit

76: second voltage supply unit 80: first voltage supply control unit

82: second voltage supply control unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a driving apparatus for a plasma display panel and a driving method thereof capable of reducing costs by reducing the number of power supplies required for driving the plasma display panel.

Plasma Display Panel (hereinafter referred to as " PDP ") is used to excite and emit phosphors using ultraviolet rays generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is discharged. Is displayed. Such PDPs are not only thin and large in size, but also have improved image quality due to recent technology development.

 FIG. 1 is a diagram illustrating a subfield pattern of an 8 bit default code for implementing 256 gray levels in a plasma display panel.

Referring to FIG. 1, the PDP performs time division driving by dividing one frame into several subfields having different emission counts in order to implement grayscale of an image. Each subfield is divided into a reset period for initializing the full screen, an address period for selecting a scan line and a discharge cell for selecting a discharge cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. Each of the eight subfields SF1 to SF8 is divided into a reset period RP, an address period AP, and a sustain period SP as described above. At this time, while the reset period RP and the address period AP of each subfield are the same for each subfield, the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2) in each subfield. 3,4,5,6,7).

2 is a diagram illustrating a conventional PDP driving waveform.

Referring to FIG. 2, each of the subfields SF includes a reset period RP for initializing the discharge cells of the full screen, an address period AP for selecting the discharge cells, and a sustain for discharging the selected discharge cells. It includes a period SP.

In the reset period RP, the rising ramp waveform PR is simultaneously applied to all the scan electrodes Y in the setup period SU. This rising ramp waveform PR causes a weak discharge (setup discharge) to occur in the cells of the full screen, thereby generating wall charges in the cells. After the rising ramp waveform PR is applied in the set-down period SD, the positive sustain voltage Vs lower than the peak voltage of the rising ramp waveform PR to the negative scan voltage Vs is negative. The falling ramp waveform NR falling at a predetermined slope is simultaneously applied to the scan electrodes Y. The falling ramp waveform NR generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges, thereby uniformly retaining wall charges required for address discharges in the cells of the full screen.

In the address period AP, a negative scan pulse SCNP is sequentially applied to the scan electrodes Y, and a positive data pulse DP is applied to the address electrodes. As the voltage difference between the scan pulse SCNP and the data pulse DP and the wall voltage generated in the reset period RP are added, an address discharge is generated in the cell to which the data pulse DP is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive sustain voltage Vs is applied to the sustain electrodes Z during the set down period SD and the address period AP.

In the sustain period SP, a sustain pulse SSUS is applied to the scan electrodes Y and the sustain electrodes Z alternately. Then, the cell selected by the address discharge is in the form of surface discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse SSUS is applied while the wall voltage and the sustain pulse SSUS in the cell are added. Sustain discharge occurs. Here, the sustain pulses SSP have the same voltage value as the sustain voltage Vs.

3 is a view showing a conventional PDP driving apparatus.

Referring to FIG. 3, a conventional PDP driving apparatus includes a panel capacitor Cp having a scan electrode Y and a sustain electrode Z, a scan driver 2 and a sustain electrode Z for driving the scan electrode Y. It includes a sustain driver (4) for driving.

The panel capacitor Cp equivalently represents the capacitance formed between the scan electrode Y and the sustain electrode Z of the PDP. The panel capacitor Cp generates sustain discharge by sustain voltages having opposite polarities.

The scan driver 2 supplies the reset pulses PR and NR as shown in FIG. 2 to the scan electrodes Y1 to Yn during the reset period RP in response to a timing control signal supplied from a timing controller (not shown). do. In addition, the scan driver 2 supplies the scan reference voltage Vsc to the scan electrodes Y1 to Yn during the address period AP, and also has a scan pulse SCNP having a negative scan voltage (-Vy). Are sequentially supplied to the scan electrodes Y1 to Yn. The scan driver 2 also has a sustain pulse susp having a sustain voltage level Vs and a ground voltage level GND during the sustain period SP in response to a timing control signal supplied from a timing controller (not shown). Is supplied to the scan electrodes Y1 to Yn. To this end, the scan driver 2 includes a sustain pulse supply unit 6, a setup voltage supply unit 8, a setdown voltage supply control unit 10, a scan sustain voltage supply unit 12, a scan reference voltage supply unit 14, and a scan integrated circuit. (Intergrated Circuit; hereinafter referred to as " IC ") 16, fifth switch SW5, and seventh switch SW7.

The sustain pulse supply unit 6 supplies a sustain pulse SUSP having a sustain voltage level Vs and a ground voltage level GND to the scan electrodes Y1 to Yn during the sustain period SP. Vs) and ground voltage GND. In addition, the sustain pulse supply unit 6 recovers energy of the reactive power that does not contribute to the discharge in the PDP from the panel capacitor Cp during the sustain period SP, and recovers the recovered energy to the scan electrodes Y1 to Yn. Supply. To this end, the sustain pulse supply unit 6 includes a first energy recovery / supply unit 18, a first sustain voltage supply unit 20, and a first base voltage supply unit 22. This sustain pulse supply unit 6 is used as an energy recovery circuit.

The first energy recovery / supply unit 18 recovers energy of reactive power that does not contribute to discharge in the PDP from the panel capacitor Cp and supplies the recovered energy to the panel capacitor Cp during the sustain period SP. . The first energy recovery / supply unit 18 may include a source capacitor Cs, a source capacitor Cs and the first sustain voltage supply unit 20, and a first base voltage supply unit 22 for storing the recovered energy. Inductor L connected between second node N2, between source capacitor Cs and inductor L to form a current path for supplying energy stored in source capacitor Cs to panel capacitor Cp. The first diode SW1 and the first diode D1 connected in series to the first diode D1 to form a current path for recovering energy of reactive power not contributing to the discharge from the panel capacitor Cp. And a second diode (D2) and a second switch (SW2) connected in series between the first node (N1) and the source capacitor (Cs) between the and inductor (L).

The first sustain voltage supply unit 20 supplies the sustain voltage Vs to the scan electrode Y of the panel capacitor Cp during the setup period SU during the reset period RP, and also sustain voltage during the sustain period SP. A sustain pulse SSUS having a level Vs is supplied to the scan electrode Y. The first sustain voltage supply unit 20 includes a sustain voltage source Vs, a third switch SW3 connected between the sustain voltage source Vs and the second node N2.

The first base voltage supply unit 22 supplies a sustain pulse SSUS having a base voltage level GND to the scan electrode Y during the sustain period SP. The first base voltage supply unit 22 includes a base voltage source GND and a fourth switch SW4 connected between the base voltage source GND and the second node N2.

The setup voltage supply unit 8 has a setup voltage Vsetup having a predetermined slope such that the rising ramp waveform PR shown in FIG. 2 is supplied to the scan electrode Y during the setup period SU during the reset period RP. Is supplied to the scan electrode (Y). The setup voltage supply unit 8 is a sixth switch connected between the setup voltage source Vsetup, the setup voltage source Vsetup and the third node N3 between the fifth switch SW5 and the seventh switch SW7. And a first variable resistor R1 connected to the gate terminal of the sixth switch SW6.

The setdown voltage supply control unit 10 has a setdown voltage having a predetermined slope such that the falling ramp waveform NR as shown in FIG. 2 is supplied to the scan electrode Y during the setdown period SD of the reset period RP. -Vy is supplied to the scan electrode (Y). The set-down voltage supply control unit 10 includes an eighth switch SW8 connected between the scan voltage source -Vy and the fourth node N4 between the seventh switch SW7 and the scan reference voltage supply unit 14. The second variable resistor R2 is connected to the gate terminal of the eighth switch SW8.

The scan sustain voltage supply unit 12 supplies the scan voltage (-Vy) as shown in FIG. 2 to the scan electrode Y during the address period AP. The scan sustain voltage supply unit 12 may connect the ninth switch SW9 connected in parallel with the eighth switch SW8 between the scan voltage source (-Vy), the scan voltage source (-Vy), and the fourth node N4. Include.

The scan reference voltage supply unit 14 supplies the scan reference voltage Vsc as shown in FIG. 2 to the scan electrode Y during the address period AP. The scan reference voltage supply unit 14 may include a tenth switch SW10 and an eleventh switch SW11 connected in series between the scan reference voltage source Vsc, the scan reference voltage source Vsc, and the fourth node N4. Include.

The scan IC 16 includes a twelfth switch SW12 and a fifth connected in a push-pull form between the fifth node N5 and the fourth node N4 between the tenth switch SW10 and the eleventh switch SW11. 13 switch SW13. Here, the twelfth switch SW12 connects the scan electrode Y of the panel capacitor Cp to the fifth node N5 via its own body diode, and the thirteenth switch SW13 has its own body. The fourth node N4 is connected to the scan electrode Y of the panel capacitor Cp via the diode.

The sustain driver 4 supplies the sustain voltage Vs to the sustain electrodes Z during the setdown period SD and the address period AP during the reset period RP, and the sustain electrodes SP during the sustain period SP. A sustain pulse SSUS having a sustain voltage level Vs and a ground voltage level GND at Z) is supplied to the sustain electrodes Z alternately with the scan driver 2. The sustain driver 4 recovers energy of reactive power that does not contribute to discharge in the PDP from the panel capacitor Cp and supplies the recovered energy to the scan electrodes Y1 to Yn during the sustain period SP. do. The sustain driver 4 includes a second energy recovery / supply unit 32, a second sustain voltage supply unit 34, and a second base voltage supply unit 36. This sustain pulse supply unit 6 is used as an energy recovery circuit.

The second energy recovery / supply unit 32 recovers the energy of the reactive power that does not contribute to the discharge in the PDP from the panel capacitor Cp during the sustain period SP, and recovers the recovered energy from the sustain electrode of the panel capacitor Cp. To the field (Z). The second energy recovery / supply unit 32 is provided between the source capacitor Cs, the source capacitor Cs and the second sustain voltage supply unit 34, and the second base voltage supply unit 36 to store the recovered energy. Inductor L connected between seventh node N7, between source capacitor Cs and inductor L to form a current path for supplying energy stored in source capacitor Cs to panel capacitor Cp. The third diode D1 to form a current path for recovering energy of reactive power not contributing to the discharge from the fourteenth switch SW14 and the third diode D3 connected in series to the panel capacitor Cp. And a fourth diode D4 and a fifteenth switch SW15 connected in series between the sixth node N6 between the inductor L and the source capacitor Cs.

The second sustain voltage supply unit 34 supplies the sustain voltage Vs to the sustain electrodes Z of the panel capacitor Cp during the set-down period SD and the address period AP during the reset period RP. The sustain pulse SSUS having the sustain voltage level Vs is supplied to the sustain electrodes Z during the period SP. The second sustain voltage supply unit 34 includes a sixteenth switch SW16 connected between the sustain voltage source Vs, the sustain voltage source Vs, and the seventh node N7.

The second base voltage supply unit 36 supplies the sustain electrodes Z with the sustain pulse SUSP having the base voltage level GND during the sustain period SP. The second base voltage supply unit 36 includes a base voltage source GND and a seventeenth switch SW17 connected between the base voltage source GND and the seventh node N7.

In the conventional PDP driving apparatus, a setup voltage Vsetup, a sustain voltage Vs, a ground voltage GND, a scan reference voltage Vsc, and a data voltage V are used to drive the PDP using the driving waveform shown in FIG. A plurality of DC power supplies having voltage levels such as Va) and scan voltage (-Vy) are required. At this time, the sustain voltage Vs, the base voltage GND, and the data voltage Va are supplied from a power supply board (not shown), and other additional power sources, that is, the setup voltage Vsetup and the scan voltage (-Vy). For example, the scan reference voltage Vsc is used by converting the sustain voltage Vs to DC-DC so as to match the level of each power supply. Accordingly, there is a problem in that the cost of the PDP driving apparatus increases because a DC-DC conversion circuit for converting the level of each power source is required.

Accordingly, an object of the present invention is to provide a plasma display panel driving apparatus and a driving method thereof which can reduce the cost by reducing the number of power sources required for driving the plasma display panel.

In order to achieve the above object, the driving apparatus of the plasma display panel according to the present invention supplies a setup voltage and a scan reference voltage to the scan electrodes of the panel capacitors, and supplies a positive first voltage to the scan electrodes and the sustain electrodes of the panel capacitors. A scan driver alternately supplying and controlling a second voltage having a negative polarity to be supplied to the scan electrode of the panel capacitor; And a sustain driver to alternately supply the second voltage to the scan electrode and the sustain electrode of the panel capacitor, and to control the first voltage to be supplied to the sustain electrode of the panel capacitor.

The first voltage and the second voltage are characterized in that the voltage difference as much as the sustain voltage.

The first voltage has a voltage value between the base voltage and the positive sustain voltage, and the second voltage has a voltage value between the base voltage and the negative sustain voltage.

The first voltage is 1/2 sustain voltage, and the second voltage is -1/2 sustain voltage.

The scan driver includes: a first voltage source for supplying the first voltage to the scan electrode and the sustain electrode of the panel capacitor; A scan voltage supply controller connected between a first node between the first voltage source and the scan electrode of the plasma display panel and the sustain driver to control a second voltage supplied from the sustain driver to be supplied to the scan electrode of the panel capacitor ; And a second voltage connected to the scan voltage supply control unit in parallel between the first node and the sustain driver to adjust the second voltage to have a predetermined slope, and a second voltage having the predetermined slope to the scan electrode of the panel capacitor. And a setdown voltage supply control unit to control the supply.

The scan voltage supply control unit includes a first switch connected between the first node and the sustain driver.

The set down voltage supply control unit includes a second switch connected in parallel with the first switch between the first node and the sustain driver; And a variable resistor connected to the gate terminal of the second switch to adjust the slope of the second voltage.

The sustain driver may include a second voltage source for supplying a second voltage to the scan electrode and the sustain electrode of the plasma display panel; A first voltage supply control unit connected between the first voltage source and the sustain electrode of the panel capacitor to control a first voltage to the first voltage source to be supplied to the sustain electrode of the panel capacitor; And a second node connected between a second node, which is a common terminal of the second voltage source, the setdown voltage supply control unit, and the scan voltage supply control unit, and a sustain electrode of the panel capacitor, so that the second voltage is supplied to the sustain electrode of the panel capacitor. And a second voltage supply control unit.

The first voltage supply control unit includes a third switch connected between the first voltage source and the sustain electrode of the panel capacitor.

The second voltage supply controller includes a fourth switch connected between the first node and the sustain electrode of the panel capacitor.

A method of driving a plasma display panel according to the present invention is a method of driving a plasma display panel which is divided into a reset period, an address period and a sustain period, wherein a positive polarity is applied to a scan electrode of the plasma display panel during a setup period during the reset period. Supplying a rising ramp waveform rising at a predetermined slope from one voltage and supplying a second negative voltage to the sustain electrode of the panel capacitor; Supplying a falling ramp waveform that falls from the first voltage to the second voltage at a predetermined slope during the set down period of the reset period, and supplying the first voltage to the sustain electrode of the panel capacitor; Supplying a scan pulse having a second voltage level to the scan electrode of the panel capacitor during the address period; During the sustain period, a positive sustain pulse having a first voltage level and a negative sustain pulse having a second voltage level are sequentially supplied to a scan electrode of the panel capacitor, and alternately with the scan electrode of the panel capacitor. And sequentially supplying the negative sustain pulse and the positive sustain pulse to the sustain electrode of the capacitor.

The first voltage and the second voltage are characterized in that the voltage difference as much as the sustain voltage.

The first voltage has a voltage value between the base voltage and the positive sustain voltage, and the second voltage has a voltage value between the base voltage and the negative sustain voltage.

The first voltage is a 1/2 sustain voltage, and the second voltage is -1/2 sustain voltage.

Other objects and advantages other than the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 17.

4 is a diagram illustrating a driving apparatus of a plasma display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 4, a driving apparatus of a plasma display panel according to an exemplary embodiment of the present invention includes a scan driver 52 for driving the scan electrode Y of the panel capacitor Cp and a sustain electrode of the panel capacitor Cp. And a sustain driver 54 for driving Z).

The panel capacitor Cp equivalently represents the capacitance formed between the scan electrode Y and the sustain electrode Z of the plasma display panel. The panel capacitor Cp generates sustain discharge by the sustain pulses supplied to the scan electrode Y and the sustain electrode Z.

The scan driver 52 supplies the setup voltage Vsetup, the base voltage GND, the scan reference voltage Vsc, and the positive first voltage Vs / 2 to the scan electrode Y of the panel capacitor Cp. The first voltage Vs / 2 is supplied to the sustain electrode Z of the panel capacitor Cp, and the second negative voltage -Vs / 2 is applied to the scan electrode Y of the panel capacitor Cp. Control to be supplied. In other words, the scan driver 52 has a peak voltage Vs / 2 + Vsetup at the positive first voltage Vs / 2 at a predetermined slope with respect to the scan electrode Y of the panel capacitor Cp during the setup period during the reset period. In addition to supplying the rising ramp waveform up to), the scan reference voltage Vsc is supplied to the scan electrode Y of the panel capacitor Cp during the address period. In addition, the scan driver 52 supplies a sustain pulse SSUS having a first voltage level Vs / 2 and a ground voltage level GND to the scan electrode Y of the panel capacitor Cp during the sustain period. The first voltage Vs / 2 is supplied to the sustain electrode Z. In addition, the scan driver 52 has a falling ramp waveform that falls from the first positive voltage Vs / 2 to the second negative voltage (-Vs / 2) by a predetermined slope for a set down period during the reset period. It is controlled to be supplied to the scan electrode Y of (Cp), and the scan pulse having the second voltage level (-Vs / 2) is supplied to the scan electrode (Y) of the panel capacitor (Cp) during the address period. . Here, the first voltage (Vs / 2) and the second voltage (-Vs / 2) have a voltage difference equal to the sustain voltage (Vs). At this time, the voltage between the base voltage GND and the positive sustain voltage Vs is used as the first voltage Vs / 2, and the voltage between the base voltage GND and the negative voltage is used as the second voltage -Vs / 2. The voltage between voltage (-Vs) is used. More specifically, the first voltage (Vs / 2) is used with 1/2 sustain voltage (Vs / 2), and the second voltage (-Vs / 2) is used with -1/2 sustain voltage (-Vs / 2). do. The scan driver 52 may include a first energy recovery / supply unit 68, a first voltage supply unit 70, a first base voltage supply unit 72, a setup voltage supply unit 58, a setdown voltage supply control unit 60, The scan voltage supply control unit 62, the scan reference voltage supply unit 64, an integrated circuit (hereinafter referred to as an “IC”) 66, a first switch SW1, and a second switch SW2 are included. .

The first energy recovery / supply section 68 is connected to the first node N1 between the first voltage supply section 70 and the first base voltage supply section 72 so as to not contribute to the discharge in the panel capacitor Cp. The energy of the power is recovered and the recovered energy is supplied to the scan electrode Y and the sustain electrode Z of the panel capacitor Cp. At this time, the first energy recovery / supply unit 68 recovers the energy stored in the panel capacitor Cp by the first voltage Vs / 2, and recovers the recovered energy from the scan electrode Y and the panel capacitor Cp. It is supplied to the sustain electrode Z. The first energy recovery / supply unit 68 may include a first source capacitor Cs1 and a first source capacitor for storing energy recovered from the scan electrode Y and the sustain electrode Z of the panel capacitor Cp. Energy stored in the first inductor L1 and the first source capacitor Cs1 connected between the Cs1 and the first node N1 is supplied to the scan electrode Y and the sustain electrode Z of the panel capacitor Cp. Energy stored in the third switch SW3 and the first diode D1 and the panel capacitor Cp connected in series between the first source capacitor Cs1 and the first inductor L1 to form a current path for Second diode D2 and fourth connected between second node N2 and first source capacitor Cs1 between first diode D1 and first inductor L1 to form a current path for recovery. And a switch SW4. Here, the third switch SW3 and the first diode D1, the second diode D2, and the fourth switch SW4 are connected in parallel between the first source capacitor Cs1 and the first inductor L1. .

The first source capacitor Cs1 recovers the energy charged in the panel capacitor Cp by the first voltage Vs / 2, and collects the recovered energy in the scan electrode Y and the sustain electrode of the panel capacitor Cp. Resupply to (Z).

The first inductor L1 stores energy supplied from the panel capacitor Cp and supplies the stored energy to the panel capacitor Cp by LC resonance with the panel capacitor Cp.

The third switch SW3 is connected between the first source capacitor Cs1 and the second node N2 and is connected to the first source capacitor Cs1 in response to a third switching control signal supplied from a timing controller (not shown). The current path is formed to supply the energy stored in the scan electrode Y and the sustain electrode Z of the panel capacitor Cp.

The first diode D1 is connected between the third switch SW3 and the second node N2 so that the energy charged in the first source capacitor Cs1 is supplied to the scan electrode Y and the sustain electrode of the panel capacitor Cp. When supplied to (Z), reverse current from the panel capacitor Cp is prevented.

The fourth switch SW4 is connected between the second node N2 and the first source capacitor Cs1 and stored in the panel capacitor Cp in response to a fourth switching control signal supplied from a timing controller (not shown). A current path is formed so that energy is recovered to the first source capacitor Cs1.

The second diode D2 is connected between the second node N2 and the fourth switch SW4 so that when the energy stored in the panel capacitor Cp is recovered to the first source capacitor Cs1, the first source capacitor Cs1 To prevent reverse current from

The first voltage supply unit 70 is connected to the first node N1 to supply the first voltage Vs / 2 to the scan electrode Y of the panel capacitor Cp during the setup period during the reset period, and also during the sustain period. The first voltage Vs / 2 is alternately supplied to the scan electrode Y and the sustain electrode Z of the panel capacitor Cp. The first voltage supply unit 70 includes a first voltage source Vs / 2 and a fifth switch SW5 for supplying the first positive voltage Vs / 2.

The fifth switch SW5 is connected between the first voltage source Vs / 2 and the first node N1 to respond to the fifth switching control signal supplied from a timing controller (not shown). 2) is electrically connected to the first node N1. Therefore, the first voltage Vs / 2 supplied from the first voltage source Vs / 2 is transmitted to the first node N1 during the setup period and the sustain period during the reset period.

The first base voltage supply unit 72 is connected to the first node N1 to supply the base voltage GND to the scan electrode Y during the sustain period. The first base voltage supply unit 72 includes a base voltage source GND and a sixth switch SW6.

The sixth switch SW6 is connected between the first node N1 and the ground voltage source GND to switch the ground voltage source GND to the first node in response to a sixth switching control signal supplied from a timing controller (not shown). It is electrically connected to (N1). As a result, the ground voltage GND is transmitted to the first node N1 during the sustain period.

The first energy recovery / supply unit 68, the first voltage supply unit 70, and the first base voltage supply unit 72 are used as an energy recovery circuit.

The setup voltage supply unit 58 is connected to the third node N3 between the first switch SW and the second switch SW2 so that the peak voltage Vs at the first voltage Vs / 2 during the setup period during the reset period. / 2 + Vsetup) to supply a ramp ramp waveform rising at a predetermined slope. To this end, the first node Vs / 2 is supplied to the third node N3 during the setup period during the reset period. The setup voltage supply unit 58 includes a setup voltage source Vsetup, a seventh switch SW7 and a first variable resistor R1.

The seventh switch SW7 is connected between the setup voltage source Vsetup and the third node N3 to set the setup voltage source Vsetup in response to a seventh switching control signal supplied from a timing controller (not shown). It is electrically connected to the node N3.

The first variable resistor R1 is connected to the gate terminal of the seventh switch SW7 to adjust the slope of the setup voltage Vsetup supplied from the setup voltage source Vsetup. Accordingly, the setup voltage Vsetup supplied from the setup voltage source Vsetup has a predetermined slope.

The set down voltage supply control unit 60 is connected between the fourth node N4 between the second switch SW2, the scan reference voltage supply unit 64, and the scan IC 66 and the sustain driver 54 to set down during the reset period. During the period of time, the set-down voltage falling to the second voltage (−Vs / 2) is controlled to be supplied to the scan electrode Y of the panel capacitor Cp. In other words, when the second voltage (-Vs / 2) is supplied from the sustain driver 54, the set-down voltage supply control unit 60 may select a predetermined voltage from the first voltage (Vs / 2) to the second voltage (-Vs / 2). The falling ramp waveform falling to the slope is controlled to be supplied to the scan electrode Y of the panel capacitor Cp during the set down period during the reset period. The set down voltage supply control unit 60 includes an eighth switch SW8 and a second variable resistor R2.

The eighth switch SW8 is connected between the fourth node N4 and the sustain driver 54 and is supplied from the sustain driver 54 in response to an eighth switching control signal supplied from a timing controller (not shown). The second voltage (-Vs / 2) is transmitted to the fourth node N4.

The second variable resistor R2 is connected to the gate terminal of the eighth switch SW8 to control the slope of the second voltage (-Vs / 2) supplied from the sustain driver 54. Accordingly, the second voltage (-Vs / 2) supplied from the sustain driver 54 during the set down period during the reset period has a predetermined slope. That is, the second voltage (-Vs / 2) having a predetermined slope is supplied to the fourth node N4 during the setdown period during the reset period.

The scan voltage supply controller 62 is connected between the fourth node N4 and the sustain driver 54 to scan pulses having the second voltage level (-Vs / 2) during the address period, and scan electrodes of the panel capacitor Cp. While supplying to (Y), the second voltage (-Vs / 2) is supplied to the scan electrode (Y) of the panel capacitor (Cp) during the sustain period. The scan voltage supply control unit 62 includes a ninth switch SW9.

The ninth switch SW9 is connected between the fourth node N4 and the sustain driver 54 and is supplied from the sustain driver 54 in response to a ninth switching control signal supplied from a timing controller (not shown). The second voltage (-Vs) is transmitted to the fourth node N4. As a result, the second voltage -Vs is transmitted to the fourth node N4 during the address period and the sustain period.

The scan reference voltage supply unit 64 is connected between the fourth node N4 and the scan IC 66 to supply the scan reference voltage Vsc to the scan electrode Y of the panel capacitor Cp during the address period. The scan reference voltage supply unit 64 may include the tenth switch SW10 and the eleventh switch SW11 connected in series between the scan reference voltage source Vsc, the scan reference voltage source Vsc, and the fourth node N4. Include.

The tenth switch SW10 is connected between the scan reference voltage source Vsc and the scan IC 66 to receive the scan reference voltage source Vsc in response to a tenth switching control signal supplied from a timing controller (not shown). The fifth node N5 is electrically connected between the switch SW11 and the scan IC 66. Accordingly, the scan reference voltage Vsc is supplied to the fifth node N5 during the address period.

The eleventh switch SW11 is connected between the fifth node N5 and the fourth node N4 and is connected to the fifth node N5 and the fifth node in response to an eleventh switching control signal supplied from a timing controller (not shown). Four nodes N4 are electrically connected. Accordingly, the voltage supplied to the fifth node N5 is transmitted to the fourth node N4, and the voltage supplied to the fourth node N4 is transmitted to the fifth node N5.

The scan IC 66 includes a twelfth switch SW12 and a thirteenth switch SW13 connected in a push-pull form between the fifth node N5 and the fourth node N4. At this time, the output terminal between the twelfth switch SW12 and the thirteenth switch SW13 is connected to the scan electrode Y of the panel capacitor Cp.

The twelfth switch SW12 is connected between the fifth node N5 and the scan electrode Y of the panel capacitor Cp and is supplied to the fifth node N5 via its body diode. Is supplied to the scan electrode Y of the panel capacitor Cp. In other words, the twelfth switch SW12 is a voltage supplied to the fifth node N5 by electrically connecting the scan electrode Y of the panel capacitor Cp to the fifth node N5 via its body diode. Is supplied to the scan electrode Y of the panel capacitor Cp. At this time, a negative voltage is supplied to the fifth node N5. Accordingly, a voltage as low as a negative voltage supplied to the fifth node N5 is supplied to the scan electrode Y of the panel capacitor Cp.

The thirteenth switch SW13 is connected between the fourth node N4 and the scan electrode Y of the panel capacitor Cp and receives the voltage supplied to the fourth node N4 via its body diode. It is supplied to the scan electrode Y of Cp). In other words, the thirteenth switch SW13 is a voltage supplied to the fourth node N4 by electrically connecting the fourth node N4 to the scan electrode Y of the panel capacitor Cp via its body diode. Is supplied to the scan electrode Y of the panel capacitor Cp. At this time, the positive voltage is supplied to the fourth node N4. Accordingly, the scan electrode Y of the panel capacitor Cp is supplied with a voltage as high as the voltage of the positive polarity supplied to the fourth node N4.

The first switch SW1 is connected between the first node N1 and the third node N3 to electrically connect the first node N1 to the third node N3 via its own body diode. . Accordingly, the voltage supplied from the first energy recovery / supply unit 68, the first voltage supply unit 70, and the first base voltage supply unit 72 is transmitted to the first node (via the body diode of the first switch SW1). From N1) to the third node N3. That is, the first switch SW1 forms an energy supply path for supplying energy to the panel capacitor Cp using its own body diode. In addition, the first switch SW1 electrically connects the third node N3 to the first node N1 in response to a first switching control signal supplied from a timing controller (not shown). Accordingly, energy of reactive power that does not contribute to the discharge in the panel capacitor Cp is transferred from the third node N3 to the first node N1. That is, the first switch SW1 forms an energy recovery path for transferring energy from the panel capacitor Cp to the first energy recovery / supply unit 68 in response to the first switching control signal.

The second switch SW2 is connected between the third node N3 and the fourth node N4 to electrically connect the fourth node N4 to the third node N3 via its own body diode. . Accordingly, energy of reactive power that does not contribute to the discharge in the panel capacitor Cp is transferred from the fourth node N4 to the third node N3. That is, the second switch SW2 forms an energy recovery path that transfers energy from the panel capacitor Cp to the first energy recovery / supply unit 68 using its own body diode. In addition, the second switch SW2 electrically connects the third node N3 to the fourth node N4 in response to a second switching control signal supplied from a timing controller (not shown). Accordingly, the voltage supplied to the third node N3 is transmitted to the fourth node N4. That is, the second switch SW2 forms an energy supply path for supplying energy to the panel capacitor Cp in response to a second switching control signal supplied from a timing controller (not shown).

The sustain driver 54 supplies a second voltage (-Vs / 2) and a ground voltage GND to the sustain electrode Z of the panel capacitor Cp during the sustain period, and also the first driver supplied from the scan driver 52. The voltage Vs / 2 is controlled to be supplied to the sustain electrode Z of the panel capacitor Cp. In addition, the sustain driver 54 supplies the second voltage -Vs to the scan electrode Y of the panel capacitor Cp during the set-down period, the address period, and the sustain period during the reset period. The sustain driver 54 includes a second energy recovery / supply unit 78, a second voltage supply unit 76, a second base voltage supply unit 74, a first voltage supply control unit 80, and a second voltage supply control unit ( 82).

The second energy recovery / supply unit 78 is connected to the sixth node N6 between the second voltage supply unit 76 and the second base voltage supply unit 74 and does not contribute to discharge in the panel capacitor Cp. The energy is recovered and the recovered energy is supplied to the scan electrode Y and the sustain electrode Z of the panel capacitor Cp. At this time, the second energy recovery / supply unit 78 recovers the energy stored in the panel capacitor Cp by the second voltage Vs / 2, and recovers the recovered energy from the scan electrode Y and the panel capacitor Cp. It is supplied to the sustain electrode Z. The second energy recovery / supply unit 78 may include a second source capacitor Cs2 and a second source capacitor for storing energy recovered from the scan electrode Y and the sustain electrode Z of the panel capacitor Cp. Energy stored in the second inductor L2 and the second source capacitor Cs2 connected between Cs2 and the sixth node N6 is supplied to the scan electrode Y and the sustain electrode Z of the panel capacitor Cp. Energy stored in the fourteenth switch SW14 and the third diode D3 and the panel capacitor Cp connected in series between the second source capacitor Cs2 and the second inductor L2 to form a current path for Fourth diode D4 and fifteen connected between the seventh node N7 and the second source capacitor Cs2 between the third diode D3 and the second inductor L2 to form a current path for recovery. And a switch SW15. Here, the fourteenth switch SW3 and the third diode D3, the fourth diode D4, and the fifteenth switch SW15 are connected in parallel between the second source capacitor Cs2 and the second inductor L2. . In addition, the second source capacitor Cs2 is connected between the fourteenth switch SW14 and the fifteenth switch SW15 and between the second voltage source -Vs / 2.

The second source capacitor Cs2 recovers the energy charged in the panel capacitor Cp by the second voltage (-Vs / 2), and the recovered energy is stored in the scan electrode Y and the sustain of the panel capacitor Cp. Resupply to electrode (Z).

The second inductor L2 stores energy supplied from the panel capacitor Cp and supplies the stored energy to the panel capacitor Cp by LC resonance with the panel capacitor Cp.

The fourteenth switch SW14 is connected between the second source capacitor Cs1 and the seventh node N7 to respond to the fourteenth switching control signal supplied from a timing controller (not shown). The current path is formed to supply the energy stored in the scan electrode Y and the sustain electrode Z of the panel capacitor Cp.

The third diode D3 is connected between the fourteenth switch SW14 and the seventh node N7 so that the energy charged in the second source capacitor Cs2 is applied to the scan electrode Y and the sustain electrode of the panel capacitor Cp. When supplied to (Z), reverse current from the panel capacitor Cp is prevented.

The fifteenth switch SW15 is connected between the seventh node N7 and the second source capacitor Cs2 and stored in the panel capacitor Cp in response to a fifteenth switching control signal supplied from a timing controller (not shown). A current path is formed so that energy is recovered to the second source capacitor Cs2.

The fourth diode D4 is connected between the seventh node N7 and the fifteenth switch SW15 so that the second source capacitor Cs2 when the energy stored in the panel capacitor Cp is recovered to the second source capacitor Cs2. To prevent reverse current from

The second voltage supply unit 76 is connected between the sixth node N6 and the second energy recovery / supply unit 78 to scan the electrode Y of the panel capacitor Cp during the setdown period, the address period, and the sustain period during the reset period. ) And a second voltage (-Vs / 2) to the sustain electrode (Z) of the panel capacitor (Cp) during the sustain period. At this time, the second voltage supply unit 76 alternately supplies the second voltage (-Vs / 2) to the scan electrode Y and the sustain electrode Z of the panel capacitor Cp during the sustain period. The second voltage supply unit 76 includes a second voltage source (-Vs / 2) and a sixteenth switch SW16 that supply a second negative voltage (-Vs / 2).

The sixteenth switch SW16 is connected between the second voltage source -Vs / 2 and the sixth node N6 to respond to the sixteenth switching control signal supplied from a timing controller (not shown). Vs / 2) is electrically connected to the sixth node N6. Therefore, the second voltage (-Vs / 2) supplied from the second voltage source (-Vs / 2) is transmitted to the sixth node N6 during the setdown period, the address period, and the sustain period during the reset period.

The second base voltage supply unit 74 is connected to the sixth node N6 to supply the base voltage GND to the sustain electrode Z during the sustain period. The second base voltage supply 74 includes a base voltage source GND and a seventeenth switch SW17.

The seventeenth switch SW17 is connected between the sixth node N6 and the ground voltage source GND to switch the ground voltage source GND to the sixth node in response to a seventeenth switching control signal supplied from a timing controller (not shown). It is electrically connected to (N6). As a result, the ground voltage GND is transmitted to the sixth node N6 during the sustain period.

The second energy recovery / supply unit 78, the second voltage supply unit 76, and the second base voltage supply unit 74 are used as energy recovery circuits.

The first voltage supply controller 80 is connected between the first node N1 and the sustain electrode Z of the panel capacitor Cp so that the first voltage Vs / 2 is the sustain electrode Z of the panel capacitor Cp. ) To be supplied. The first voltage supply controller 80 includes an eighteenth switch SW18.

The eighteenth switch SW18 is connected between the first node N1 and the sustain electrode Z of the panel capacitor Cp to supply a first voltage in response to an eighteenth switching control signal supplied from a timing controller (not shown). The first voltage Vs / 2 supplied from the supply unit 70 is supplied to the sustain electrode Z of the panel capacitor Cp.

The second voltage supply controller 82 is connected between the sixth node N6 and the sustain electrode Z of the panel capacitor Cp so that the second voltage (-Vs / 2) and the ground voltage GND are connected to the panel capacitor ( It is controlled to be supplied to the sustain electrode Z of Cp). The second voltage supply controller 82 includes a nineteenth switch SW19.

The nineteenth switch SW19 is connected between the sixth node N6 and the sustain electrode Z of the panel capacitor Cp to supply a second voltage in response to a nineteenth switching control signal supplied from a timing controller (not shown). The second voltage (-Vs / 2) supplied from the supply unit 76 and the base voltage GND supplied from the second base voltage supply unit 74 are supplied to the sustain electrode Z of the panel capacitor Cp. In addition, the nineteenth switch SW19 receives the energy supplied from the second energy recovery / supply unit 78 in response to a nineteenth switching control signal supplied from a timing controller (not shown). A supply path for supplying Z) is formed, and a recovery path is formed such that energy stored in the panel capacitor Cp is supplied to the second energy recovery / supply unit 78 by the second voltage (-Vs / 2). . The nineteenth switch SW19 may be configured to supply the second voltage Vs supplied from the second voltage supply unit 76 to the sustain electrode Z of the panel capacitor Cp during the set down period and the address period during the reset period. prevent.

In the driving device of the plasma display panel having such a configuration, each of the switches SW1 to SW19 uses a field effect transistor (FET) having a body diode embedded therein.

FIG. 5 is a diagram illustrating driving waveforms generated according to on / off timings of the switches illustrated in FIG. 4, and FIG. 6 is a diagram illustrating on / off timings of switches for generating driving waveforms illustrated in FIG. 7 to 17 are diagrams illustrating current paths formed according to on / off timings illustrated in FIG. 6.

5 to 5, the second switching control signal and the fifth switching signal of the HIGH state supplied from a timing controller (not shown) at the time t1, which is the beginning of the setup period SU, during the reset period RP. The second switch SW2, the fifth switch SW5, the sixteenth switch SW16, and the nineteenth switch SW19 are turned on according to the control signal, the sixteenth switching control signal, and the nineteenth switching control signal. Accordingly, as shown in FIG. 7, the first voltage source Vs / 2, the fifth switch SW5, the first node N1, the body diode of the first switch SW1, the third node N3, The first current path and the panel capacitor Cp leading to the scan electrode Y of the panel capacitor Cp via the body diodes of the second switch SW2, the fourth node N4, and the thirteenth switch SW13. A second current path leading to the second voltage source (-Vs / 2) is formed via the sustain electrode Z, the nineteenth switch SW19, and the sixth node N6. Accordingly, the first voltage Vs / 2 is supplied to the scan electrode Y of the panel capacitor Cp, and the second voltage -1/2 is supplied to the sustain electrode Z of the panel capacitor Cp. do.

The second switching control signal, the fifth switching control signal, the seventh switching control signal, and the sixteenth switching control in the high state supplied from the timing controller (not shown) at the time t2 which is the setup period SU during the reset period RP. According to the signal and the nineteenth switching control signal, the second switch SW2, the fifth switch SW5, the sixteenth switch SW16, and the nineteenth switch SW19 maintain the previous on state and the seventh switch SW7. ) Is turned on. Accordingly, as illustrated in FIG. 8, the third node N3 is passed through the body diodes of the first voltage source Vs / 2, the fifth switch SW5, the first node N1, and the first switch SW1. Body of the first current path, the setup voltage source Vsetup, the seventh switch SW7, the third node N3, the second switch SW2, the fourth node N4, and the thirteenth switch SW13 The second current path leading to the scan electrode Y of the panel capacitor Cp via the diode and the sustain electrode Z of the panel capacitor Cp, the nineteenth switch SW19 and the sixth node N6. A third current path is formed that leads to the second voltage source (-Vs / 2). Accordingly, the rising ramp waveform PR that rises with a predetermined slope from the first voltage Vs / 2 to the peak voltage Vs / 2 + Vsetup is supplied to the scan electrode Y of the panel capacitor Cp, The second voltage (-Vs / 2) is supplied to the sustain electrode Z of the panel capacitor Cp.

The second switching control signal, the fifth switching control signal, the seventeenth switching control signal, and the nineteenth switching state which are supplied from the timing controller (not shown) at the time t3 of the reset period RP, which is the beginning of the setdown period SD. According to the switching control signal, the second switch SW2, the fifth switch SW5, and the nineteenth switch SW19 maintain the previous on state, and the seventeenth switch SW17 is turned on. In addition, the seventh switch SW7 and the sixteenth switch SW16 are turned off according to the seventh switching control signal and the sixteenth switching control signal in a low state supplied from a timing controller (not shown). . Accordingly, as shown in FIG. 9, the first voltage source Vs / 2, the fifth switch SW5, the first node N1, the body diode of the first switch SW1, the third node N3, The first current path and the panel capacitor Cp connected to the scan electrode Y of the panel capacitor Cp via the body diodes of the second switch SW2, the fourth node N4, and the thirteenth switch SW13. A second current path is formed to the ground voltage source GND via the sustain electrode Z, the nineteenth switch SW19, and the sixth node N6. Therefore, the first voltage Vs / 2 is supplied to the scan electrode Y of the panel capacitor Cp, and the ground voltage GND is supplied to the sustain electrode Z of the panel capacitor Cp.

At the time t4 which is the setdown period SD of the reset period RP, the fifth switching control signal, the eighth switching control signal, the eleventh switching control signal, and the sixteenth switching control of the high state supplied from a timing controller (not shown) are provided. According to the signal and the eighteenth switching control signal, the fifth switch SW5 maintains the previous on state, and the eighth switch SW8, the eleventh switch SW11, the sixteenth switch SW16 and the eighteenth switch ( SW18) is turned on. In addition, the seventeenth switch SW17 and the nineteenth switch SW19 are turned off in response to a low-th 17th switching control signal and a nineteenth switching control signal supplied from a timing controller (not shown). Accordingly, as shown in FIG. 10, the sustain electrode of the panel capacitor Cp is passed through the first voltage source Vs / 2, the fifth switch SW5, the first node N1, and the eighteenth switch SW18. The first current path leading to (Z) and the scan electrode Y of the panel capacitor Cp, the body diode of the twelfth switch SW12, the fifth node N5, the eleventh switch SW11, and the fourth node ( A second current path is formed that leads to the second voltage source (-Vs / 2) via N4), the eighth switch SW8, and the sixth node N6. Accordingly, the falling ramp waveform NR falling to the scan electrode Y of the panel capacitor Cp with a predetermined slope from the first voltage Vs / 2 to the second voltage -Vs / 2 is supplied. The first voltage Vs / 2 is supplied to the sustain electrode Z of the panel capacitor Cp.

At time t5 of the address period AP, the fifth switch SW5 and the eighteenth according to the fifth switching control signal, the tenth switching control signal, and the eighteenth switching control signal supplied from the timing controller (not shown). The switch SW18 maintains the previous on state, and the tenth switch SW10 is turned on. The eighth switch SW8, the eleventh switch SW11, and the sixteenth switch according to the eighth switching control signal, the eleventh switching control signal, and the sixteenth switching control signal in a low state supplied from a timing controller (not shown). The switch SW16 is turned off. Accordingly, as shown in FIG. 11, the sustain electrode of the panel capacitor Cp is passed through the first voltage source Vs / 2, the fifth switch SW5, the first node N1, and the eighteenth switch SW18. Scan via the first current path leading to (Z) and the scan electrode (Y) of the panel capacitor (Cp), the body diode of the twelfth switch (SW12), the fifth node (N5), and the tenth switch (SW10). A second current path is formed that leads to the reference voltage source Vsc. At this time, when the scan reference voltage Vsc supplied from the scan reference voltage source Vsc has a voltage value equal to or greater than the base voltage GND, the second current path includes the scan reference voltage source Vsc, the tenth switch SW10, and the fifth. It is formed to lead to the scan electrode Y of the panel capacitor Cp via the body diodes of the node N5, the eleventh switch SW11, the fourth node N4, and the thirteenth switch SW13. Accordingly, the scan reference voltage Vsc is supplied to the scan electrode Y of the panel capacitor Cp, and the first voltage Vs / 2 is supplied to the sustain electrode Z of the panel capacitor Cp.

A fifth switching control signal in a high state supplied from a timing controller (not shown) at a time t6 when the scan pulse SCNP is supplied to the scan electrode Y of the panel capacitor Cp during the address period AP; According to the switching control signal, the eleventh switching control signal, the sixteenth switching control signal, and the eighteenth switching control signal, the fifth switch SW5 and the eighteenth switch SW18 maintain the previous on state and the eleventh switch SW11. ), The ninth switch SW9 and the sixteenth switch SW16 are turned on. In addition, the tenth switch SW10 is turned off in response to the tenth switching control signal in a low state supplied from a timing controller (not shown). Accordingly, as shown in FIG. 12, the sustain electrode of the panel capacitor Cp is passed through the first voltage source Vs / 2, the fifth switch SW5, the first node N1, and the eighteenth switch SW18. The first current path leading to (Z) and the scan electrode Y of the panel capacitor Cp, the body diode of the twelfth switch SW12, the fifth node N5, the eleventh switch SW11, and the fourth node ( A second current path that leads to the second voltage source (-Vs / 2) is formed via N4, the ninth switch SW9, the sixth node N6, and the sixteenth switch SW16. Thus, the scan pulse SCNP having the second voltage level (-Vs / 2) is supplied to the scan electrode Y of the panel capacitor Cp, and the first sustain electrode Z of the panel capacitor Cp is supplied. The voltage Vs / 2 is supplied.

At time t7 of the address period AP, the fifth switch SW5 and the eighteenth according to the fifth switching control signal, the tenth switching control signal, and the eighteenth switching control signal supplied from the timing controller (not shown). The switch SW18 maintains the previous on state, and the tenth switch SW10 is turned on. The ninth switch SW9, the eleventh switch SW11, and the sixteenth switch according to the ninth switching control signal, the eleventh switching control signal, and the sixteenth switching control signal supplied from a timing controller (not shown). The switch SW16 is turned off. Accordingly, as shown in FIG. 11, the sustain electrode of the panel capacitor Cp is passed through the first voltage source Vs / 2, the fifth switch SW5, the first node N1, and the eighteenth switch SW18. Scan reference via the first current path leading to (Z) and the scan electrode (Y) of the panel capacitor (Cp), the body diode of the twelfth switch (SW12), the fifth node (N5), and the tenth switch (SW10). A second current path is formed that leads to the voltage source Vsc. At this time, when the scan reference voltage Vsc supplied from the scan reference voltage source Vsc has a voltage value equal to or greater than the base voltage GND, the second current path includes the scan reference voltage source Vsc, the tenth switch SW10, and the fifth. The node N5, the eleventh switch SW11, the fourth node N4, and the body diode of the thirteenth switch SW13 and the scan electrode Y of the panel capacitor Cp are formed. Accordingly, the scan reference voltage Vsc is supplied to the scan electrode Y of the panel capacitor Cp and the first voltage Vs / 2 is supplied to the sustain electrode Z of the panel capacitor Cp as in the time t5. ) Is supplied.

At the time t8, which is the initial stage of the sustain period SP, the second switching control signal, the sixth switching control signal, the seventeenth switching control signal, and the nineteenth switching control signal in a high state supplied from a timing controller (not shown) may be used. The second switch SW2, the sixth switch SW6, the seventeenth switch SW17, and the nineteenth switch SW19 are turned on. In addition, the fifth switch (not shown) according to the fifth switching control signal, the ninth switching control signal, the eleventh switching control signal, the sixteenth switching control signal, and the eighteenth switching control signal supplied from a timing controller (not shown). SW5, the ninth switch SW9, the eleventh switch SW11, the sixteenth switch SW16, and the eighteenth switch SW18 are turned off. Accordingly, as shown in FIG. 13, the base voltage source GND, the sixth switch SW6, the first node N1, the body diode of the first switch SW1, the third node N3, and the second switch. A first current path, a ground voltage source GND, and a seventeenth switch leading to the scan electrode Y of the panel capacitor Cp via the SW2, the fourth node N4, and the body diode of the thirteenth switch SW13. A second current path is connected to the sustain electrode Z of the panel capacitor Cp via SW17, the sixth node N6, and the nineteenth switch SW19. Thus, the ground voltage GND is supplied to the scan electrode Y and the sustain electrode Z of the panel capacitor Cp.

During the sustain period SP, the timing controller may recover the energy of reactive power that does not contribute to the discharge in the panel capacitor Cp from the panel capacitor Cp and supply the recovered energy to the panel capacitor Cp. (Not shown), the second switch SW2 and the nineteenth switch SW19 are moved according to the second switching control signal, the third switching control signal, the fifteenth switching control signal and the nineteenth switching control signal in the high state. Is maintained in the on state, and the third switch SW3 and the fifteenth switch SW15 are turned on. In addition, the sixth switch SW6 and the seventeenth switch SW17 are turned off in response to a sixth switching control signal and a seventeenth switching control signal in a low state supplied from a timing controller (not shown). Accordingly, as shown in FIG. 14, the first source capacitor Cs1, the third switch SW3, the first diode D1, the first inductor L1, the first node N1, and the first switch ( Scan electrode Y of panel capacitor Cp via the body diode of SW1, the third node N3, the second switch SW2, the fourth node N4, and the body diodes of the thirteenth switch SW13. The first current path and the sustain electrode Z of the panel capacitor Cp, the nineteenth switch SW19, the sixth node N6, the second inductor L2, the seventh node N7, and the fourth diode A second current path that leads to the second voltage source (-Vs / 2) is formed via D4, the fifteenth switch SW15, and the second source capacitor Cs2. Therefore, the energy stored in the first source capacitor Cs1 is supplied to the scan electrode Y of the panel capacitor Cp, and the sustain electrode Z of the panel capacitor Cp has the energy of the reactive power that does not contribute to the discharge. Is supplied to the second source capacitor Cs2. Accordingly, since the energy stored in the first source capacitor Cs1 is supplied to the scan electrode Y of the panel capacitor Cp, the scan voltage Y of the panel capacitor Cp is reduced from the base voltage GND to the first voltage. Rising voltage is supplied to Vs / 2). In addition, since the energy of the reactive power that does not contribute to the discharge in the panel capacitor Cp is recovered from the sustain electrode Z of the panel capacitor Cp to the second source capacitor Cs2, the sustain electrode Z of the panel capacitor Cp. ) Is supplied with a voltage falling from the base voltage GND to the second voltage -Vs / 2.

A second high state supplied from a timing controller (not shown) at the time t10 at which the sustain pulse SSUS is supplied to the scan electrode Y and the sustain electrode Z of the panel capacitor Cp during the sustain period SP. According to the switching control signal, the fifth switching control signal, the sixteenth switching control signal, and the nineteenth switching control signal, the second switch SW2 and the nineteenth switch SW19 maintain the previous on state, and the fifth switch SW5. ) And the sixteenth switch SW16 are turned on. In addition, the third switch SW3 and the fifteenth switch SW15 are turned off according to the third switching control signal and the fifteenth switching control signal in a low state supplied from a timing controller (not shown). Accordingly, as shown in FIG. 7, the first voltage source Vs / 2, the fifth switch SW5, the first node N1, the body diode of the first switch SW1, the third node N3, The first current path and the panel capacitor Cp connected to the scan electrode Y of the panel capacitor Cp via the body diodes of the second switch SW2, the fourth node N4, and the thirteenth switch SW13. A second current path is formed to the second voltage source (-Vs / 2) via the sustain electrode Z, the nineteenth switch SW19, and the sixth node N6. Accordingly, the first voltage Vs / 2 is supplied to the scan electrode Y of the panel capacitor Cp, and the second voltage -1/2 is supplied to the sustain electrode Z of the panel capacitor Cp. do. Here, the operations at time t9 and time t10 occur almost simultaneously. That is, in FIG. 5, the first voltage Vs / 2 is supplied to the scan electrode Y of the panel capacitor Cp during the sustain period SP, and the second voltage is supplied to the sustain electrode Z of the panel capacitor Cp. When (-Vs / 2) is supplied, the operation at time t9 and the operation at time t10 occur.

During the sustain period SP, the timing controller (t11) recovers the energy of reactive power not contributing to the discharge in the panel capacitor Cp from the panel capacitor Cp and supplies the recovered energy to the panel capacitor Cp. (Not shown) according to the first switching control signal, the fourth switching control signal, the eleventh switching control signal, the fourteenth switching control signal and the nineteenth switching control signal in the high state, The ON state is maintained and the first switch SW1, the fourth switch SW4, and the eleventh switch SW11 are turned on. Further, the second switch SW2, the fifth switch SW5, and the sixteenth according to the second switching control signal, the fifth switching control signal, and the sixteenth switching control signal in a low state supplied from a timing controller (not shown). The switch SW16 is turned off. Accordingly, as illustrated in FIG. 15, the scan electrode Y and the twelfth switch SW12 of the panel capacitor Cp are the body diode, the fifth node N5, the eleventh switch SW11, and the fourth node ( N4), body diode of second switch SW2, third node N3, first switch SW1, first node N1, first inductor L1, second node N2, second First current path, second voltage source (-Vs / 2), and second source capacitor Cs2 leading to the ground voltage source GND via the diode D2, the fourth switch SW4, and the first source capacitor Cs1. ), The sustain electrode Z of the panel capacitor Cp via the fourteenth switch SW14, the third diode D3, the second inductor L2, the sixth node N6, and the nineteenth switch SW19. A second current path is formed that leads to. As a result, the energy of the reactive power that does not contribute to the discharge in the panel capacitor Cp is recovered from the scan electrode Y of the panel capacitor Cp to the first source capacitor Cs1, so that the scan electrode of the panel capacitor Cp Y) is supplied with a voltage falling from the first voltage Vs / 2 to the ground voltage GND. In addition, since the energy stored in the second source capacitor Cs2 is supplied to the sustain electrode Z of the panel capacitor Cp, the energy is stored at the second voltage (-Vs / 2) to the sustain electrode Z of the panel capacitor Cp. The voltage rising to the low voltage GND is supplied.

During the sustain period SP, a high state supplied from a timing controller (not shown) at a time t12 when the polarity of the sustain pulse SUSP supplied to the scan electrode Y and the sustain electrode Z of the panel capacitor Cp changes. According to the second switching control signal, the sixth switching control signal, the seventeenth switching control signal, and the nineteenth switching control signal, the nineteenth switch SW19 maintains the previous on state, and the second switch SW2 and the sixth switch The switch SW6 and the seventeenth switch SW17 are turned on. In addition, the first switch SW1 and the fourth switch according to the first switching control signal, the fourth switching control signal, the eleventh switching control signal, and the fourteenth switching control signal in a low state supplied from a timing controller (not shown). SW4, the eleventh switch SW11, and the fourteenth switch SW14 are turned off. Accordingly, as shown in FIG. 13, the base voltage source GND, the sixth switch SW6, the first node N1, the body diode of the first switch SW1, the third node N3, and the second switch. A first current path, a ground voltage source GND, and a seventeenth switch leading to the scan electrode Y of the panel capacitor Cp via the SW2, the fourth node N4, and the body diode of the thirteenth switch SW13. A second current path is connected to the sustain electrode Z of the panel capacitor Cp via SW17, the sixth node N6, and the nineteenth switch SW19. Thus, the ground voltage GND is supplied to the scan electrode Y and the sustain electrode Z of the panel capacitor Cp.

During the sustain period SP, the timing controller may recover the energy of reactive power that does not contribute to the discharge in the panel capacitor Cp from the panel capacitor Cp and supply the recovered energy to the panel capacitor Cp. (Not shown) according to the third switching control signal, the ninth switching control signal, the eleventh switching control signal, the fifteenth switching control signal and the eighteenth switching control signal in the high state, the third switch SW3 and the ninth switching control signal. The switch SW9, the eleventh switch SW11, the fifteenth switch SW15, and the eighteenth switch SW18 are turned on. The second switch SW2 and the sixth switch according to the second switching control signal, the sixth switching control signal, the seventeenth switching control signal, and the nineteenth switching control signal in a low state supplied from a timing controller (not shown). SW6, the seventeenth switch SW17, and the nineteenth switch SW19 are turned off. Accordingly, as shown in FIG. 16, the first source capacitor Cs1, the third switch SW3, the first diode D1, the second node N2, the first inductor L1, and the first node ( The first current path leading to the sustain electrode Z of the panel capacitor Cp, the scan electrode Y of the panel capacitor Cp, and the body of the twelfth switch SW12 via the N1) and the eighteenth switch SW18. Diode, fifth node N5, eleventh switch SW11, fourth node N4, ninth switch SW9, sixth node N6, second inductor L2, seventh node N7 A second current path is formed to the second voltage source (-Vs / 2) via the fourth diode D4, the fifteenth switch SW15, and the second source capacitor Cs2. As a result, the energy stored in the first source capacitor Cs1 is supplied to the sustain electrode Z of the panel capacitor Cp, and the scan electrode Y of the panel capacitor Cp has the energy of reactive power that does not contribute to the discharge. Is supplied to the second source capacitor Cs2. Accordingly, a voltage rising from the base voltage GND to the first voltage Vs / 2 is supplied to the sustain electrode Z of the panel capacitor Cp due to the energy supplied from the first source capacitor Cs1. do. In addition, since the energy of reactive power that does not contribute to the discharge in the panel capacitor Cp is recovered from the scan electrode Y of the panel capacitor Cp to the second source capacitor Cs2, the scan electrode Y of the panel capacitor Cp ) Is supplied with a voltage falling from the base voltage GND to the second voltage -Vs / 2.

A fifth state in a high state supplied from a timing controller (not shown) at the time t14 at which the sustain pulse SSUS is supplied to the scan electrode Y and the sustain electrode Z of the panel capacitor Cp during the sustain period SP. According to the switching control signal, the ninth switching control signal, the eleventh switching control signal, the sixteenth switching control signal, and the eighteenth switching control signal, the ninth switch SW9, the eleventh switch SW11, and the eighteenth switch SW18 The previous on state is maintained and the fifth switch SW5 and the sixteenth switch SW16 are turned on. In addition, the third switch SW3 and the fifteenth switch SW15 are turned off according to the third switching control signal and the fifteenth switching control signal in a low state supplied from a timing controller (not shown). Accordingly, as shown in FIG. 12, the sustain electrode of the panel capacitor Cp is passed through the first voltage source Vs / 2, the fifth switch SW5, the first node N1, and the eighteenth switch SW18. The first current path leading to (Z) and the scan electrode Y of the panel capacitor Cp, the body diode of the twelfth switch SW12, the fifth node N5, the eleventh switch SW11, and the fourth node ( A second current path that leads to the second voltage source (-Vs / 2) is formed via N4, the ninth switch SW9, the sixth node N6, and the sixteenth switch SW16. Thus, the scan pulse SCNP having the second voltage level (-Vs / 2) is supplied to the scan electrode Y of the panel capacitor Cp, and the first sustain electrode Z of the panel capacitor Cp is supplied. The voltage Vs / 2 is supplied.

During the sustain period SP, at the time t15 of recovering the energy of the reactive power not contributing to the discharge in the panel capacitor Cp from the panel capacitor Cp and supplying the recovered energy to the panel capacitor Cp, the timing controller ( (Not shown) the ninth switch SW9, the eleventh switch in accordance with the fourth switching control signal, the ninth switching control signal, the eleventh switching control signal, the fourteenth switching control signal, and the eighteenth switching control signal in a high state. SW11 and the eighteenth switch SW18 maintain the previous on state, and the fourth switch SW4 and the fourteenth switch SW14 are turned on. In addition, the fifth switch SW5 and the sixteenth switch SW16 are turned off according to the fifth switching control signal and the sixteenth switching control signal in the low state supplied from the timing controller (not shown). Accordingly, as shown in FIG. 17, the sustain electrode Z of the panel capacitor Cp, the eighteenth switch SW18, the first node N1, the first inductor L1, the second node N2, First current path and second voltage source (-Vs / 2), second source capacitor (Cs2), and fourteenth switch leading to the ground voltage source (GND) via the second diode (D2) and the first source capacitor (Cs1). (SW14), the third diode (D3), the seventh node (N7), the second inductor (L2), the sixth node (N6), the ninth switch (SW9), the fourth node (N4) and the eleventh switch ( A second current path leading to the fifth node N5 is formed via SW11. Therefore, the sustain electrode Z of the panel capacitor Cp supplies the energy of reactive power not contributing to the discharge to the first source capacitor Cs1, and the second scan electrode Y of the panel capacitor Cp to the scan electrode Y. The energy stored in the source capacitor Cs2 is supplied. Accordingly, energy of reactive power that does not contribute to the discharge from the sustain electrode Z of the panel capacitor Cp is recovered to the first source capacitor Cs1, so that the first voltage is applied to the sustain electrode Z of the panel capacitor Cp. A voltage falling from Vs / 2 to the ground voltage GND is supplied. In addition, the scan electrode Y of the panel capacitor Cp is connected to the fifth node N5 through the body diode of the twelfth switch SW12 and supplied to the fifth node N5, that is, the second source capacitor. Since the energy stored in Cs2 is supplied, a voltage rising from the second voltage (-Vs / 2) to the base voltage GND is supplied to the scan electrode Y of the panel capacitor Cp.

At this time, from the time t8 to the time t15, the operation is repeatedly performed during the sustain period SP to supply the sustain pulse SSUS to the scan electrode Y and the sustain electrode Z of the panel capacitor Cp.

As described above, the driving apparatus and driving method of the plasma display panel according to the present invention are manufactured by reducing the number of DC-DC conversion circuits for converting the level of each power source by reducing the number of power sources required for driving the plasma display panel. The cost can be reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (14)

A setup voltage and a scan reference voltage are supplied to the scan electrode of the panel capacitor, and a first positive voltage is alternately supplied to the scan electrode and the sustain electrode of the panel capacitor, and a second negative voltage is used to scan the panel capacitor. A scan driver controlling the supply to the electrode; And And a sustain driver configured to alternately supply the second voltage to the scan electrode and the sustain electrode of the panel capacitor, and to control the first voltage to be supplied to the sustain electrode of the panel capacitor. Drive system. The method of claim 1, And the first voltage and the second voltage have a voltage difference equal to that of a sustain voltage. The method of claim 2, And wherein the first voltage has a voltage value between the base voltage and the positive sustain voltage, and the second voltage has a voltage value between the base voltage and the negative sustain voltage. The method of claim 3, wherein Wherein the first voltage is a 1/2 sustain voltage, and the second voltage is a −1/2 sustain voltage. The method of claim 1, The scan driver A first voltage source for supplying the first voltage to the scan electrode and the sustain electrode of the panel capacitor; A scan voltage supply controller connected between a first node between the first voltage source and the scan electrode of the plasma display panel and the sustain driver to control a second voltage supplied from the sustain driver to be supplied to the scan electrode of the panel capacitor ; And The second node is connected in parallel with the scan voltage supply control unit between the first node and the sustain driver to adjust the second voltage to have a predetermined slope, and a second voltage having the predetermined slope is supplied to the scan electrode of the panel capacitor. And a set down voltage supply control unit configured to control the plasma display panel. The method of claim 5, The scan voltage supply control unit And a first switch connected between the first node and the sustain driver. The method of claim 6, The set down voltage supply control unit A second switch connected in parallel with the first switch between the first node and the sustain driver; And a variable resistor connected to the gate terminal of the second switch to adjust the slope of the second voltage. The method of claim 7, wherein The sustain drive unit A second voltage source for supplying a second voltage to the scan electrode and the sustain electrode of the plasma display panel; A first voltage supply control unit connected between the first voltage source and the sustain electrode of the panel capacitor to control a first voltage to the first voltage source to be supplied to the sustain electrode of the panel capacitor; And A second node which is a common terminal of the second voltage source, the set-down voltage supply control unit and the scan voltage supply control unit, and a sustain electrode of the panel capacitor are connected to control the second voltage to be supplied to the sustain electrode of the panel capacitor. And a second voltage supply control unit. The method of claim 8, The first voltage supply control unit And a third switch connected between the first voltage source and the sustain electrode of the panel capacitor. The method of claim 9, The second voltage supply control unit And a fourth switch connected between the first node and the sustain electrode of the panel capacitor. In the driving method of a plasma display panel which is driven divided into a reset period, an address period and a sustain period, Supplying a rising ramp waveform rising from the first positive voltage to a predetermined slope to a scan electrode of the plasma display panel during a setup period during the reset period, and supplying a second negative voltage to the sustain electrode of the panel capacitor. step; Supplying a falling ramp waveform that falls from the first voltage to the second voltage at a predetermined slope during the set down period of the reset period, and supplying the first voltage to the sustain electrode of the panel capacitor; Supplying a scan pulse having a second voltage level to the scan electrode of the panel capacitor during the address period; During the sustain period, a positive sustain pulse having a first voltage level and a negative sustain pulse having a second voltage level are sequentially supplied to a scan electrode of the panel capacitor, and alternately with the scan electrode of the panel capacitor. And sequentially supplying the negative sustain pulse and the positive sustain pulse to the sustain electrode of the capacitor. The method of claim 11, And the first voltage and the second voltage have a voltage difference equal to that of a sustain voltage. The method of claim 12, And wherein the first voltage has a voltage value between the base voltage and the positive sustain voltage, and the second voltage has a voltage value between the base voltage and the negative sustain voltage. The method of claim 13, Wherein the first voltage is a 1/2 sustain voltage, and the second voltage is a −1/2 sustain voltage.

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