KR20060104507A - Method for manufacturing capacitor - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor capacitor, and in particular, the method includes forming and patterning an interlayer insulating film on a lower structure of a semiconductor substrate to form a lower electrode open region and a surface of the interlayer insulating film except for the lower electrode open region. Forming a protective film; depositing Ru with ALD in the lower electrode open region of the interlayer insulating film; forming a lower electrode; and after removing the protective film, sequentially forming a dielectric film and an upper electrode on the lower electrode. Include. Therefore, in the present invention, when the lower electrode material of the capacitor is used as Ru, the capacitor is deactivated on the surface of the interlayer insulating film where the lower electrode is not formed and the protective film is formed by OTS, and then the Ru is deposited on the lower electrode open area of the interlayer insulating film by ALD process. Compared to the method of depositing the Ru lower electrode by CVD, it is possible to prevent the generation of voids in the Ru electrode by aggregation during the subsequent annealing process to achieve higher density of the lower electrode.

Bottom electrode, Ru, ALD, passivation, protective film

Description

Method for manufacturing a semiconductor capacitor

1 to 6 are process flowcharts sequentially showing a semiconductor capacitor manufacturing process using the Ru atomic film deposition process of the present invention.

* Explanation of symbols for main parts of drawings *

10: lower structure of the semiconductor substrate

12: plug

14: interlayer insulation film

16: lower electrode open area

18: alkyl chain

20: protective film

22: lower electrode

24: dielectric film

26: upper electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor, and more particularly, to a method of manufacturing a semiconductor capacitor capable of manufacturing a lower electrode of a capacitor by an atomic layer deposition process of Ru (hereinafter referred to as ALD).

At present, in order to achieve high integration of semiconductor devices, research / development has been actively conducted on reduction of cell area and reduction of operating voltage. In addition, as the integration of semiconductor devices increases, the area of the capacitor decreases drastically, but the charge required for the operation of the memory device, that is, the capacitance secured in the unit area, must be increased.

In order to secure a sufficient capacity of the capacitor, a method of securing a sufficient capacitance by increasing the capacitor area or reducing the thickness of the dielectric film through a conventional cylinder structure change has been made. The capacitor materials of 256Mega class or higher integrated memory devices are ONO / MPS or TaON, Ta2O5 and BST (BaSrTiO3).

The structure divided into capacitor electrode materials includes MIS (Metal / Insulator / Silicon) and MIM (Metal / Insulator / Metal). Among them, MIM type capacitor has low specific resistance and parasitic capacitance due to depletion inside. It is mainly used for a high performance semiconductor device because there is no.

Recently, Ru is considered as the most promising electrode material in the MIM structure. As the capacitor structure becomes more complex, researches using Ru for the metal-organic chemical vapor deposition (MOCVD) process are being actively conducted. However, when the electrode of the capacitor is formed by Ru of MOCVD, there is a problem in that voids are formed in the Ru electrode due to agglomeration during the subsequent annealing process due to deposition on a porous film by CVD.

An object of the present invention is to provide a method of manufacturing a semiconductor capacitor that can achieve a high density of the lower electrode by depositing Ru in an ALD process with high step coverage in order to solve the problems of the prior art as described above.

In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor capacitor, the method comprising: forming an interlayer insulating film on a lower structure of a semiconductor substrate and patterning the interlayer insulating film to form a lower electrode open region; Forming a protective film on the surface, depositing Ru with ALD in the lower electrode open region of the interlayer insulating film, and forming a lower electrode, and then removing the protective film, sequentially forming a dielectric film and an upper electrode on the lower electrode. Steps.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 to 6 are process flowcharts sequentially showing a semiconductor capacitor manufacturing process using the Ru atomic film deposition process of the present invention. Referring to these drawings, a semiconductor capacitor manufacturing process according to an embodiment of the present invention will be described.

As shown in FIG. 1, an interlayer insulating film 14 such as Undoped Silicate Glass (USG), Boro Phospho Silicate Glass (BPSG), SiO 2, etc. is formed and patterned on the lower structure 10 of the semiconductor substrate. Is opened to form the lower electrode open region 16, which is a region where the lower electrode is to be formed. More specifically, although not shown in the drawings, the lower structure of the semiconductor substrate is a transistor in which a gate oxide film and a gate electrode are stacked on a semiconductor substrate on which a device isolation film is formed, and a source / drain is formed in the substrate, and an interlayer insulating film. A contact electrode and a bit line bonded to the source / drain through the plug, and a plug 12 connected to the source / drain region through the interlayer insulating layer.

Subsequently, as shown in FIG. 2, deactivation 18 is performed on the upper surface of the interlayer insulating layer 14 except for the lower electrode open region 16 by an alkyl chain. At this time, the deactivation process 18 is carried out at about 160 ℃ to 180 ℃, preferably at 170 ℃.

As shown in FIG. 3, the passivation layer 20 is formed on the surface of the passivation interlayer insulating layer 14. At this time, the process of forming the protective film 20 forms a regularly well-ordered organic molecular film, for example, octadecyltrichlorosilane (OTS) spontaneously coated on the surface of the interlayer insulating film 14 by SAMs (Self-Assembled Monolayers). The OTS consists of a reactor in the head portion bonded to the surface of the interlayer insulating film 14, a long alkane chain in the body portion which enables regular molecular film formation, and a functional group in the tail portion that influences the function of the molecular film.

Subsequently, as shown in FIG. 4, about 300 to 500 mW of Ru is deposited with ALD in the lower electrode open region of the interlayer insulating film 14 to form the lower electrode 22. Here, Ru is deposited by using RuCp2 as a precursor and O2 as a reactant. Further, a purge gas for separating the precursor and the reactant, for example, Ar or N 2, is additionally supplied to the Ru deposition chamber by about 100 to 150 sccm. Further, the initial pressure in the deposition chamber of Ru is 10 ⁻⁵ to 10 ⁻⁷ Torr, the manufacturing pressure is 1.0 to 1.4 Torr, and the deposition temperature is performed at 310 ° C. to 350 ° C. In addition, it is desirable to maintain a canister and a source line that delivers the precursor of RuCp2 at 80 to 100 ° C during Ru deposition.

Next, as shown in FIG. 5, the protective film is removed by a wet etching process or the like. As a result, the lower electrode 22, which is connected to the plug 12 and made of ALD, remains in the lower electrode open regions (side walls and bottoms) of the interlayer insulating layer 14.

Next, as shown in FIG. 6, HfO ₂ / Al ₂ O ₃ / HfO ₂ is laminated on the lower electrode 22 and the interlayer insulating layer 14 with ALD to form the dielectric film 24. Here, the dielectric film 24 of HfO ₂ / Al ₂ O ₃ / HfO ₂ forms HfO ₂ with a thickness of 30 kPa to 60 kPa, Al ₂ O ₃ with a thickness of ₅ kPa-10 kPa, and HfO ₂ with a thickness of 30 kPa-60 kPa. Form. At this time, the dielectric film 24 of HfO ₂ / Al ₂ O ₃ / HfO ₂ is deposited at 250 ° C. to 550 ° C. and maintained at a deposition pressure of about 1.0 Torr. In the ALD deposition process, Al precursor is used as TMA, and Hf precursor is Hf [(N (CH ₃ ) ₂ ] ₄ , Hf [(N (CH ₂ CH ₃ ) ₂ ] ₄ , or Hf [(N (CH ₂₎ CH ₃ ) (CH ₃ )] ₄ and O ₂ or O ₃ as a reactant, and it is preferable to maintain the vessel to deliver the precursor of Hf at 60 to 120 ℃ during Hf deposition.

Subsequently, although not shown in the drawing, the temperature of the electric furnace in the HfO ₂ / Al ₂ O ₃ / HfO ₂ dielectric film 24 is set at 550 to 700 ° C., and heat-treated in an N ₂ atmosphere to crystallize the dielectric film 24 and in the film. It increases nitrogen content and removes carbon impurities.

6, the upper electrode 26 is formed on the HfO ₂ / Al ₂ O ₃ / HfO ₂ dielectric layer 24. At this time, the upper electrode 26 is formed of a doped polysilicon or a metal film, the doped polysilicon is deposited by CVD and the metal film is deposited by physical vapor deposition (PVD), such as sputtering. As the metal film, TiN, TaN, W, WN, WSi, Ru, RuO ₂ , Ir, IrO ₂ , Pt and the like are used.

As described above, in the present invention, when the lower electrode material of the capacitor is used as Ru, the passivation layer is formed on the surface of the interlayer insulating film where the lower electrode is not formed and the protective film is formed by OTS. Compared to the method of depositing the Ru bottom electrode of the capacitor by CVD, it is possible to prevent the generation of voids in the Ru electrode by coagulation or the like during the subsequent annealing process to achieve higher density of the bottom electrode.

In addition, since the lower electrode is formed only in the open region of the interlayer insulating layer without patterning the lower electrode by etching by deactivation and forming a protective film of OTS, defects that occur in the Ru lower electrode due to etching or the like are not shown. You can prevent it.

On the other hand, the present invention is not limited to the above-described embodiment, but various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims below.

Claims (10)

In the method of manufacturing a semiconductor capacitor, Forming an interlayer insulating film on a lower structure of the semiconductor substrate and patterning the interlayer insulating film to form a lower electrode open region; Forming a protective film on a surface of the interlayer insulating film except for the lower electrode open region; Depositing Ru with ALD in the lower electrode open region of the interlayer insulating film to form a lower electrode; And After removing the protective film, sequentially forming a dielectric film and an upper electrode on the lower electrode. The method of claim 1, further comprising, prior to forming the passivation layer, deactivating an alkyl chain on a surface of the interlayer insulating layer on which the passivation layer is to be formed. The method of claim 2, wherein the deactivation process is performed at about 160 ° C. to 180 ° C. 4. The method of claim 1, wherein the protective film is formed of OTS. The method of claim 1, wherein the forming of the lower electrode comprises depositing Ru using RuCp 2 as a precursor and O 2 as a reactant. The method of manufacturing a semiconductor capacitor according to claim 5, wherein a purge gas for separating the precursor and the reactant is further supplied. The method of manufacturing a semiconductor capacitor according to claim 6, wherein the purge gas is supplied at 100 to 150 sccm. The method of claim 1, wherein the forming of the lower electrode comprises an initial pressure of 10 ⁻⁵ to 10 ⁻⁷ Torr and a manufacturing pressure of 1.0 to 1.4 Torr. The method of claim 1, wherein the forming of the lower electrode is performed at a deposition temperature of 310 ° C. to 350 ° C. 6. The method of manufacturing a semiconductor capacitor according to claim 1, wherein the lower electrode has a thickness of 300 to 500 kPa.

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