KR20060098583A - Cmos device and method for manufacturing the same - Google Patents

Abstract

The present invention provides a CMOS device and a method of manufacturing the same, which can simplify the manufacturing process while reducing the area of the device. To this end, in the present invention, a substrate, a first gate insulating film formed on the substrate, and the first A common gate electrode formed on the gate insulating film, a first source / drain region formed on the substrate exposed to both sides of the common gate electrode, a second gate insulating film formed on the common gate electrode, and an upper portion of the second gate insulating film Provided is a CMOS device including a conductive silicon layer formed at a second layer and second source / drain regions formed at both sides of the conductive silicon layer.

NMOS, PMOS, common gate electrode, vertical.

Description

CMOS device and its manufacturing method {CMOS DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1 is an equivalent circuit diagram of a CMOS inverter according to the prior art.

Sectional drawing which shows the CMOS inverter shown in FIG.

3 is a cross-sectional view showing a CMOS according to a preferred embodiment of the present invention.

4A to 4D are cross-sectional views illustrating a method of manufacturing the CMOS inverter shown in FIG. 3.

<Explanation of symbols for main parts of drawing>

110 semiconductor substrate 111 well region

112a / 112b: first source / drain region 113: first interlayer insulating film

114: first dielectric film 115: gate electrode

116: second dielectric film 117: silicon layer

118: polysilicon film 118a / 118b: second source / drain region

119: second interlayer insulating film 120: contact plug

121a to 121c: first to third wirings

NM: NMOS transistor PM: PMOS transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS device and a method of manufacturing the same, and more particularly, to a CMOS (Integrator) and a method of manufacturing the same.

In general, a CMOS (hereinafter referred to as CMOS) element is composed of a pair of NMOS transistors and PMOS transistors, and operates as an inverter according to the connection state of the NMOS transistors and the PMOS transistors. Such a CMOS inverter is a basic device widely used in most integrated circuits and is currently used in various semiconductor products.

Hereinafter, a CMOS inverter according to the related art will be described with reference to FIG. 1.

1 is an equivalent circuit diagram of a CMOS inverter according to the prior art, and FIG. 2 is a cross-sectional view of the CMOS inverter shown in FIG. 1.

As shown in FIG. 1, a CMOS inverter according to the related art is composed of an NMOS transistor NM and a PMOS transistor PM. The NMOS transistor NM and the PMOS transistor PM are connected in series, and an input signal Vin is commonly input to each gate electrode. The source of the NMOS transistor NM is connected to the ground voltage source Vss, and the source of the PMOS transistor PM is connected to the power source voltage source V _DD . In addition, the drains of the NMOS transistor NM and the PMOS transistor PM are connected to each other to function as an output terminal Vout.

Such a CMOS inverter is manufactured by the following method. First, as shown in FIG. 2, the conventional CMOS inverter has different conductivity to the P-type semiconductor substrate 10 defined by the NMOS region (NMOS) where the NMOS transistor is to be formed and the PMOS region (PMOS) where the PMOS transistor is to be formed. Wells of the mold are formed. For example, a P well P-Well 11a is formed in the semiconductor substrate 10 of the NMOS region NM, and an N well Nb 11b is formed in the semiconductor substrate 10 of the PMOS region PM.

First and second gate electrodes 15a and 15b are horizontally formed on the semiconductor substrate 10 of the NMOS region NM and the PMOS region PM, respectively. The first and second source / drain regions 16a and 16b are formed in the P well 11a and the N well 11b exposed to both sides of the first and second gate electrodes 15a and 15b, respectively. In this case, the first and second gate electrodes 15a and 15b have a structure in which a polysilicon film 14 is stacked on a silicon oxide film (SiO ₂ ; 13) having a dielectric constant of 3.9 or less.

However, in the conventional CMOS inverter as described above, as the NMOS transistor and the PMOS transistor each occupy a predetermined area and are formed horizontally, a problem arises in that the area of the device increases as a whole. Furthermore, in order to supply the input signal Vin in common to the gate electrodes 15a and 15b of the NMOS transistor and the PMOS transistor, a wiring process for connecting the first and second gate electrodes 15a and 15b to each other must be additionally performed. do. As a result, the manufacturing process of the CMOS inverter as a whole becomes complicated and a problem arises in that the manufacturing cost increases.

Accordingly, an object of the present invention is to provide a CMOS device and a method of manufacturing the same, which have been proposed to solve the above-described problems of the prior art and can simplify the manufacturing process while reducing the area of the device.

According to an aspect of the present invention, a substrate, a first gate insulating film formed on the substrate, a common gate electrode formed on the first gate insulating film, and both sides of the common gate electrode are provided. A first source / drain region formed on the exposed substrate, a second gate insulating film formed on the common gate electrode, a conductive silicon layer formed on the second gate insulating film, and formed on both sides of the conductive silicon layer A CMOS device including a second source / drain region is provided.

According to another aspect of the present invention, there is provided a method of forming a first conductive well region in a semiconductor substrate, and forming a first conductive source / drain region of a second conductive type in the well region. Depositing a first interlayer insulating film on the well region and the first source / drain region, forming a via hole exposing the well region between the first source / drain region, and forming the via hole. Forming a first gate insulating layer at a bottom of the substrate; forming a common gate electrode on the first gate insulating layer to fill a portion of the via hole; and forming a second gate on the common gate electrode to fill the via hole. Forming an insulating film, forming a second conductive silicon layer on the second gate insulating film, and covering the silicon layer in an overall structure Depositing a polysilicon film on the substrate; etching the polysilicon film to expose the silicon layer; and implanting first conductive impurity ions into the polysilicon film to form a second source / drain region. It provides a method for manufacturing a CMOS device.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

Example

3 is a cross-sectional view illustrating a CMOS inverter according to a preferred embodiment of the present invention.

First, as shown in FIG. 3, the CMOS inverter according to the preferred embodiment of the present invention has a symmetrical structure such that the NMOS transistor and the PMOS transistor share one gate electrode 115 in common with each other in a vertical direction. As an example, a structure in which an NMOS transistor is positioned above and a PMOS transistor is formed below will be described.

The PMOS transistor PM includes an N-well region 111 formed in the semiconductor substrate 110, a first gate insulating layer 114 formed in a predetermined region on the N-well region 111, and a first gate insulating layer 114. And a P ⁺ first source / drain regions 112a and 112b formed in the N-well region 111 exposed to both sides of the common gate electrode 115.

The NMOS transistor NM includes a common gate electrode 115, a second gate insulating layer 116 formed on the common gate electrode 115, a P-silicon layer 117 formed on the second gate insulating layer 116, includes the N ⁺ second source / drain regions (118a, 118b) formed to both sides of the P- silicon layer 117.

The first and second drain regions 112b and 118a are connected to the output pad 121a through the contact plug 120, and the first source region 112a is connected to the power supply voltage source V _DD through the contact plug 120. The second source region 118b is connected to the ground voltage source Vss through the contact plug 120.

As described above, in the CMOS inverter according to the preferred embodiment of the present invention, the NMOS transistor NM and the PMOS transistor PM are vertically formed to reduce the overall area of the semiconductor device. As a result, since only one area for forming one transistor is required, it can bring about a 50% area reduction than in the above-mentioned prior art.

In addition, since the NMOS transistor NM and the PMOS transistor PM share one gate electrode 115, there is no need to perform an additional wiring process for connecting them as in the above-mentioned prior art. Therefore, the overall manufacturing process of the semiconductor device can be simplified.

In addition, by using an Al ₂ O ₃ film having a high dielectric constant as the gate insulating film of the NMOS transistor NM and the PMOS transistor PM, a semiconductor device having excellent thermal stability and structural stability can be manufactured.

4A through 4D are cross-sectional views illustrating a method of manufacturing a CMOS inverter according to an exemplary embodiment of the present invention shown in FIG. 3. Here, the same reference numerals among the reference numerals shown in FIGS. 4A to 4D are the same elements performing the same function.

First, as shown in FIG. 4A, a well ion implantation process is performed on the P-type semiconductor substrate 110 to form an N-well region 111.

Subsequently, a mask process and a source / drain ion implantation process are performed to form P ⁺ first source / drain regions 112a and 112b for the PMOS transistor in a portion of the N-well region 111.

Subsequently, a first interlayer insulating layer 113 is deposited on the surfaces of the N-well region 111 and the first source / drain regions 112a and 112b. In this case, the first interlayer insulating layer 113 may include an HDP (High Density Plasma) oxide film, a BPSG (Boron Phosphorus Silicate Glass) film, a PSG (Phosphorus Silicate Glass) film, TEOS (Tetra Ethyle Ortho Silicate), PETEOS (Plasma Enhanced TEOS) film , USG (Un-doped Silicate Glass) film, FSG (Fluorinated Silicate Glass) film, CDO (Carbon Doped Oxide) film and OSG (Organo Silicate Glass) film can be formed of any one.

Subsequently, as shown in FIG. 4B, a via hole (not shown) may be formed to expose the N-well region 111 between the first source / drain regions 112a and 112b by performing a mask process and an etching process. Form.

Subsequently, the first gate insulating layer 114 is formed at the bottom such that a portion of the via hole is filled. In this case, the first gate insulating layer 114 is formed of an Al ₂ O ₃ film having a dielectric constant of at least 9. Here, the Al ₂ O ₃ film is formed by performing a hetero-epitaxy process to form an epitaxial layer having a chemical composition different from that of the semiconductor substrate 110 material.

Subsequently, a polysilicon film is deposited on the first gate insulating layer 114 to fill a portion of the via hole. In this case, the polysilicon film is formed of a doped or undoped polysilicon film by a low pressure chemical vapor deposition (LPCVD) method. For example, in the case of a doped polysilicon film, SiH ₄ and PH ₃ or Si ₂ H ₆ and PH ₃ are used. SiH ₄ or Si ₂ H ₆ is used for the undoped polysilicon film. When the undoped polysilicon film is formed, an impurity ion implantation process is separately performed to implant impurity ions into the undoped polysilicon film.

Next, the polysilicon film remaining on the first interlayer insulating film 113 is removed. In this case, the removal process may be performed by a chemical mechanical polishing (CMP) process, or may be performed by a wet or dry etching process using a photolithography process.

Subsequently, a second gate insulating layer 116 is formed on the polysilicon layer so that the via hole is completely filled. In this case, the second gate insulating layer 116 is formed of the same Al ₂ O ₃ film as the first gate insulating layer 114. Here, the Al ₂ O ₃ film is formed by performing a hetero-epitaxy process of forming an epitaxial layer having a chemical composition different from that of the polysilicon film material under the first gate insulating film.

Subsequently, although not illustrated in the drawings, a step between the first interlayer insulating layer 113 and the second gate insulating layer 116 may be removed by performing a chemical mechanical polishing (CMP) process.

Subsequently, as shown in FIG. 4C, the P-silicon layer 117 is formed on the second gate insulating layer 116. Here, the P-silicon layer 117 functions as a channel region of the NMOS transistor.

Subsequently, the polysilicon layer 118 is deposited along the stepped portion above the resultant P-silicon layer 117 is formed. In this case, the polysilicon film 118 is formed of an N-type doped or undoped polysilicon film by LPCVD. For example, in the case of a doped polysilicon film, SiH ₄ and BCl ₃ (or B ₂ H ₆ ) or Si ₂ H ₆ and BCl ₃ (or B ₂ H ₆ ) are used. In the case of undoped polysilicon film, SiH ₄ or Si ₂ H ₆ is used. In the case of forming the undoped polysilicon film, an impurity ion implantation process is separately performed to implant N-type impurity ions into the undoped polysilicon film.

Subsequently, as shown in FIG. 4D, a partial region of the polysilicon film 118 (see FIG. 4C) is etched to expose the P-silicon layer 117 by performing a CMP process or an etching process.

Subsequently, when the polysilicon film 118 is formed of an undoped polysilicon film, the remaining polysilicon film 118 is doped at a high concentration by performing a mask process and a high concentration source / drain ion implantation process. Of course, the source / drain ion implantation process can also be performed when it is formed from the doped polysilicon film. As a result, N ⁺ second source / drain regions 118a and 118b are formed at both sides of the P-silicon layer 117.

Subsequently, a second interlayer insulating layer 119 is deposited on the resultant formed second source / drain regions 118a and 118b. In this case, the second interlayer insulating layer 119 is deposited using the same material as the first interlayer insulating layer 113.

Subsequently, the mask process and the etching process are performed to expose the first source / drain regions 112a and 112b and the second source / drain regions 118a and 118b in the first and second interlayer insulating layers 113 and 119. Form contact holes (not shown).

Subsequently, a conductive material filling the contact hole is deposited to form a plurality of contact plugs 120.

Subsequently, a wiring process is performed to form first to third wirings 121a to 121c on the plurality of contact plugs 120. In this case, the first wiring 121a is connected to the first and second drain regions 112b and 118a of the PMOS transistor and the NMOS transistor at the same time, and the second wiring is connected to the second source region 118b and the third wiring 121c is connected to the first source region 112a.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, one transistor is formed in common, and one transistor is formed by symmetrically forming an NMOS transistor and a PMOS transistor in a direction perpendicular to each other with the gate electrode interposed therebetween. Since only the area required for, it can bring about 50% area reduction than in the above-mentioned prior art.

In addition, according to the present invention, since the NMOS transistor and the PMOS transistor are formed to share one gate electrode in common, a separate wiring process for connecting each gate electrode is not necessary, thereby simplifying the overall CMOS inverter manufacturing process.

In addition, according to the present invention, by forming each gate insulating film of the NMOS transistor and the PMOS transistor into an Al ₂ O ₃ film having a high dielectric constant, a CMOS inverter device having excellent thermal stability and structural stability can be manufactured.

Claims (7)

Board; A first gate insulating film formed on the substrate; A common gate electrode formed on the first gate insulating layer; First source / drain regions formed on the substrate exposed to both sides of the common gate electrode; A second gate insulating layer formed on the common gate electrode; A conductive silicon layer formed on the second gate insulating layer; And Second source / drain regions formed on both sides of the conductive silicon layer; CMOS device comprising a. The method of claim 1, The first and second gate insulating film is a CMOS device consisting of an Al ₂ O ₃ film. The method of claim 1, And the first and second source / drain regions are formed of different impurity ions. The method of claim 3, wherein And the conductive silicon layer is formed of a conductive type different from the second source / drain region. Forming a well region of a first conductivity type in the semiconductor substrate; Forming a first source / drain region of a second conductivity type in the well region; Depositing a first interlayer insulating film on said well region and said first source / drain region; Forming a via hole exposing the well region between the first source / drain region; Forming a first gate insulating layer on a bottom of the via hole; Forming a common gate electrode on the first gate insulating layer to fill a portion of the via hole; Forming a second gate insulating layer on the common gate electrode to fill the via hole; Forming a second conductive silicon layer on the second gate insulating film; Depositing a polysilicon film over the entire structure to cover the silicon layer; Etching the polysilicon layer to expose the silicon layer; And Implanting first conductivity type impurity ions into the polysilicon layer to form a second source / drain region; Method for manufacturing a CMOS device comprising a. The method of claim 5, wherein And the polysilicon film is a doped polysilicon film doped with a first conductivity type impurity ion or is formed of an undoped polysilicon film. The method according to claim 5 or 6, And the first and second gate insulating layers are formed of an Al ₂ O ₃ film.

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