KR20060095043A - Thin film transistor array panel - Google Patents

Abstract

A thin film transistor array panel according to an exemplary embodiment of the present invention includes a gate line, a data line crossing the gate line, a storage electrode separated from the gate line and the data line, a thin film transistor connected to each gate line and data line, and having a drain electrode, A second insulating film covering the pixel electrode and the thin film transistor connected to the drain electrode, a first insulating film disposed under the pixel electrode, and an upper insulating film formed on the lower insulating film, and having an opening exposing the lower insulating film in a portion corresponding to the sustain electrode. An insulating film is included.

Mask, transmittance, semiconductor, holding capacitance, photoresist

Description

Thin Film Transistor Display Panels {THIN FILM TRANSISTOR ARRAY PANEL}

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

2 and 3 are cross-sectional views of the thin film transistor array panel illustrated in FIG. 1 taken along lines II-II 'and III-III', respectively.

4 is a layout view of a thin film transistor array panel in a first step of manufacturing according to an embodiment of the present invention,

5A and 5B are cross-sectional views taken along the lines Va-Va 'and Vb-Vb' of FIG. 4, respectively.

6A and 6B are cross-sectional views taken along the lines Va-Va 'and Vb-Vb' in FIG. 4, respectively, and are cross-sectional views in the next steps of FIGS. 5A and 5B;

7A and 7B are cross-sectional views taken along the Va-Va 'line and the Vb-Vb' line in FIG. 4, respectively, and are cross-sectional views of the next steps of FIGS. 6A and 6B.

8 is a layout view of a thin film transistor array panel in the next step of FIGS. 7A and 7B.

9A and 9B are cross-sectional views taken along the lines IXa-IXa 'and IXb-IXb' of FIG. 8, respectively.

FIG. 10 is a layout view of a thin film transistor array panel in the next step of FIGS. 9A and 9B.

11A and 11B are cross-sectional views taken along the lines XIa-XIa 'and XIb-XIb' of FIG. 10, respectively.

12 is a layout view illustrating a structure of a thin film transistor array panel according to another exemplary embodiment of the present invention.

FIG. 13 is a layout view illustrating a structure of a common electrode display panel according to an exemplary embodiment.

FIG. 14 is a layout view illustrating a structure of a liquid crystal display including two display panels of FIGS. 12 and 13.

FIG. 15 is a cross-sectional view of the liquid crystal display of FIG. 14 taken along the line XV-XV ′; FIG.

16 is a layout view illustrating a structure of a thin film transistor array panel according to another exemplary embodiment of the present invention.

17 is a layout view illustrating a structure of a common electrode display panel according to another exemplary embodiment of the present invention.

FIG. 18 is a layout view illustrating a structure of a liquid crystal display including two display panels of FIGS. 16 and 17.

19 is a cross-sectional view of the liquid crystal display of FIG. 18 taken along the line XIX-XIX ′;

20 is a layout view illustrating a structure of a thin film transistor array panel according to another exemplary embodiment of the present invention.

FIG. 21 is a layout view illustrating a structure of a common electrode display panel according to another exemplary embodiment.

FIG. 22 is a layout view illustrating a structure of a liquid crystal display including the two display panels of FIGS. 20 and 21.

23 and 24 are cross-sectional views of the liquid crystal display of FIG. 22 taken along lines XXIII-XXIII 'and XXIV-XXIV';

25 is a circuit diagram illustrating a unit pixel in the liquid crystal display of FIGS. 20 to 24.

<Description of the symbols for the main parts of the drawings>

110: substrate 121, 129: gate line

124: gate electrode 140; Gate insulating film

151, 154: semiconductors 161, 163, 165: ohmic contact members

171, 179: data line 173: source electrode

175: drain electrode 180: protective film

181, 182, 185, 185a, 185b: contact hole

190, 190a, 190b: pixel electrodes 81, 82: contact auxiliary members

88: shielding electrode 85: sustain electrode

270: common electrode 220: light blocking member

230: color filter 235, 236: opening

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array panel and to a thin film transistor array panel used as a substrate of a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which field generating electrodes such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light to display an image.

Among the liquid crystal display devices, a field generating electrode is provided on each of two display panels. Among them, a liquid crystal display device having a structure in which a plurality of pixel electrodes are arranged in a matrix form on one display panel and one common electrode covering the entire display panel on the other display panel is mainstream. The display of an image in this liquid crystal display device is performed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor, which is a three-terminal element for switching a voltage applied to a pixel electrode, is connected to each pixel electrode, and a gate line for transmitting a signal for controlling the thin film transistor and a data line for transmitting a voltage to be applied to the pixel electrode are provided. Install on the display panel. In addition, the display panel includes a sustain electrode that overlaps the pixel electrode to form a storage capacitor.

The display panel is manufactured by a photolithography process using a mask. In order to reduce the production cost, it is preferable to reduce the number of masks. For this purpose, a photosensitive film pattern having a medium thickness is formed, and the data line and the semiconductor are used as an etching mask. Techniques for patterning together are being developed.

However, in such a manufacturing method, the storage capacitor overlaps with the storage electrode to form the storage capacitor, and the semiconductor remains in the lower portion of the conductor connected to the pixel electrode, which induces flicker or afterimage that flickers on the screen. It acts as a cause of deterioration of image quality and as a cause of deterioration of aperture ratio of a pixel.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor array panel capable of simplifying a manufacturing process and ensuring excellent image quality.

In addition, another technical problem to be achieved by the present invention is to provide a thin film transistor array panel which can improve the aperture ratio of a pixel.

In order to solve this problem, in the exemplary embodiment of the present invention, a lower portion of the photoresist used as an etch mask is formed between the source electrode and the drain electrode and the upper part of the sustain electrode, so that the lower layer is not etched when some film is etched as necessary. And etch together another layer. At this time, the area occupied by the drain electrode in the portion where the storage capacitor is formed is minimized, and only the inorganic insulating film is left, and the organic insulating film is removed.

A thin film transistor array panel according to an exemplary embodiment of the present invention includes a gate line, a data line crossing the gate line, a storage electrode separated from the gate line and the data line, a thin film transistor connected to each gate line and data line, and having a drain electrode, A second insulating film covering the pixel electrode and the thin film transistor connected to the drain electrode, a first insulating film disposed under the pixel electrode, and an upper insulating film formed on the lower insulating film, and having an opening exposing the lower insulating film in a portion corresponding to the sustain electrode. An insulating film is included.

The first insulating film may be made of an inorganic insulating material, and the second insulating film may be made of an organic insulating material, and the second insulating film may include a color filter.

The sustain electrode is preferably made of the same layer as the gate line.

The contact hole connecting the pixel electrode and the drain electrode is preferably located in the opening.

The thin film transistor array panel according to the present exemplary embodiment may further include a shielding electrode formed of the same layer as the pixel electrode, and the shielding electrode and the pixel electrode are preferably positioned on the first and second insulating layers.

The storage electrode is the same layer as the shielding electrode and may protrude from the shielding electrode, wherein the storage electrode preferably overlaps the drain electrode.

The shielding electrode preferably extends along the data line, and may completely cover the boundary line of the data line.

The shielding electrode preferably overlaps at least a portion of the gate line, and the shielding electrode extends along the gate line and the data line, and is preferably narrower than the gate line and wider than the data line.

The pixel electrode preferably has a cutout, and may include a first pixel electrode and a second pixel electrode which is capacitively coupled to the first pixel electrode.

The display device further includes a capacitive coupling electrode connected to the drain electrode and overlapping the second pixel electrode, and the second pixel electrode and the capacitive coupling electrode overlap each other with only the first insulating layer interposed therebetween.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a structure of a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In the thin film transistor array panel according to the exemplary embodiment, a plurality of gate lines 121 and storage electrode lines 131 may be formed on the insulating substrate 110 to transmit a gate signal.

The gate lines 121 mainly extend in the horizontal direction and are separated from each other, and a part of each gate line 121 forms a plurality of gate electrodes 124, and an area for connecting another layer or an external device. It has a wide end 129.

Each storage electrode line 131 extends mainly in the horizontal direction and is electrically separated from the gate line 121. The storage electrode line 131 may have a protrusion forming the storage electrode, and a predetermined voltage such as a common voltage applied to the common electrode of another display panel is applied to the storage electrode line 131.

The gate line 121 and the storage electrode line 131 are made of a metal such as Al, Al alloy, Ag, Ag alloy, Cr, Ti, Ta, Mo, Cu, or an alloy containing them. As shown in FIG. 2, in the present embodiment, the gate line 121 includes two layers having different physical properties, that is, a lower layer 121p and an upper layer 121q thereon. The lower layer 121p is made of a low resistivity metal such as aluminum (Al) or an aluminum alloy such as aluminum alloy to reduce the delay or voltage drop of the gate signal. Has a thickness. In contrast, the top layer 121q is a material having excellent physical, chemical and electrical contact properties with other materials, particularly indium zinc oxide (IZO) or indium tin oxide (ITO), such as molybdenum (Mo) and molybdenum alloys [see: Molybdenum -Tungsten (MoW) alloy], chromium (Cr), etc., and has a thickness in the range of 100-1,000Å. Examples of the combination of the lower layer 121p and the upper layer 121q include pure aluminum or aluminum-neodymium (Nd) alloy / molybdenum, and the positions may be interchanged. In FIG. 2, the lower and upper layers of the gate electrode 124 are denoted by reference numerals 124p and 124q, and the lower and upper layers of the end portion 129 of the gate line 121 are denoted by reference numerals 129p and 129q, respectively. The lower film and the upper film of) are denoted by reference numerals 131p and 131q, respectively. A portion of the upper layer 129q of the end portion 129 of the gate line 121 may be removed to expose a portion of the lower layer 129p below it.

Side surfaces of the lower layers 121p, 124p, 129p, and 131p and the upper layers 121q, 124q, 129q, and 131q are inclined, respectively, and the sidewall inclination angle is about 30-80 ° with respect to the surface of the substrate 110.

A gate insulating layer 140 made of silicon nitride (SiNx) or the like is formed on the gate line 121 and the storage electrode line 131.

On the gate insulating layer 140, a plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si), polycrystalline silicon, or the like are formed. Each linear semiconductor 151 extends mainly in the longitudinal direction, and each includes a plurality of protrusions 154 extending toward the gate electrode 124.

On top of the linear semiconductor 151, a plurality of linear and island ohmic contacts 161 and 165 made of a material such as n + hydrogenated amorphous silicon doped with silicide or high concentration of n-type impurities are formed. Formed. Each of the linear ohmic contacts 161 has a plurality of protrusions 163, and the protrusions 163 and the island-like resistive contact members 165 are paired and disposed on the protrusions 154 of the semiconductor 151. .

Side surfaces of the linear semiconductor 151 and the ohmic contacts 161 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is preferably 30 to 80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165, respectively.

The data line 171 mainly extends in the vertical direction and crosses the gate line 121 and the storage electrode line 131 to transmit a data voltage, and has a wide end portion for connecting another layer or an external device ( 179).

Each drain electrode 175 extends to an upper portion of the storage electrode line 131 and overlaps a part of the storage electrode line 131.

Each data line 171 also has a source electrode 173 extending from the data line 171 with a plurality of branches toward each drain electrode 175. One gate electrode 124, one source electrode 173, and one drain electrode 175 together with the protrusion 154 of the semiconductor 151 form one thin film transistor (TFT). A channel of the transistor is formed in the protrusion 154 between the source electrode 173 and the drain electrode 175.

Like the gate line 121, the data line 171 and the drain electrode 175 are made of a metal such as Al, Al alloy, Ag, Ag alloy, Cr, Ti, Ta, Mo, Cu, or an alloy containing the same. And a single layer or a multilayer, and examples of the multilayer layer include a double layer formed of a combination of an upper layer and a lower layer of the gate line 121 or a three layer layer of Mo or Mo alloy / Al or Al alloy / Mo or Mo alloy. .

At this time, the semiconductor 151 has a planar shape substantially the same as the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165, except for the channel portion 154 where the thin film transistor is located. Have In detail, the linear semiconductor 151 may include the source electrode 173 and the drain electrode 175 in addition to the data line 171, the drain electrode 175, and the portions below the ohmic contacts 161 and 165. It has an exposed part between them.

On the data line 171 and the drain electrode 175 and the portion of the semiconductor 151 that is not covered by them, an organic material having excellent planarization characteristics and photosensitivity, plasma enhanced chemical vapor deposition Low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or a passivation layer 180 formed of an inorganic material such as silicon nitride or silicon oxide. have. In the present exemplary embodiment, the passivation layer 180 is disposed under the protection layer to protect the channel portion of the semiconductor 151 from being in direct contact with the organic material. It has a double film structure of the upper insulating film 180q. In this case, the upper insulating layer 180q may be a color filter capable of displaying one of primary colors such as red, green, and blue.

The passivation layer 180 includes a plurality of contact holes 185q and 182 exposing at least a portion of the drain electrode 175 and an end portion 179 of the data line 171, respectively, and include a gate insulating layer 140 and a gate insulating layer 140. In addition, a plurality of contact holes 181 exposing the end portion 129 of the gate line 121 are formed. Here, the contact hole 185p exposing the end of the drain electrode 175 has only the lower insulating film 180p, and the upper insulating film 180q has an opening 185q exposing most of the lower insulating film 180p above the storage electrode line 131. ) In the opening 185q, a contact hole 185p exposing an end portion of the drain electrode 175 is disposed, and a vertical boundary of the drain electrode 175 is located in the opening 185q. In this case, in order to minimize the amorphous silicon layer remaining under the drain electrode 175, it is preferable to minimize the area occupied by the drain electrode 175. Particularly, an end portion of the drain electrode 175 positioned above the storage electrode line 131. It is desirable to minimize the area of.

A plurality of pixel electrodes 190 and a plurality of contact assistants 81 and 82 formed of a transparent conductive material such as IZO or ITO are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the contact hole 185p to receive a data voltage from the drain electrode 175. The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules of the liquid crystal layer by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied. .

In addition, as described above, the pixel electrode 190 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off, thereby enhancing the voltage holding capability. In order to do this, another capacitor connected in parallel with the liquid crystal capacitor is provided and is called a "storage capacitor". The storage capacitor is made of the pixel electrode 190 and a neighboring gate line 121 (which is referred to as a "previous gate line") or a superimposition of the storage electrode line 131.

In the present invention, the pixel electrode 190 and the storage electrode line 131 overlap the gate insulating layer 140 and the lower insulating layer 180q through the opening 185q of the upper insulating layer 180q to form a storage capacitor. The holding capacity can be secured stably, and a sufficient holding capacity can be formed in a narrow area. Therefore, the flicker phenomenon or the afterimage of the screen flickering due to the holding capacitance can be prevented, so that excellent display characteristics can be secured and a high aperture ratio can be obtained.

Unlike the present exemplary embodiment, the upper insulating layer 180q exposing the gate insulating layer 140 when the storage capacitor is formed by overlapping the pixel electrode 190 and the gate line 121 of the previous stage without arranging a separate storage electrode line 131. ) May be disposed above the gate line 121 of the front end. In this case, it is preferable that a part of the gate line 121 of the front end overlapping the pixel electrode 190 extends.

In addition, in the embodiment in which the upper insulating layer 180q includes the color filter, the color filter does not remain in the pad region where the end portions 129 and 179 of the gate line 121 and the data line 171 are positioned.

The pixel electrode 190 also overlaps with the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap.

The contact auxiliary members 81 and 82 are connected to the end portions 129 and 179 of the gate line and the data line, respectively, through the contact holes 181 and 182. The contact auxiliary members 81 and 82 serve to protect and protect the adhesion between the end portions 129 and 179 of the gate line 121 and the data line 171 and an external device such as a driving integrated circuit. It is not essential that the application is optional.

According to another embodiment of the present invention, a transparent conductive polymer may be used as the material of the pixel electrode 190, and in the case of a reflective liquid crystal display, an opaque reflective metal may be used. In this case, the contact assistants 81 and 82 may be made of a material different from the pixel electrode 190, in particular, IZO or ITO.

Next, a method of manufacturing the TFT panel for the liquid crystal display device having the structure of FIGS. 1 to 3 will be described in detail with reference to FIGS. 4 to 11B and FIGS. 1 to 3. do.

FIG. 4 is a layout view of a thin film transistor array panel in a first step of manufacturing according to an embodiment of the present invention, and FIGS. 5A and 5B are cross-sectional views taken along lines Va-Va 'and Vb-Vb' in FIG. 4, respectively. 6A and 6B are cross-sectional views taken along the Va-Va 'line and the Vb-Vb' line in FIG. 4, respectively, and are cross-sectional views in the next steps of FIGS. 5A and 5B, and FIGS. 7A and 7B are respectively shown in FIG. 4. 6A and 6B are cross-sectional views taken along the Va-Va 'line and the Vb-Vb' line, and FIG. 8 is a layout view of the thin film transistor array panel at the next steps of FIGS. 7A and 7B. 9A and 9B are cross-sectional views taken along the lines IXa-IXa 'and IXb-IXb' in FIG. 8, respectively, and FIG. 10 is a layout view of the thin film transistor array panel in the next steps of FIGS. 9A and 9B. 11A and 11B are cross-sectional views taken along the lines XIa-XIa 'and XIb-XIb' of FIG. 10, respectively. .

First, sputtering two layers of metal films, that is, a lower metal film of pure aluminum or an Al-Nd alloy and an upper metal film of molybdenum or molybdenum alloy, on an insulating substrate 110 made of transparent glass or the like. Laminate in order. Here, the lower metal film preferably has a thickness of about 1,000-3,000 mm 3, and the upper metal film preferably has a thickness of about 500-1,000 mm 3.

Next, as shown in FIGS. 4, 5A, and 5B, the gate line 121 including the plurality of gate electrodes 124 is patterned by sequentially patterning the upper metal layer and the lower metal layer by a photolithography process using a photoresist pattern. The storage electrode line 131 is formed.

The patterning of the top films 121q and 131q and the bottom films 121p and 131p is an aluminum etchant that can be etched while laterally inclining both aluminum and molybdenum, CH ₃ COOH (acetic acid) / HNO ₃ (nitric acid) / H ₃ It is preferred to proceed by wet etching with PO ₄ (phosphate) / H ₂ O.

6A and 6B, the gate insulating layer 140, the intrinsic amorphous silicon layer 150, and the impurity amorphous silicon layer 160 are each about 1,500 kPa to about 5,000 kPa, using chemical vapor deposition. Continuous deposition is at a thickness of 500 kPa to about 2,000 kPa, from about 300 kPa to about 600 kPa. Subsequently, a conductive layer 170 was formed by stacking the conductive material for data by a method such as sputtering, and then applying a photoresist film having a thickness of 1 μm to 2 μm thereon, and then irradiating light to the photoresist film through a photomask. After development, the photoresist patterns 52 and 54 are formed.

At this time, the thickness of the developed photoresist film varies depending on the position, and the photoresist film is composed of first to third portions whose thickness becomes smaller. The first part located in the area A and the second part located in the area C are denoted by reference numerals 52 and 54, respectively, and no reference is given to the third part located in the area B, which means that the third part has a thickness of zero. This is because the lower conductive layer 170 is exposed. The ratio of the thicknesses of the first portion 52 and the second portion 54 varies depending on the process conditions in the subsequent process, but the thickness of the second portion 54 is 1/2 of the thickness of the first portion 52. It is preferable to set it as the following, for example, it is good that it is 4,000 Pa or less. Here, the region A corresponds to the wiring region corresponding to the data line 171 and the drain electrode 175, the region C corresponds to the channel region between the source electrode 173 and the drain electrode 175, and the region B is Corresponds to areas other than the A and C areas.

At this time, there can be a variety of ways to vary the thickness of the photosensitive film according to the position in the photographic process using a single mask, mainly slit to adjust the light transmission amount of the portion corresponding to the second portion 54 Or form a lattice pattern or use a semi-permeable membrane.

Here, the line width of the pattern located between the slits or the spacing between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure machine used for exposure, and in the case of using a semi-transmissive film, to control the transmittance when manufacturing the mask. For this purpose, thin films having different transmittances or thin films having different thicknesses may be used.

Thereafter, a plurality of data lines 171 each including a plurality of source electrodes 173 as shown in FIGS. 8, 9A and 9B through a series of etching steps using the photoresist patterns 52 and 54 as an etching mask, and A plurality of linear resistive contact members 161, a plurality of island-like resistive contact members 165, and a plurality of channel portions 154 that form a plurality of drain electrodes 175 and each include a plurality of protrusions 163. A plurality of linear semiconductors 151 are formed.

For convenience of description, portions of the conductor layer 170, the impurity amorphous silicon layer 160, and the intrinsic amorphous silicon layer 150 in the region A are referred to as first portions, and the conductor layer 170 and the impurity amorphous in the C region are referred to as first portions. A portion of the silicon layer 160 and the intrinsic amorphous silicon layer 150 is referred to as a second portion, and a portion of the conductor layer 170, the impurity amorphous silicon layer 160, and the intrinsic amorphous silicon layer 150 positioned in the region B is referred to as a second portion. Let's call it the third part.

One example of the order of forming such a structure is as follows.

(1) removing the third portion of the conductor layer 170, the impurity amorphous silicon layer 160 and the amorphous silicon layer 150 located in the region B,

(2) removing the second portion 54 of the photosensitive film located in the region C,

(3) removing the second portion of the conductor layer 170 and the impurity amorphous silicon layer 160 located in region C, and

(4) Removal of the first portion 52 of the photosensitive film located in the region A. FIG.

Another example of this order is as follows.

(1) removing the third portion of conductor layer 170 located in region B,

(2) removing the second portion 54 of the photosensitive film located in the region C,

(3) removing the third portions of the impurity amorphous silicon layer 160 and the amorphous silicon layer 150 located in the region B,

(4) removing the second portion of conductor layer 170 located in region C,

(5) removing the first portion 52 of the photosensitive film located in the region A, and

(6) Removal of the second portion of the impurity amorphous silicon layer 160 located in the C region.

The second example is described here.

First, as illustrated in FIGS. 7A and 7B, the conductive layer 170 exposed to the region B is removed by wet or dry etching to expose the third portion of the lower impurity amorphous silicon layer 160. The aluminum-based conductive film is mainly performed by wet etching, and the molybdenum-based conductive film may be selectively wet and dry etched, and in the case of a multilayer, wet and dry etching may be selectively performed. In addition, when the bilayer includes aluminum and molybdenum, it may be patterned by one wet etching condition. In the case of using dry etching, the upper portion of the photoresist films 52 and 54 may be cut to a certain thickness.

Subsequently, the third portion of the impurity amorphous silicon layer 160 located in the region B and the intrinsic amorphous silicon layer 150 thereunder is removed, and the second photosensitive film 54 in the region C is removed to remove the conductor. (174) Expose the second portion. Removal of the second portion 54 of the photoresist film is performed simultaneously with or separately from removal of the third portion of the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150. At this time, the residue of the second portion 54 remaining in the C region is removed by ashing.

In this step, the linear intrinsic semiconductor 151 is completed. In addition, reference numeral 164 denotes an impurity amorphous silicon layer 160 in which the linear ohmic contact 161 and the island-type ohmic contact 165 are still attached, which is referred to as impurity semiconductor.

Reference numeral 174 denotes a conductor in which the data line 171 and the drain electrode 175 are still attached. In this case, the conductor 174 is etched to the lower portion of the photoresist films 52 and 54 so that the conductor 174 and the photoresist films 52 and 54 have an undercut structure.

Next, as illustrated in FIGS. 8, 9A, and 9B, the second conductor 174 and the second portion of the impurity semiconductor 164 positioned in the C region are etched and removed. In addition, the remaining photoresist first portion 52 is also removed.

In this case, as shown in FIG. 9B, the portion of the linear intrinsic semiconductor 151 located in the region C of the channel portion 154 may be removed to reduce the thickness, and the first portion 52 of the photoresist may also have a certain thickness. Etched.

In this way, each of the conductors 174 is completed while being separated into one data line 171 and a plurality of drain electrodes 175, and each of the impurity semiconductors 164 is formed of one linear ohmic contact 161 and a plurality of electrodes. Completed by dividing into the island resistive contact member 165.

Next, as shown in FIGS. 10, 11A, and 11B, the silicon nitride and the organic insulating material are sequentially formed on the substrate 110 to sequentially include the passivation layer 180 including the lower insulating layer 180p and the upper insulating layer 180q. ), And then patterned by a photolithography process using a mask to form a plurality of contact holes 185p and 182 and a plurality of openings 185q. In this case, the gate insulating layer 140 is also etched together to form a contact hole exposing the same layer as the gate line 121 to form a contact hole 181 exposing the end portion 129 of the gate line 121 together. In this case, the lower insulating layer 180p and the upper insulating layer 180q having different shapes may be patterned by one photolithography process using a photoresist pattern having a different thickness according to a position as an etching mask. In the embodiment including the color filter, the color filter is formed by a separate photo process, and the opening 185q exposing the lower insulating layer 180p on the storage electrode line 131 is formed together.

Lastly, as shown in FIGS. 1 to 3, a IZO or ITO layer having a thickness of 500 μs to 1,500 μs is deposited by a sputtering method and etched to photograph the plurality of pixel electrodes 190 and the plurality of contact assistants 81. 82). In the case of using the IZO layer, the etching is preferably wet etching using an etching solution such as (HNO ₃ / (NH ₄ ) ₂ Ce (NO ₃ ) ₆ / H ₂ O), which does not corrode aluminum. Therefore, the conductive film can be prevented from corroding in the data line 171, the drain electrode 175, and the gate line 121.

In this embodiment, the data line 171, the drain electrode 175, the ohmic contacts 161 and 165, and the semiconductor 151 formed thereunder are formed by a photolithography process using one photoresist pattern as an etching mask. The process can be simplified.

In addition, in the thin film transistor array panel and the method of manufacturing the same according to the present exemplary embodiment, the gate insulating layer 140 and the lower insulating layer disposed between the pixel electrode 190 and the storage electrode line 131 by arranging the opening 185q over the storage electrode line 131. A storage capacitor having only 180p as a dielectric is formed. As a result, by reducing the area of the amorphous silicon remaining under the drain electrode 175, a stable holding capacitor can be formed, and a sufficient holding capacitor can be formed in a narrow area. Therefore, the flicker phenomenon or the afterimage of the screen flickering due to the holding capacitance can be prevented, so that excellent display characteristics can be secured and a high aperture ratio can be obtained.

Meanwhile, as a means for implementing a wide viewing angle, the field generating electrode may have a cutout or a method of forming a protrusion on the field generating electrode. Since the direction in which the liquid crystal molecules are inclined by the cutout and the protrusion can be determined, the wide viewing angle can be secured by dispersing the inclination directions of the liquid crystal molecules in various directions.

12 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment. FIG. 13 is a layout view illustrating a structure of a common electrode display panel for a liquid crystal display according to an exemplary embodiment. 14 is a layout view illustrating a structure of a liquid crystal display device including the thin film transistor array panel of FIG. 12 and the common electrode display panel of FIG. 13, and FIG. 15 is a cross-sectional view of the liquid crystal display of FIG. 14 taken along the line XV-XV ′. to be.

The liquid crystal display according to the exemplary embodiment of the present invention includes a thin film transistor array panel 100, a common electrode display panel 200, and a liquid crystal layer 3 interposed between the two display panels 100 and 200.

The layer structure of the thin film transistor array panel 100 according to the present exemplary embodiment is substantially the same as that of FIGS. 1 to 3.

Referring to the thin film transistor array panel 100, a plurality of gate lines 121 and a plurality of storage electrode lines 131 including the gate electrode 124 are formed on the substrate 110, and the gate insulating layer 140 is disposed thereon. ), A linear semiconductor 151 including the protrusion 154, and a plurality of linear ohmic contact members 161 including the protrusion 163, and a plurality of island-type ohmic contact members 165 are sequentially formed. A plurality of data lines 171 and a plurality of drain electrodes 175 including the source electrode 173 are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140, and the lower insulating layer 180 is formed thereon. A plurality of contact holes 181, 182, and 185 are formed in the lower insulating layer 180 and the gate insulating layer 140. A plurality of pixel electrodes 190 and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180.

Unlike FIGS. 1 to 3, the plurality of gate electrodes 124 form a plurality of protrusions in the gate line 121, and each of the sustain electrode lines 131 forms a plurality of protrusions that form the storage electrode 135. Each includes.

Each drain electrode 175 includes an extension that overlaps with each sustain electrode 135, where the extension of the drain electrode 175 has an area smaller than that of the sustain electrode 135.

The source electrode 173 is bent to partially surround one end of the drain electrode 175 positioned on the protrusion 154 of the semiconductor 151.

In addition, an upper insulating film including a color filter 230 capable of displaying one of primary colors such as red, green, and blue is formed on the lower insulating film 180p to form a protective film. In this case, the color filter 230 has an opening 235 exposing most of the lower insulating layers 180p positioned on the storage electrode 135. The color filter 230 may extend in the vertical direction along the pixel electrode 190, and the color filters 230 positioned in adjacent areas with respect to the data line 171 may display different colors and may be red. It is preferable to display green, blue sequentially.

In this case, the pixel electrode 190 connected to the drain electrode 175 through the contact hole 185 through the opening 235 of the color filter 230 is the same as the previous embodiment through the gate insulating layer 140 and the lower portion. The storage capacitor is formed by overlapping the storage electrode 135 with only the insulating layer 180p therebetween.

The pixel electrode 190 has a substantially rectangular shape in which the left corner of the outer boundary is chamfered, and has a central cutout 91, a lower cutout 92a, and an upper cutout 92b, and the pixel electrode 190 includes these. It is divided into a plurality of areas by the cutouts 91, 92a and 92b. The cutouts 91, 92a, and 92b have almost inverted symmetry with respect to a horizontal center line that bisects the pixel electrode 190 in parallel with the gate line 121.

The lower and upper cutouts 92a and 92b extend obliquely from the right side to the left side of the pixel electrode 190 and are positioned on the lower half and the upper half of the horizontal center line of the pixel electrode 190, respectively. The lower and upper cutouts 92a and 92b extend perpendicular to each other at an angle of about 45 degrees with respect to the gate line 121.

The center cutout 91 is disposed at the center of the pixel electrode 190 and has an inlet at the right side. The inlet of the central incision 91 has a pair of hypotenuses substantially parallel to the lower incision 92a and the upper incision 92b, respectively.

Accordingly, the lower half of the pixel electrode 190 is divided into two regions by the lower cutout 92a, and the upper half is also divided into two regions by the upper cutout 92b. In this case, the number of regions or the number of cutouts may vary depending on the size of the pixel, the ratio of the length of the horizontal side and the vertical side of the pixel electrode, the type and characteristics of the liquid crystal layer 3, and the inclination direction may also vary.

Next, the common electrode display panel 200 will be described with reference to FIGS. 13 to 15.

The light blocking member 220 is formed on the insulating substrate 210 made of transparent glass or the like. The light blocking member 220 has a plurality of openings facing the pixel electrode 190 and having substantially the same shape as the pixel electrode 190, and corresponding to the gate line 121 and the data line 171 and the thin film transistor. It is preferable that it consists of the part corresponding to.

An overcoat 250 is formed on the light blocking member 220, and a common electrode 270 made of a transparent conductor such as ITO or IZO is formed on the light blocking member 220.

The common electrode 270 has a plurality of sets of cutouts 71, 72a, and 72b.

The pair of cutouts 71, 72a, and 72b face the one pixel electrode 190 and include a center cutout 71, a lower cutout 72a, and an upper cutout 72b. Each of the cutouts 71, 72a and 72b is disposed between adjacent cutouts 91, 92a and 92b of the pixel electrode 190 or between the cutouts 92a and 92b and the chamfered hypotenuse of the pixel electrode 190. have. In addition, each cutout 71, 72a, and 72b includes at least one diagonal line extending in parallel with the lower cutout 92a or the upper cutout 92b of the pixel electrode 190.

Each of the lower and upper cutouts 72a and 72b overlaps the sides along the sides of the pixel electrode 190 from an oblique portion extending from the left side of the pixel electrode 190 toward the upper or lower side, and from each end of the diagonal portion. It includes a horizontal portion and a vertical portion extending while forming an obtuse angle with the oblique portion.

The central cutout 71 is a central horizontal portion extending in a horizontal direction from the left side of the pixel electrode, and a pair of diagonal lines extending toward the right side of the pixel electrode 190 at an angle with the central horizontal portion at the end of the central horizontal portion. And a vertical longitudinal portion extending from the end of the diagonal portion and overlapping with the right side along the right side of the pixel electrode and forming an obtuse angle with the diagonal portion.

The number and direction of the cutouts 71, 72a, and 72b may also vary depending on the design element, and the light blocking member 220 overlaps the cutouts 71, 72a, and 72b and is located near the cutouts 71, 72a, and 72b. Can block light leaks.

Vertical alignment layers 11 and 21 are coated on the inner surfaces of the display panels 100 and 200, and polarizing plates 12 and 22 are provided on the outer surfaces thereof. The transmission axes of the two polarizing plates are orthogonal and one of the transmission axes is parallel to the gate line 121. In the case of a reflective liquid crystal display, one of the two polarizing plates 12 and 22 may be omitted.

A phase retardation film may be interposed between the display panels 100 and 200 and the polarizers 12 and 22 to compensate for the delay value of the liquid crystal layer 3, respectively. The phase retardation film has birefringence and serves to reversely compensate for the birefringence of the liquid crystal layer 3. As the retardation film, a uniaxial or biaxial optical film can be used, and in particular, a negative uniaxial optical film can be used.

The liquid crystal display may also include a polarizer 12 and 22, a phase retardation film, display panels 100 and 200, and a backlight unit for supplying light to the liquid crystal layer 3.

The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules 310 of the liquid crystal layer 3 are aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field. Therefore, incident light does not pass through the quadrature polarizers 12 and 22 and is blocked.

When a common voltage is applied to the common electrode 270 and a data voltage is applied to the pixel electrode 190, an electric field almost perpendicular to the surface of the display panel is generated. The liquid crystal molecules 310 try to change the direction of the long axis perpendicular to the direction of the electric field in response to the electric field. Meanwhile, the hypotenuses of the cutouts 71, 72a, 72b, 91, 92a, and 92b of the common electrode 270 and the pixel electrode 190 and the pixel electrode 190 parallel to the distorted electric field incline the liquid crystal molecules. Create a horizontal component that determines the direction. The horizontal component of the electric field is perpendicular to the sides of the cutouts 71, 72a, 72b, 91, 92a, 92b and the hypotenuse of the pixel electrode 190. In addition, the horizontal components of the electric fields at two opposite sides of the cutouts 71, 72a, 72b, 91, 92a, and 92b are opposite to each other.

Through these electric fields, the cutouts 71, 72a, 72b, 91, 92a, and 92b control the direction in which the liquid crystal molecules of the liquid crystal layer 3 are inclined. Liquid crystal molecules in each domain defined by adjacent cutouts 71, 72a, 76b, 91, 92a, and 92b or defined by the left hypotenuse of the cutouts 72a and 72b and the pixel electrode 190 may be cut out. Inclined in the direction perpendicular to the longitudinal direction of (71, 72a, 72b, 91, 92a, 92b). The two longest sides of each domain are substantially parallel to each other, and form approximately ± 45 degrees with the gate line 121, and most of the liquid crystal molecules in the domain are inclined in four directions.

The width of the cutouts 91, 92a, 92b, 71, 72a, 72b is preferably about 9 μm to about 12 μm.

At least one cutout 91, 92a, 92b, 71, 72a, 72b may be replaced with a protrusion (not shown) or a depression (not shown). The protrusions may be made of organic or inorganic materials and may be disposed above or below the field generating electrodes 190 and 270, and the width thereof is preferably about 5 μm to about 10 μm.

Meanwhile, when the inclination direction of the liquid crystal molecules 310 and the transmission axis of the polarizers 12 and 22 are 45 degrees, the highest luminance can be obtained. In the present embodiment, the inclination direction of the liquid crystal molecules 310 in all domains is the gate line. The gate line 121 is perpendicular or horizontal to the edges of the display panels 100 and 200 at an angle of 45 ° with the 121. Therefore, in the present exemplary embodiment, when the transmission axes of the polarizers 12 and 22 are attached to be perpendicular or parallel to the edges of the display panels 100 and 200, the highest luminance can be obtained and the polarizers 12 and 22 can be manufactured at low cost. Can be.

The shape and arrangement of the incisions 91, 92a, 92b, 71, 72a, 72b can be modified.

Many features of the thin film transistor array panel described in the previous embodiment may also be applied to the thin film transistor array panel illustrated in FIGS. 12 to 15.

FIG. 16 is a layout view of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment. FIG. 17 is a layout view of a common electrode display panel for a liquid crystal display according to another exemplary embodiment. FIG. 19 is a layout view of a liquid crystal display including the thin film transistor array panel and the common electrode panel illustrated in FIG. 17, and FIG. 19 is a cross-sectional view of the liquid crystal display of FIG. 18 taken along the line XIX-XIX ′.

16 to 19, the liquid crystal display according to the present exemplary embodiment also includes a thin film transistor array panel 100, a common electrode display panel 200, and a liquid crystal layer 3 inserted between the two display panels 100 and 200. And a pair of polarizers 12 and 22 attached to outer surfaces of the two display panels 100 and 200.

The layered structure of the display panels 100 and 200 according to the present exemplary embodiment is substantially the same as the layered structure of the display panels 100 and 200 illustrated in FIGS. 12 to 15.

Referring to the thin film transistor array panel 100, a plurality of gate lines 121 including the gate electrode 124 are formed on the substrate 110, and the protrusions 154 are disposed on the gate insulating layer 140. A plurality of linear ohmic contacts 161 and a plurality of island-type ohmic contacts 165 having a plurality of linear semiconductors 151 and protrusions 163 are formed in this order. A plurality of data lines 171 and a plurality of drain electrodes 175 including the source electrode 173 are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140, and the lower insulating layer 180p and the color are formed. The filters 230 are sequentially formed, and a plurality of contact holes 181, 182, and 185 are formed in the lower insulating layer 180p and the gate insulating layer 140. The color filter 230 has an opening 235 exposing the lower insulating layer 180p and the contact hole 185, and the plurality of pixel electrodes 190 and the plurality of contact auxiliary members 81 and 82 are disposed on the passivation layers 180p and 230. ) Is formed, and the alignment film 11 is formed thereon.

Referring to the common electrode display panel 200, the light blocking member 220, the overcoat 250, the common electrode 270, and the alignment layer 21 are formed on the insulating substrate 210.

However, unlike FIGS. 12 to 15, the drain electrode 175 extends to the center portion of the pixel electrode 190 and has an extended portion extending in the horizontal direction, and the opening 235 of the color filter 230 is the drain electrode 175. Reveals the extension of. The opening 235 extends to the contact hole 185 connecting the pixel electrode 190 and the drain electrode 175, which may not be the case.

Four corners of the pixel electrode 190 are chamfered to form a hypotenuse, and a shielding electrode 88 is formed on the same layer.

In this case, the length of the chamfered hypotenuse in the chamfering structure is preferably in the range of about 4-10 μm, in particular, at least twice the resolution of the exposure apparatus used in the photographing process for forming the pixel electrode 190 and the shielding electrode 88. It is preferable. In this way, the probability that the conductor remains at the corner of the pixel electrode 190 can be greatly reduced, so that the short circuit between the pixel electrode 190 and the shielding electrode 88 can be prevented, and the pixel electrode 190 can be prevented. And the distance between the shielding electrode 88 can be made close.

In addition, when the pixel electrode 190 and the shielding electrode 88 are short-circuited at the corners of the pixel electrode 190, the short-circuit using low magnification optics is used because the distance between the shielding electrode 88 and the pixel electrode 190 is wide there. Not only can the position be easily detected, but a short circuit can be easily repaired using a laser.

The shielding electrode 88 includes a vertical portion extending along the data line 171 and a horizontal portion extending along the gate line 121. The vertical portion completely covers the data line 171, and the horizontal portion covers the gate line 121. It is located inside the boundary of.

A common voltage is applied to the shielding electrode 88. The common electrode is connected to the storage electrode line 131 through a contact hole (not shown) of the passivation layer 180 and the gate insulating layer 140, or the common voltage is applied to the thin film transistor array panel. The display device may be connected to a short point (not shown) transferred from the 100 to the common electrode display panel 200. At this time, it is preferable to minimize the distance between the shielding electrode 88 and the pixel electrode 190 so that the aperture ratio decreases to a minimum.

As such, when the shielding electrode 88 to which the common voltage is applied is disposed on the data line 171, the shielding electrode 88 is disposed between the data line 171 and the pixel electrode 190, and the data line 171 and the common electrode ( By blocking the electric field formed between the 270, the voltage distortion of the pixel electrode 190 and the signal delay of the data voltage transmitted by the data line 171 are reduced.

Also, in order to prevent a short circuit between the pixel electrode 190 and the shielding electrode 88, a distance is required between them so that the pixel electrode 190 is further away from the data line 171, thereby reducing the parasitic capacitance therebetween. Furthermore, since the permittivity of the liquid crystal layer 3 is higher than that of the passivation layer 180, the parasitic capacitance between the data line 171 and the shielding electrode 88 is absent when the shielding electrode 88 is absent. It is smaller than the parasitic capacitance between 171 and the common electrode 270.

In addition, since the pixel electrode 190 and the shielding electrode 88 are made of the same layer, the distance between them is kept constant and thus the parasitic capacitance between them is constant.

In addition, the shielding electrode 88 extends in the horizontal direction and is positioned in the recess of the pixel electrode 190, and overlaps the storage electrode 85 with the drain electrode 175 through the opening 235 of the color filter 230. Has The drain electrode 175 to which the pixel voltage is transmitted and the storage electrode 85 to which the common voltage is transmitted overlap each other to form a storage capacitor. As described above, the shielding electrode 88 is extended to overlap the drain electrode 175 to form the storage capacitor. In this embodiment, a separate storage electrode line is not required as in the previous embodiment. At this time, the drain electrode 175 and the sustain electrode portion 85 overlap each other with only the lower insulating layer 180p interposed therebetween, so that the storage capacitance can be sufficiently secured in a narrow area, thereby minimizing the area of the opaque drain electrode 175. Through this, the aperture ratio of the pixel can be maximized. In this case, the sustain electrode 85 of the shielding electrode 88, the opening of the color filter 230, and the extension of the drain electrode 175 may be modified in various forms to improve display characteristics of the liquid crystal display.

Also, cutouts 91a, 91b, 92a, 92b, 93a, 93b, 94a, 94b, 95a, 95b of the pixel electrode 190, and cutouts 71, 72, 73a, 73b, 74a, of the common electrode 270. The arrangement and shape of 74b, 75a, 75b) is different from the previous embodiment. Notches are formed in the cutouts 72, 73a, 73b, 74a, and 74b of the common electrode 270 to control the alignment of the liquid crystal molecules 310 in the cutouts 72, 73a, 73b, 74a, and 74b.

The light blocking member 220 includes a portion corresponding to the data line 171 and a portion corresponding to the thin film transistor.

In addition, since the same common voltage is applied to the common electrode 270 and the shielding electrode 88, there is almost no electric field between the two. Therefore, since the liquid crystal molecules positioned between the common electrode 270 and the shielding electrode 88 maintain the initial vertical alignment state, light incident on the portion is not transmitted and is blocked.

Many of the features of the liquid crystal display shown in the previous embodiment may be applied to the liquid crystal display shown in FIGS. 16 to 19.

FIG. 20 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment. FIG. 21 is a layout view illustrating a structure of a common electrode display panel for a liquid crystal display according to another exemplary embodiment. 21 is a layout view illustrating a structure of a liquid crystal display device including the thin film transistor array panel of FIG. 20 and the thin film transistor array panel of FIG. 21, and FIGS. 23 and 24 illustrate lines XXIII-XXIII ′ of the liquid crystal display of FIG. 21; 25 is a cross-sectional view taken along the line XXIV-XXIV ', and FIG. 25 is a circuit diagram illustrating the configuration of one pixel in the liquid crystal display according to the exemplary embodiment of the present invention.

The liquid crystal display according to the present exemplary embodiment also includes a thin film transistor array panel 100, a common electrode panel 200 facing the same, and a liquid crystal layer 3 interposed between the two display panels 100 and 200.

The layered structures of the display panels 100 and 200 according to the present exemplary embodiment are substantially the same as those of FIGS. 16 to 19.

Referring to the thin film transistor array panel 100, a plurality of gate lines 121 including the gate electrode 124 are formed on the substrate 110, and have a gate insulating layer 140 and a protrusion 154 thereon. A plurality of linear ohmic contacts 161 and a plurality of island-type ohmic contacts 165 having a plurality of linear semiconductors 151 and protrusions 163 are formed in this order. A plurality of data lines 171 and a plurality of drain electrodes 175 including the source electrode 173 are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140, and the lower insulating layer 180p and the color are formed. The filters 230 are sequentially formed, and a plurality of contact holes 181 and 182 are formed in the lower insulating layer 180p and the gate insulating layer 140. A plurality of first and second pixel electrodes 190a and 190b and a plurality of contact auxiliary members 81 and 82 are formed on the passivation layers 180p and 230, and an alignment layer 11 is formed thereon.

Referring to the common electrode display panel 200, the light blocking member 220, the overcoat 250, the common electrode 270, and the alignment layer 21 are formed on the insulating substrate 210.

Unlike the liquid crystal display of FIGS. 16 to 19, a plurality of storage electrode lines 131a and 131b are formed on the same layer as the gate line 121.

Each of the storage electrode lines 131a and 131b mainly extends in the horizontal direction and is disposed in pairs between the adjacent gate lines 121. Each of the storage electrode lines 131a and 131b is positioned near the gate lines 121 adjacent to each other, and includes a plurality of protrusions forming the storage electrodes 135a and 135b, respectively. The two storage electrodes 135a and 135b extend in a wider width than the other portions, and the two storage electrode lines 131a and 131b are centerlines of the first and second pixel electrodes 190a and 190b parallel to the gate line 121. It is symmetrical with respect to.

Each of the drain electrodes 175 is positioned at the top and the bottom of the region surrounded by the gate line 121 and the data line 171 to overlap the storage electrodes 135a and 135b, respectively. It includes. Each of the extensions 175a and 175b of the drain electrode 175 has an area smaller than that of the sustain electrodes 135a and 135b to maximize the area of the sustain electrodes 135a and 135b that are not covered by the extensions 175a and 175b. It is preferable to form a symmetrical structure with respect to the center line of the first and second pixel electrodes 190a and 190b parallel to the gate line 121.

In addition, the drain electrode 175 includes a capacitive coupling electrode 176 positioned in the center of the region surrounded by the gate line 121 and the data line 171.

The drain electrode 175 also has connecting portions 177a and 177b connecting the two extension portions 175a and 175b and the capacitive coupling electrode 176 to each other.

The lower insulating layer 180 is provided with a plurality of contact holes 185a and 185b respectively exposing the extension portions 175a and 175b of the pair of drain electrodes 175.

A pair that exposes the gate insulating layer 140 and the extension portions 175a and 175b of the drain electrode in which the contact holes 185a and 185b are located, respectively, in the color filter 230 as the upper insulating layer. The openings 236 exposing the openings 235a and 235b and the capacitive coupling electrode 176 are formed.

Here, the first and second pixel electrodes 190a and 190b are separated from each other through a gap formed by the cutouts 93a and 93b, and the first pixel electrode 190a is drained through the contact holes 185a and 185b. It is physically and electrically connected to the extension portions 175a and 175b of the electrode 175 to receive a data voltage from the drain electrode 175. The second pixel electrode 190b overlaps the capacitive coupling electrode 176 of the drain electrode 175. Accordingly, the second pixel electrode 190b is electromagnetically coupled (capacitive) to the first pixel electrode 190a to indirectly apply a data voltage. In this case, the capacitive coupling electrode 176 overlaps the second pixel electrode 190b through the opening 236 of the color filter 230 with only the lower insulating layer 180p interposed therebetween, thereby providing sufficient coupling capacitance with a narrow area. It can be ensured, through which the aperture ratio can be improved. In addition, the first pixel electrode 190a and the storage electrodes 135a and 135b may pass through the lower insulating layer 180p and the gate insulating layer through the openings of the openings 235a and 235b of the color filter 230 that are wider than the drain electrode 175. Since only 140) is overlapped, the holding capacity can be sufficiently formed in a narrow area, and the opening ratio can be prevented from being resisted.

The pair of first and second pixel electrodes 190a and 190b substantially exist in an area surrounded by the data line 171 and the gate line 121, and most of the boundary is formed between the gate line 121 and the data line 171. Parallel to form a rectangle.

In this case, the first pixel electrode 190a may be separated from each other and may be formed of two parts positioned at an upper portion and a lower portion with respect to the second pixel electrode 190b. The gaps 93a and 93b separating the two portions of the first pixel electrode 190a and the second pixel electrode 190b have sides that are inclined by ± 45 ° with respect to the gate line 121. The first and second pixel electrodes 190a and 190b may be sandwiched between two portions of the first pixel electrode 190a, and the first and second pixel electrodes 190a may be parallel to the gate line 121. , 190b) has a symmetrical structure with respect to the centerline.

In addition, the common electrode 270 and the first and second pixel electrodes 190a and 190b may have cutouts 71, 72, 73, 74a, 74b, 75a, 75b, 76a, 76b, 91, 92, 93a, 93b, 94a, 94b, 95a, 95b), which define a plurality of domains. In this case, the number of domains or the number of cutouts varies depending on the size of the pixel, the ratio of the lengths of the horizontal and vertical sides of the first and second pixel electrodes 190a and 190b, and the type and characteristics of the liquid crystal layer 3. .

In the liquid crystal display according to the exemplary embodiment of the present invention, as described above, the second pixel electrode 190b is electromagnetically coupled (capacitively coupled) to the first pixel electrode 190a. Referring to FIG. 25, two portions of the first pixel electrode 190a are directly connected to the thin film transistor Q through the drain electrode 175 and transferred through the data line 171 through the thin film transistor Q. The voltage of the second pixel electrode 190b is changed by capacitive coupling with the first pixel electrode 190a as opposed to receiving the image signal voltage. In this embodiment, the voltage of the second pixel electrode 190b is always lower than the voltage of the first pixel electrode 190a, and the reason thereof will be described in detail.

In FIG. 25, Clca represents a liquid crystal capacitor formed between the first pixel electrode 190a and the common electrode 270, and Csta represents a storage capacitor formed between the first pixel electrode 190a and the storage electrode line 131. . Clcb represents the liquid crystal capacitance formed between the second pixel electrode 190b and the common electrode 270, Cstb represents the storage capacitance formed between the second pixel electrode 190b and the storage electrode line 131, and Ccp represents A coupling capacitor formed between the second pixel electrode 190b and the first pixel electrode 190a is shown.

When the voltage of the first pixel electrode 190a with respect to the voltage of the common electrode 270 is called Va, and the voltage of the second pixel electrode 190b is called Vb, according to the voltage division law,

Vb = Va × [Ccp / (Ccp + Clcb + Cstb)]

Since Ccp / (Ccp + Clcb + Cstb) cannot always be greater than 1, Vb is always smaller than Va. At this time, the voltage of the common electrode 270 for Clca and Clcb and the voltages of the sustain electrode lines 131a and 131b for Csta and Cstb may be different. In this case, the voltage of the common electrode 270 applied to Clca and Clcb is the same. The absolute value of the image signal voltage Va applied to Clca always has a value greater than the absolute value of the image signal voltage Vb applied to Clcb. As such, when two pixel electrodes having different voltages are disposed in one pixel, the liquid crystal molecules may be driven at different voltages to be inclined at different tilt angles, thereby improving side visibility.

By adjusting Ccp, the ratio of Vb to Va can be adjusted. The adjustment of Ccp is possible by adjusting the overlapping area and distance of the capacitive coupling electrode 176 and the second pixel electrode 190b. The overlap area can be easily adjusted by changing the width of the capacitive coupling electrode 176, and the distance can be adjusted by changing the formation position of the capacitive coupling electrode 176. That is, in the exemplary embodiment of the present invention, the capacitive coupling electrode 176 is formed on the same layer as the data line 171, but the capacitive coupling electrode 176 and the second pixel are formed on the same layer as the gate line 121. The distance between the electrodes 190b may be increased. At this time, it is preferable that Vb is 0.6 to 0.8 times with respect to Va.

Meanwhile, in another embodiment, a voltage whose absolute value is always higher than the voltage of the first pixel electrode 190a may be applied to the second pixel electrode 190b, which may be applied to the second pixel electrode 190b such as a common voltage. This is achieved by capacitively coupling the first pixel electrode 190a while an arbitrary voltage is applied.

The area ratio of the second pixel electrode 190b through which the high or low pixel voltage is transmitted with respect to the first pixel electrode 190a through which the image signal is directly transmitted is in a range of 1: 0.85-1: 1.15, and the first pixel Two or more second pixel electrodes 190b may be disposed to be capacitively coupled to the electrodes 190a.

As described above, according to the exemplary embodiment of the present invention, different thin films may be patterned in one photolithography process using a photosensitive film pattern having an intermediate thickness to simplify the manufacturing process, thereby minimizing the manufacturing cost.

In addition, by minimizing the remaining of the semiconductor between the pixel electrode and the sustain electrode line constituting the storage capacitor and by arranging a dielectric with only an insulating film of an inorganic insulating material, it is possible to stably and sufficiently secure the storage capacitor of the storage capacitor, thereby stable display characteristics. It can be ensured, and the aperture ratio of the pixel can be maximized.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (18)

Gate Line, A data line intersecting the gate line, A storage electrode separated from the gate line and the data line, A thin film transistor connected to each of the gate lines and the data lines and having a drain electrode, A pixel electrode connected to the drain electrode, A first insulating film covering the thin film transistor and disposed under the pixel electrode; A second insulating film formed over the first insulating film and having an opening that exposes the first insulating film in a portion corresponding to the sustain electrode; Thin film transistor array panel comprising a. In claim 1, The thin film transistor array panel of which the first insulating layer is made of an inorganic insulating material. In claim 2, The second insulating layer is a thin film transistor array panel made of an organic insulating material. In claim 3, The second insulating layer may include a color filter. In claim 1, And the sustain electrode is formed of the same layer as the gate line. In claim 1, And a contact hole connecting the pixel electrode and the drain electrode to be in the opening. In claim 1, And a shielding electrode formed of the same layer as the pixel electrode. In claim 7, The shielding electrode and the pixel electrode are disposed on the first and second insulating layers. In claim 8, The sustain electrode is the same layer as the shielding electrode and protrudes from the shielding electrode. In claim 9, The sustain electrode overlaps the drain electrode. In claim 7, The shielding electrode extends along the data line. In claim 11, The shielding electrode completely covers a boundary line of the data line. In claim 7, The shielding electrode overlaps at least partially with the gate line. In claim 13, The shielding electrode extends along the gate line and the data line. The method of claim 14, The shielding electrode is narrower than the gate line and wider than the data line. In claim 1, The pixel electrode has a cutout. In claim 1, The pixel electrode includes a first pixel electrode and a second pixel electrode capacitively coupled to the first pixel electrode. The method of claim 17, A capacitive coupling electrode connected to the drain electrode and overlapping the second pixel electrode; The second pixel electrode and the capacitive coupling electrode overlap each other with only the first insulating layer interposed therebetween.

Images