KR20060087640A - Non-volatile memory device having side wall gate electrode and method of fabricating the same - Google Patents

Abstract

Disclosed are a nonvolatile memory device having sidewall gate electrodes and a method of manufacturing the same. A nonvolatile memory device according to the present invention includes a main gate electrode formed on an active region of a semiconductor substrate, sidewall gate electrodes formed on both sidewalls of the main gate electrode, and a storage node formed through insulating layers between the main gate electrode and the semiconductor substrate; And a source and a drain respectively formed in the active region of the semiconductor substrate including the outer sidewall gate electrodes.

Description

Non-volatile memory device having a sidewall gate electrode and a method of manufacturing the same {Non-volatile memory device having side wall gate electrode and method of fabricating the same}

1 is a cross-sectional view illustrating a conventional Sonos type nonvolatile memory device.

2 is a cross-sectional view illustrating a nonvolatile memory device according to an embodiment of the present invention.

3 to 7 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

FIG. 8 is a graph illustrating a threshold voltage transition time according to 1 / V _d of a conventional sonos type nonvolatile memory device and a nonvolatile memory device according to an exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to non-volatile memory devices and methods of manufacturing the same.

Recently, due to the expansion of the mobile phone or digital camera market, there is an increasing demand for a nonvolatile memory capable of storing data therein even when power is cut off, despite a high processing speed, unlike a DRAM used in a conventional computer.

As an example of such a nonvolatile memory, a nonvolatile memory having a floating gate type or a charge trap type storage node structure is widely used to conserve charge. As a charge trapping storage node, a memory having a silicon nitride film is also called a SONOS type memory in view of its structure. For example, the charge trapping storage node has an oxide / nitride / oxide structure. Hereinafter, a conventional sonos type nonvolatile memory 100 will be described with reference to the drawings.

1 is a cross-sectional view illustrating a conventional Sonos type nonvolatile memory 100. Referring to FIG. 1, a storage node 115 and insulating layers 110 and 120 are interposed between the gate electrode 130 and the semiconductor substrate 105. The storage node 115 may be formed of a silicon nitride layer, and the insulating layers 110 and 120 may be formed of a silicon oxide layer. The spacer insulating layer 140 may be formed on the sidewall of the gate electrode 130.

The source 150 and the drain 155 are formed on the outer semiconductor substrate 105 of the gate electrode 130. However, a portion of the source 150 and the drain 155 may overlap the gate electrode 130. This is because the source 150 and the drain 155 are formed by impurity ion implantation and heat treatment because impurities diffuse sideways in the heat treatment step.

On the other hand, the read operation of the conventional sonos-type memory 100 may be performed by grounding the source 150 and applying a first read voltage to the drain 155 and a second read voltage to the gate electrode 130. In this case, a soft program phenomenon may occur in which some of the electrons accelerated by the voltage applied to the drain 155 overlap the drain 155 or are injected into the adjacent storage node 115.

The soft program phenomenon may shift the threshold voltage of the semiconductor substrate 105. Accordingly, disturbance may occur in the read operation. In particular, as the read operation is repeatedly performed over time, such a threshold voltage transition increases, and read disturbance becomes more serious.

On the other hand, in order to reduce the threshold voltage transition and thus the read failure, the voltage applied to the drain 155 should be reduced. However, when the voltage of the drain 155 is reduced, a problem arises in that the read current is decreased and the operating speed of the memory 100 is lowered.

An object of the present invention is to provide a nonvolatile memory device capable of reducing read disturbance.

Another object of the present invention is to provide a method of manufacturing a nonvolatile memory device that can reduce read disturbance.

According to an aspect of the present invention for achieving the above technical problem, a main gate electrode formed on the active region of the semiconductor substrate; Sidewall gate electrodes formed on both sidewalls of the main gate electrode; A storage node interposed between the main gate electrode and the semiconductor substrate; A first insulating layer interposed between the semiconductor substrate and the storage node; A second insulating film interposed between the main gate electrode and the storage node; A third insulating film interposed between the main gate electrode and the sidewall gate electrodes and between the sidewall gate electrodes and the semiconductor substrate; And a source and a drain respectively formed in an active region of the semiconductor substrate including outer sidewalls of the sidewall gate electrodes.

The source and drain preferably include a first portion formed outside the sidewall gate electrodes and a second portion partially overlapping the sidewall gate electrode.

In addition, the storage node is preferably formed of silicon nitride, and may further be formed of nano-dots or nano-crystals.

The memory device may further include a metal wiring electrically connecting the main gate electrode and the sidewall gate electrodes.

According to an aspect of the present invention for achieving the above another technical problem, forming a first insulating layer on the active region of the semiconductor substrate; Forming a storage node layer on the first insulating layer; Forming a second insulating layer on the storage node layer; Forming a main gate electrode layer on the second insulating layer; Patterning the main gate electrode layer to form a main gate electrode; Forming a third insulating layer on an entire surface of the resultant product on which the main gate electrode is formed; Forming a sidewall gate electrode layer on the third insulating layer; Anisotropically etching the sidewall gate electrode layer to form sidewall gate electrodes on both sidewalls of the main gate electrode; And forming a source and a drain respectively formed in an active region of the semiconductor substrate including outer sides of the sidewall gate electrodes.

The storage node layer is preferably formed of a silicon nitride layer, but may also be formed of nano-dots or nano-crystals.

The method may further include forming a wiring metal connecting the main gate electrode and the sidewall gate electrodes after the source and drain forming step.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. In the drawings, the components are exaggerated in size for convenience of description.

2 is a cross-sectional view illustrating a nonvolatile memory device 200 according to an embodiment of the present invention.

2, the memory device 200 includes a plurality of gate electrodes 230 and 240. Sidewall gate electrodes 240 are formed on both sidewalls of the main gate electrode 230. In this case, the main gate electrode 230 and the sidewall gate electrodes 240 are insulated from each other by the spacer insulating layer 235 interposed therebetween.

More specifically, the main gate electrode 230 and the sidewall gate electrodes 240 may be formed to include polysilicon doped with an impurity to have conductivity. For example, the main gate electrode 230 and the sidewall gate electrodes 240 may be formed of a polysilicon / metal composite layer. The spacer insulating layer 235 may be formed to include a silicon oxide layer.

The storage node 215 is interposed between the main gate electrode 230 and the active region of the semiconductor substrate 205. A blocking insulating film 220 is formed between the main gate electrode 230 and the storage node 215, and a tunneling insulating film 210 is formed between the storage node 215 and the semiconductor substrate 205. Is formed. Meanwhile, although the active region is defined by the device isolation region in the semiconductor substrate 205, only the active region is shown in the drawing, and thus the active region and the semiconductor substrate 205 are not largely divided.

More specifically, the storage node 215 is preferably formed of a silicon nitride film. Furthermore, the storage node 215 may be formed of nano-dots or nano-crystals. The blocking insulating layer 220 is to insulate the main gate electrode 230 from the storage node 215 and may be, for example, a silicon oxide layer.

The tunneling insulating layer 210 serves as a tunnel through which charge is transferred between the storage node 215 and the semiconductor substrate 205. For example, during a write operation, electrons may be injected from the semiconductor substrate 205 through the tunneling insulating layer 210 to the storage node 215 by a tunneling phenomenon. The tunneling insulating layer 210 may be a thin silicon oxide layer.

On the other hand, the source 250 and the drain 255 are formed in the active region of the semiconductor substrate 205 including the outside of the sidewall gate electrodes 240, respectively. In this case, the source 250 preferably includes a first portion 250a formed outside the sidewall gate electrode 240 and a second portion 250b partially overlapping the sidewall gate electrode 240. Similarly, the drain 255 preferably includes a first portion 255a formed outside the sidewall gate electrode 240 and a second portion 255b partially overlapping the sidewall gate electrode 240.

That is, although the source 250 and the drain 255 may partially overlap the sidewall gate electrode 240, the source 250 and the drain 255 are spaced apart from the outside without being overlapped with the storage node 215. Therefore, even when a relatively high voltage is applied to the drain 255 during a read operation, a soft program phenomenon in which charge is directly injected into the storage node 215 from the drain 255 or from the semiconductor substrate 205 adjacent to the drain 255 is prevented. Can be effectively suppressed.

However, unlike the related art, in order to conduct the source 250 and the drain 255 by turning on the channel of the semiconductor substrate or the active region 205, the sidewalls as well as the main gate electrode 230 may be formed. The turn-on voltage must also be applied to the gate electrodes 240.

Therefore, the main gate electrode 230 and the sidewall gate electrodes 240 may further include a metal wire (not shown) electrically connecting the main gate electrode 230 and the sidewall gate electrodes 240. desirable. Although the metal wiring is not shown in the drawings, it will be apparent to those skilled in the art that the metal wiring can be easily performed.

FIG. 8 is a graph illustrating a threshold voltage transition time according to 1 / V _d of a conventional sonos type nonvolatile memory device (100 of FIG. 1) and a nonvolatile memory device (200 of FIG. 2) according to an exemplary embodiment of the present invention. . As the memory device (100 in FIG. 1 and 200 in FIG. 2) is repeatedly read over time, the threshold voltage continues to shift due to the soft program phenomenon. In this case, the normal operation time without read failure or negligibly small is determined until the threshold voltage has shifted by a threshold value, for example, about 0.2V.

Referring to FIG. 8, in the case of using the conventional Sonos type memory device (100 of FIG. 1), a voltage (V) applied to a drain in order to ensure a normal operating time of 10 years, that is, to suppress a read failure for 10 years. _d ) should be kept below 1.43 V. On the other hand, when using the memory device (200 of FIG. 2) according to an embodiment of the present invention, to suppress the read failure for 10 years, the voltage (V _d ) applied to the drain can be increased to 1.82V.

An increase in the drain applied voltage V _d eventually leads to an improvement in the operating speed. Therefore, when using the memory device (200 of FIG. 2) according to an embodiment of the present invention, it can be seen that the operating speed faster than the conventional memory device (100 of FIG. 1).

3 to 7 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 3, first, a tunneling insulating layer 310a, a storage node layer 315a, a blocking insulating layer 320a, and a main gate electrode layer 330a are sequentially formed on a semiconductor substrate 305. In more detail, the tunneling insulating layer 310a and the blocking insulating layer 320a may be formed of a silicon oxide film. For example, the tunneling insulating layer 310a may be formed by thermally oxidizing the semiconductor substrate 305.

The storage node layer 315a may be formed of silicon nitride, but may be formed of nano-dots or nano-crystals. The main gate electrode layer 330a may be formed including polysilicon.

Referring to FIG. 4, the main gate electrode layer 330 is then patterned using photolithography and etching techniques to form the main gate electrode 330. When the main gate electrode layer 330a is etched, the blocking insulating layer 320a, the storage node layer 315a, and the tunneling insulating layer 310a outside the main gate electrode 330 are also etched to form the main gate electrode 330. It is preferable to form the blocking insulating layer 320, the storage node 315, and the tunneling insulating layer 310 interposed between the semiconductor substrates 305.

Referring to FIG. 5, the spacer insulating layer 335a and the sidewall gate electrode layer 340a are sequentially formed on the resultant product on which the main gate electrode 330 is formed. In more detail, the spacer insulating layer 335a may be formed to include a silicon oxide film. In addition, the sidewall gate electrode layer 340a may be formed including polysilicon. In this case, the polysilicon may be doped with impurities for conductivity.                     

Referring to FIG. 6, the sidewall gate electrode layer 340a is anisotropically etched to form sidewall gate electrodes 340. That is, all of the sidewall gate electrode layers 340a on the main gate electrode 330 are removed by anisotropic etching, and sidewall gate electrodes 340 are formed on both sidewalls of the main gate electrode 330.

In anisotropic etching, the spacer insulating layer 335 is also etched to form a spacer insulating layer interposed between the main gate electrode 330 and the sidewall gate electrodes 340, and between the sidewall gate electrodes 340 and the semiconductor substrate 305. It is preferable to form 335.

Referring to FIG. 7, the source 350 and the drain 355 are formed in the active region of the semiconductor substrate 305 including the outside of the sidewall gate electrodes 340, respectively. For example, the source 350 and the drain 355 may be formed by injecting n-type impurities and activating through heat treatment. In this case, the sidewall gate electrodes 340 and the main gate electrode 330 may serve as a protective layer to prevent n-type impurities from being injected into the semiconductor substrate 305 below.

Accordingly, even though the drain 355 and the sidewall gate electrode 340 may overlap, the storage node 315 and the drain 355 do not overlap and are not immediately adjacent to each other. Accordingly, in the read operation, a soft program phenomenon in which charge is injected into the storage node 315 directly from the drain 355 or from the semiconductor substrate 305 adjacent to the drain 355 can be suppressed. As a result, the voltage applied to the drain 355 during the read operation may be increased, thereby enabling the fabrication of a memory device having a high operating speed.

Meanwhile, after forming the source 350 and the drain 355, the wiring metal may be formed by a method known to those skilled in the art. In this case, the wiring metal may be formed to electrically connect the main gate electrode 330 and the sidewall gate electrodes 340. Accordingly, the main gate electrode 330 and the sidewall gate electrodes 340 may interlock with each other.

The foregoing description of specific embodiments of the invention has been presented for purposes of illustration and description. The present invention is not limited to the above embodiments, and it is apparent that many modifications and changes can be made in the technical spirit of the present invention by one of ordinary skill in the art in combination. .

According to the nonvolatile memory device 200 according to the present invention, even though the source 250 and the drain 255 may partially overlap the sidewall gate electrode 240, the storage node 215 does not overlap the storage node 215. Are spaced apart.

Therefore, even when a relatively high voltage is applied to the drain 255 during a read operation, a soft program phenomenon in which charge is directly injected into the storage node 215 from the drain 255 or from the semiconductor substrate 205 adjacent to the drain 255 is prevented. Can be effectively suppressed.

Accordingly, the voltage applied to the drain 215 during the read operation can be increased, and an increase in the drain applied voltage leads to an improvement in the operating speed.

Claims (15)

A main gate electrode formed on the active region of the semiconductor substrate; Sidewall gate electrodes formed on both sidewalls of the main gate electrode; A storage node interposed between the main gate electrode and the semiconductor substrate; A first insulating layer interposed between the semiconductor substrate and the storage node; A second insulating film interposed between the main gate electrode and the storage node; A third insulating film interposed between the main gate electrode and the sidewall gate electrodes and between the sidewall gate electrodes and the semiconductor substrate; And And a source and a drain respectively formed in an active region of the semiconductor substrate including outer sidewalls of the sidewall gate electrodes. The nonvolatile memory device of claim 1, wherein the source and the drain include a first portion formed outside the sidewall gate electrodes and a second portion partially overlapping the sidewall gate electrode. The nonvolatile memory device of claim 1, wherein the sidewall gate electrodes are formed of doped polysilicon. The nonvolatile memory device of claim 1, wherein the storage node is formed of a silicon nitride layer. The nonvolatile memory device of claim 1, wherein the storage node is formed of nano-dots or nano-crystals. The nonvolatile memory device of claim 1, wherein the insulating layers are formed of a silicon oxide layer. The nonvolatile memory device of claim 1, further comprising a metal wire electrically connecting the main gate electrode and the sidewall gate electrodes. Forming a first insulating layer on the active region of the semiconductor substrate; Forming a storage node layer on the first insulating layer; Forming a second insulating layer on the storage node layer; Forming a main gate electrode layer on the second insulating layer; Patterning the main gate electrode layer to form a main gate electrode; Forming a third insulating layer on an entire surface of the resultant product on which the main gate electrode is formed; Forming a sidewall gate electrode layer on the third insulating layer; Anisotropically etching the sidewall gate electrode layer to form sidewall gate electrodes on both sidewalls of the main gate electrode; And forming a source and a drain respectively formed in an active region of the semiconductor substrate including outer sides of the sidewall gate electrodes. 10. The method of claim 8, wherein the insulating layers are formed of an oxide film. 10. The method of claim 9, wherein the first insulating layer is formed by thermally oxidizing the semiconductor substrate. 10. The method of claim 8, wherein the storage node layer is formed of a silicon nitride film. The method of claim 8, wherein the storage node layer is formed of nano-dots or nano-crystals. 10. The method of claim 8, wherein the sidewall gate electrode layer is formed of polysilicon. The method of claim 8, further comprising forming a wiring metal connecting the main gate electrode and the sidewall gate electrodes after the source and drain forming step. The method of claim 8, wherein the forming of the main gate electrode is performed by removing the second insulating layer, the storage node layer, and the first insulating layer outside the main gate electrode, thereby forming a gap between the main gate electrode and the semiconductor substrate. Forming a storage node interposed therebetween, and forming a second insulating film and a first insulating film above and below the storage node.

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