KR20060077728A - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

In the present invention, the capacitance of the storage capacitor formed in the thin film transistor array panel is randomly formed for each pixel.

As described above, the capacitance of the storage capacitor formed for each pixel is formed at random to remove the display unevenness so that the deviation between adjacent pixels is not visible. In addition, there is an advantage that the aperture ratio is reduced or the luminance is not reduced while removing the display unevenness.

Random, retention capacitor, stain

Description

Thin film transistor array panel and manufacturing method therefor {THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF}

1 is a layout view of a polysilicon thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along the line II-II′-II.

3A is a layout view at an intermediate stage of the method of manufacturing the thin film transistor array panel shown in FIGS. 1 and 2 according to an embodiment of the present invention.

3B is a cross-sectional view of the thin film transistor array panel of FIG. 3A taken along line IIIb-IIIb'-IIIVb ''.

4A is a layout view of a thin film transistor array panel in the next step of FIG. 3A.

4B is a cross-sectional view of the thin film transistor array panel of FIG. 4A taken along line IVb-IVb′-IVb ″.

FIG. 5 is a cross-sectional view of the thin film transistor array panel of FIG. 4B taken along the line IVb-IVb ′ of FIG. 4A.

6A is a layout view of a thin film transistor array panel in the next step of FIG. 5.

FIG. 6B is a cross-sectional view of the thin film transistor array panel of FIG. 6A taken along the line VIb-VIb′-VIIb ″.

FIG. 7A is a layout view of a thin film transistor array panel in the next step of FIG. 6A.

FIG. 7B is a cross-sectional view of the thin film transistor array panel of FIG. 7A taken along the line VIIb-VIIb′-VIIb ″.

<Description of Signs of Major Parts of Drawings>

110: insulating substrate 121: gate line

124: gate electrode 140: gate insulating film

151: semiconductor 171: data line

173: input electrode 175a, 175b, 175c: output electrode

190: pixel electrode

The present invention relates to a thin film transistor array panel and a method of manufacturing the same.

In general, a thin film transistor (TFT) is used as a switching element for driving each pixel independently in a flat panel display such as a liquid crystal display or an organic light emitting display. The thin film transistor array panel including the thin film transistor includes a scan signal line (or gate line) for transmitting a scan signal to the thin film transistor and a data line for transmitting a data signal, in addition to the thin film transistor and the pixel electrode connected thereto.                         

The thin film transistor includes a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode connected to the pixel electrode, and a semiconductor positioned on the gate electrode between the source electrode and the drain electrode. The data signal from the data line is transferred to the pixel electrode in accordance with the scanning signal of.

The pixel electrode and the drain electrode are electrically connected to each other through a contact hole formed in the protective film. The protective film may be formed of a single layer or a plurality of layers, and may be formed by including an inorganic film therebetween in order to improve the adhesion between the organic film and the lower film.

When a signal is applied to the pixel electrode through this configuration, the storage capacitor is formed to maintain the same voltage even if the signal is not applied until the next frame. Increasing the capacity of the holding capacitor has a disadvantage in that the aperture ratio and the luminance deteriorate.

On the other hand, in order to form the display device, a plurality of masks are aligned and subjected to exposure and patterning. Due to the misalignment of the masks, characteristics of the thin film transistors of each pixel and capacitance of the storage capacitor are different. As a result, unevenness occurs in the display device. Such spots can be removed by sufficiently increasing the capacitance of the storage capacitor, but in this case, the aperture ratio of the display device is low and the luminance is also low.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor array panel and a method of manufacturing the same, which can remove unevenness generated in a display device without affecting aperture ratio and luminance.

In order to solve this problem, the present invention randomly forms the capacitance of the storage capacitor formed in the thin film transistor array panel for each pixel.

Specifically, an insulating substrate, a blocking layer formed on the substrate, a polycrystalline silicon layer formed on the blocking layer, a gate insulating film covering the polycrystalline silicon layer, a gate line formed on the gate insulating film, the gate insulating film A first contact hole and a first contact hole formed over the sustain electrode, the interlayer insulating film covering the gate line and the sustain electrode, and a portion of a source region and a drain region formed on the interlayer insulating layer and doped with the polysilicon layer, respectively; A data line including a second contact hole, an input electrode connected to the source region through the first contact hole, a data line connected to the drain region through the second contact hole, overlapping the sustain electrode, and a width of the pixel Covering the output electrode, the data line, and the output electrode which are randomly formed A thin film transistor array panel including a passivation layer having a third contact hole exposing a part of an output electrode, and a pixel electrode connected to the output electrode through a third contact hole on the passivation layer.

It is preferable that the width of the output electrode is equal to or smaller than the width of the sustain electrode,

Forming a semiconductor including an intrinsic region and an impurity region on a substrate, forming a gate insulating layer on the semiconductor, forming a storage electrode and a gate line overlapping the intrinsic region on the gate insulating layer, the sustain electrode, Forming an interlayer insulating film covering a gate line and a gate insulating film; forming a data line formed on the interlayer insulating film and connected to the impurity region; and forming a data line on the interlayer insulating film so as to be separated from the data line. Forming an output electrode that is connected to and overlaps with the sustain electrode, the width of which is randomly formed; stacking a passivation layer covering the output electrode and the data line; and forming a pixel electrode to be connected to the output electrode on the passivation layer. Thin film transistor comprising forming It is about the manufacturing method of a display panel,

It is preferable that the width of the output electrode is equal to or smaller than the width of the sustain electrode,

An insulating substrate, a blocking layer formed on the substrate, a polycrystalline silicon layer formed on the blocking layer, a gate insulating film covering the polycrystalline silicon layer, a gate line formed on the gate insulating film, and formed on the gate insulating film A first contact hole and a second contact hole formed in the sustain electrode, the interlayer insulating film covering the gate line and the sustain electrode, and exposing a portion of the source region and the drain region formed on the interlayer insulating layer and doped with the polysilicon layer, respectively; A data line including an input electrode connected to the source region through the first contact hole, an output electrode connected to the drain region through the second contact hole and having an extension that overlaps the sustain electrode, and the data A third covering the line and the output electrode and exposing a portion of the output electrode A protective film having a contact hole, and a pixel electrode connected to the output electrode through a third contact hole on the protective film, wherein the storage capacitor is formed to include the storage electrode, the extension of the output electrode, and the pixel electrode. The thin film transistor array panel is randomly formed for each pixel.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a polysilicon thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view of a polysilicon thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along line II-II ′.

A blocking film 111 made of silicon oxide (SiO ₂ ), silicon nitride (SiNx), or the like is formed on the transparent insulating substrate 110. The blocking film 111 may have a multilayer structure.

On the blocking film 111, a plurality of island-like semiconductors 151 made of polycrystalline silicon are formed. The island-like semiconductor 151 is formed to be horizontally long, and both ends thereof may be formed to have an extended width for contacting the upper conductive layer.

Each semiconductor 151 includes an impurity region containing conductive impurities and an intrinsic region containing little conductive impurities, and a heavily doped region having a high impurity concentration in the impurity region. There is a lightly doped region with low concentrations of impurities.

The intrinsic region includes two channel regions 154a and 154b that are spaced apart from each other. The high concentration impurity region includes a plurality of source / drain regions 153, 155, and 157 separated from each other with respect to the channel regions 154a and 154b.

The low concentration impurity regions 152a and 152b located between the source / drain regions 153, 155 and 157 and the channel regions 154a and 154b are called lightly doped drain regions (LDD regions) and have a width. Narrower than other areas                     

Examples of the conductive impurity include P-type impurities such as boron (B) and gallium (Ga) and N-type impurities such as phosphorus (P) and arsenic (As). The lightly doped regions 152a and 152b prevent leakage current or punch through from the thin film transistor, and the lightly doped regions 152a and 152b are free of impurities. ) Can be replaced with an area.

On the semiconductor 151 and the blocking layer 111, a gate insulating layer 140 having a thickness of several hundreds of silicon nitride or silicon oxide is formed.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 extending in the horizontal direction are formed on the gate insulating layer 140.

The gate line 121 transmits a gate signal, and a portion of the semiconductor 151 protrudes upward and includes a plurality of protrusions overlapping the channel regions 154a and 154b of the semiconductor 151. As such, a portion of the gate line 121 overlapping the channel regions 154a and 154b is used as the gate electrodes 124a and 124b of the thin film transistor. The gate electrodes 124a and 124b may also overlap the lightly doped regions 152a and 152b.

One end of the gate line 121 may have a large area for connecting to another layer or an external driving circuit, and a gate driving circuit (not shown) generating a gate signal is integrated on the substrate 110. The gate line 121 may be directly connected to the gate driving circuit.

The storage electrode line 131 is positioned between the two gate lines 121 and is adjacent to a lower side of the two gate lines 121. The storage electrode line 131 includes a storage electrode 133 protruding toward the upper gate line 121 and receives a predetermined voltage such as a common voltage applied to a common electrode (not shown). In the present embodiment, the storage electrode 131 is formed to have the same width, height, and width for each pixel.

The gate line 121 and the storage electrode line 131 may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based metal such as copper (Cu) or copper alloy, Molybdenum-based metals such as molybdenum (Mo) and molybdenum alloy, chromium (Cr), tantalum (Ta), titanium (Ti) and the like. However, the gate line 121 may have a multilayer structure including two conductive layers (not shown) having different physical properties.

One of these conductive films is a low resistivity metal such as an aluminum-based metal, a silver-based metal, or a copper-based metal so as to reduce signal delay or voltage drop of the gate line 121 and the storage electrode line 131. It may be made of a metal. The other conductive layer may be made of a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metal, chromium, tantalum, or titanium. A good example of such a combination is a chromium bottom film and an aluminum top film, and an aluminum bottom film and a molybdenum top film.

Side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110 so that the upper thin film can be smoothly connected.

An interlayer insulating film 160 is formed on the gate line 121, the storage electrode line 131, and the gate insulating layer 140. The interlayer insulating layer 160 is an organic material having excellent planarization characteristics and photosensitivity, a low dielectric constant insulating material such as a-Si: C: O and a-Si: O: F formed by plasma chemical vapor deposition, Or silicon nitride, which is an inorganic material. A plurality of contact holes 163 and 165 exposing the outermost source / drain regions 153 and 155 are formed in the interlayer insulating layer 160 and the gate insulating layer 140, respectively.

A plurality of date lines 171 and a plurality of output electrodes 175a, 175b, and 175c intersecting the gate line 121 are formed on the interlayer insulating layer 160.

Each data line 171 includes an input electrode 173 connected to the source / drain region 153 through the contact hole 163. One end of the data line 171 may have a large area in order to connect to another layer or an external driving circuit, and when data driving circuit (not shown) generating a data signal is integrated on the substrate 110 Line 171 may be directly connected to the data driving circuit.

The output electrodes 175a, 175b, and 175c are separated from the input electrode 173 and are connected to the source / drain region 155 through the contact hole 165. The output electrodes 175a, 175b, and 175c have an extension that overlaps the sustain electrode 133. In the present embodiment, the width of the extension is the same for each pixel, but the width of the extension for each pixel is randomly formed by randomly forming the height of the extension for each pixel. The height of the extension part is formed to be equal to or lower than the height of the storage electrode 133. By randomizing the widths of the output electrodes 175a, 175b, and 175c in this way, the capacitances of the storage capacitors formed for each pixel are formed at random, whereby deviations between adjacent pixels are no longer seen and no spots appear.                     

The data line 171 and the output electrodes 175a, 175b, and 175c are preferably made of a refractory metal such as molybdenum, chromium, tantalum, titanium, or an alloy thereof. However, they may also have a multilayer structure including a conductive film having a low resistance and a conductive film having good contact characteristics, such as the gate line 121. Examples of the multilayer film structure include a triple film of molybdenum film, aluminum film, and molybdenum film in addition to the above-described double film of chromium lower film and aluminum upper film or aluminum lower film and molybdenum upper film.

The side surfaces of the data line 171 and the output electrodes 175a, 175b, and 175c are also inclined with respect to the substrate 110 surface.

Passivation layers 180a and 180b are formed on the data line 171, the output electrodes 175a, 175b, and 175c, and the interlayer insulating layer 160. The passivation layers 180a and 180b may include the first passivation layer 180a and the second passivation layer 180b, the first passivation layer 180a may be formed of an inorganic material such as silicon nitride, and the second passivation layer 18b may be easily planarized. It consists of one organic substance and the like. The passivation layers 180a and 180b include a plurality of contact holes 185 exposing the output electrode 175 and a plurality of contact holes 182 exposing one end of the data line 171.

On the passivation layer 180b, a pixel electrode 190 and a contact auxiliary member 82 made of a transparent conductive material such as IZO (indium zinc oxide) or ITO (indium tin oxide), or an opaque reflective conductive material such as aluminum or silver ) Is formed.                     

The pixel electrode 190 is connected to the output electrode 175 connected to the source / drain region 155 through the contact hole 185 to receive a data voltage from the source / drain region 155 and the output electrode 175.

The contact assisting member 82 complements and protects the adhesion between the end of the data line 171 and the external device. The pixel electrode 190 to which the data voltage is applied generates an electric field together with the common electrode to which the common voltage is applied, thereby determining the direction of the liquid crystal molecules of the liquid crystal layer (not shown) between the two electrodes or the light emitting layer between the two electrodes. Current) to emit light.

Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 to 2 will be described in detail with reference to FIGS. 1 to 2 as well as FIGS. 3A to 7B.

FIG. 3A is a layout view at an intermediate stage of the method of manufacturing the thin film transistor array panel shown in FIGS. 1 and 2 according to an embodiment of the present invention, and FIG. 3B is IIIb-IIIb'-IIIVb 'representing the thin film transistor array panel of FIG. 3A. 4A is a layout view of a thin film transistor array panel in a next step of FIG. 3A, FIG. 4B is a cross-sectional view taken along line IVb-IVb′-IVb '' of the thin film transistor array panel of FIG. 4A, FIG. 5 is a cross-sectional view of the thin film transistor array panel of the next step of FIG. 4B, taken along line IVb-IVb ′ of the thin film transistor array panel of FIG. 4A, and FIG. 6A is a layout view of the thin film transistor array panel of the next step of FIG. 5. 6B is a cross-sectional view of the thin film transistor array panel of FIG. 6A taken along the line VIb-VIb′-VIIb ″, FIG. 7A is a layout view of the thin film transistor array panel in the next step of FIG. 6A, and FIG. 7B is a view of FIG. foil A sectional view taken along the transistor panel VIIb'-VIIb-VIIb '' line.

First, as shown in FIGS. 3A and 3B, the blocking film 111 is formed on the transparent insulating substrate 110, and then, as amorphous silicon by chemical vapor deposition (CVD), sputtering, or the like. The semiconductor film 150 thus formed is formed.

Next, the semiconductor film 150 is crystallized by laser annealing, furnace annealing, or sequential lateral solidification (SLS).

The semiconductor film 150 is patterned to form a plurality of island-like semiconductors 151, and a gate insulating layer 140 is formed thereon by a chemical vapor deposition method.

As shown in FIGS. 4A and 4B, a metal film is stacked on the gate insulating layer 140 by sputtering and a photoresist pattern PR is formed. The metal film is etched using the photoresist pattern PR to form a plurality of gate lines 121 including the gate electrode 124 and a plurality of storage electrode lines 131 including the storage electrode 137.

At this time, the etching time is sufficiently long so that the boundary line between the gate line 121 and the storage electrode line 131 is positioned inside the photoresist pattern PR.

Subsequently, N-type or P-type impurity ions are implanted at high concentration into the island-type semiconductor 151 using the photoresist pattern PR as an ion implantation mask to form source / drain regions 153, 155, and 157, which are high concentration impurity regions.

Next, as shown in FIG. 5, after removing the photoresist pattern PR, the island-type semiconductor 151 is doped with low concentration of N-type or P-type impurity ions using the gate line 121 and the storage electrode line 131 with an ion implantation mask. Thus, a plurality of low concentration impurity regions 152a and 152b are formed. In this way, the region under the gate electrode 124 positioned between the source region 153 and the drain region 155 becomes the channel region 154.

The low concentration impurity regions 152a and 152b may be formed by using metal films having different etching ratios in addition to the photoresist pattern described above, or by forming spacers on sidewalls of the gate line 121 and the storage electrode line 131. have.

6A and 6B, the plurality of contact holes 163 and 165 exposing the source region and the drain region 153 and 155 by stacking the photo interlayer insulating layer 160 on the entire surface of the substrate 110 and etching the photo, respectively. To form.

Next, a plurality of data lines 171 and a plurality of output electrodes having an input electrode 173 connected to the source region 153 and the drain region 155, respectively, through the contact holes 163 and 165 on the interlayer insulating layer 160. 175 is formed.

As shown in FIGS. 7A and 7B, an inorganic material such as silicon nitride (SiNx) is stacked on the entire surface of the substrate 110 to form a first passivation layer 180a, and a second passivation layer is formed by stacking an organic material having photosensitivity. To form 180b.

Thereafter, a plurality of pixel electrodes 190 connected to the output electrode 175 are formed on the passivation layer 180 through a contact hole 185 using a transparent conductive material such as IZO or ITO.

In the present embodiment, an embodiment in which the protective film is formed in a double layer is shown, but it is also possible to form a protective film formed in a single layer.                     

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, the capacitance of the storage capacitor formed for each pixel is formed at random to remove the display unevenness so that the deviation between adjacent pixels is not visible. In addition, there is an advantage that the aperture ratio is reduced or the luminance is not reduced while removing the display unevenness.

Claims (5)

Insulation board, A blocking layer formed on the substrate, A polycrystalline silicon layer formed on the blocking layer, A gate insulating film covering the polycrystalline silicon layer, A gate line formed on the gate insulating film, A storage electrode formed on the gate insulating film, An interlayer insulating film covering the gate line and the sustain electrode; A first contact hole and a second contact hole formed in the interlayer insulating film and exposing portions of the source region and the drain region formed by being doped with the polycrystalline silicon layer, respectively; A data line including an input electrode connected to the source region through the first contact hole; An output electrode connected to the drain region through the second contact hole, overlapping with the sustain electrode, and having an area that is randomly formed for each pixel; A passivation layer covering the data line and the output electrode and having a third contact hole exposing a portion of the output electrode; And a pixel electrode connected to the output electrode through a third contact hole on the passivation layer. In claim 1, And the width of the output electrode is equal to or smaller than the width of the sustain electrode. Forming a semiconductor including an intrinsic region and an impurity region on the substrate, Forming a gate insulating film on the semiconductor, Forming a gate line overlapping the sustain electrode and the intrinsic region on the gate insulating layer; Forming an interlayer insulating film covering the sustain electrode, the gate line, and the gate insulating film; Forming a data line on the interlayer insulating layer and connected to the impurity region; Forming an output electrode formed on the interlayer insulating layer so as to be separated from the data line, connected to the impurity region, overlapping with the sustain electrode, and having a random width; Stacking a passivation layer covering the output electrode and the data line; And forming a pixel electrode on the passivation layer so as to be connected to the output electrode. In claim 3, And the width of the output electrode is equal to or smaller than the width of the sustain electrode. Insulation board, A blocking layer formed on the substrate, A polycrystalline silicon layer formed on the blocking layer, A gate insulating film covering the polycrystalline silicon layer, A gate line formed on the gate insulating film, A storage electrode formed on the gate insulating film, An interlayer insulating film covering the gate line and the sustain electrode; A first contact hole and a second contact hole formed in the interlayer insulating film and exposing portions of the source region and the drain region formed by being doped with the polycrystalline silicon layer, respectively; A data line including an input electrode connected to the source region through the first contact hole; An output electrode connected to the drain region through the second contact hole and having an extension part overlapping the sustain electrode; A passivation layer covering the data line and the output electrode and having a third contact hole exposing a portion of the output electrode; A pixel electrode connected to the output electrode through a third contact hole on the passivation layer, And a capacitance of the storage capacitor formed by the storage electrode, the extension of the output electrode, and the pixel electrode is randomly formed for each pixel.

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