KR20060075586A - Liquid crystal display device and method of fabricating thereof - Google Patents

Abstract

The liquid crystal display of the present invention and a method for manufacturing the same are formed by simultaneously forming an amorphous silicon thin film transistor for pixels and a polycrystalline silicon thin film transistor for a driving circuit in one panel within a range that does not deform the conventional amorphous silicon thin film transistor manufacturing process. A method for embedding a driving circuit into a panel and simplifying a manufacturing process, the method comprising: providing a substrate divided into a pixel portion and a driving circuit portion; Forming a source / drain electrode on the driving circuit portion of the substrate, and forming a gate electrode and a gate line on the pixel portion; Forming a first insulating film on the substrate; Forming an active pattern on the driving circuit portion and the pixel portion of the substrate, and forming an gate insulating layer on the active pattern on the driving circuit portion and an etch stopper on the active pattern on the pixel portion; Forming a gate electrode on the gate insulating layer of the driving circuit unit, and forming a source / drain electrode on the active pattern of the pixel unit; Implanting a high concentration of impurity ions into the driving circuit to form a source / drain region in a predetermined region of the active pattern of the driving circuit; Forming a second insulating film on the entire surface of the substrate; And forming a pixel electrode in the pixel portion of the substrate, and forming a first connection electrode connecting the source region and the source electrode to a driving circuit portion and a second connection electrode connecting the drain region and the drain electrode. .

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THEREOF}

1 is an exploded perspective view schematically illustrating a structure of a general liquid crystal display device.

2A is a cross-sectional view illustrating an amorphous silicon thin film transistor having a general staggered structure.

2B is a cross-sectional view illustrating a polycrystalline silicon thin film transistor having a general coplanar structure.

3 is a plan view schematically showing the structure of a liquid crystal display device incorporating a drive circuit according to the present invention;

4 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a first exemplary embodiment of the present invention.

5A to 5G are plan views sequentially illustrating a manufacturing process along lines IVa-IVa 'and IVb-IVb' of the array substrate illustrated in FIG. 4.

6A to 6G are cross-sectional views sequentially showing manufacturing processes taken along lines IVa-IVa 'and IVb-IVb' of the array substrate shown in FIG.

7 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a second exemplary embodiment of the present invention.

8A to 8H are plan views sequentially illustrating manufacturing processes along lines VIIa-VIIa 'and VIIb-VIIb' of the array substrate shown in FIG.

9A to 9F are cross-sectional views sequentially showing manufacturing processes taken along lines VIIa-VIIa 'and VIIb-VIIb' of the array substrate shown in FIG.

10A to 10D are cross-sectional views specifically illustrating a second mask process of forming an active pattern, an etch stopper of a pixel portion, and a gate insulating film of a driving circuit portion using diffraction exposure in FIG. 9B.

** Explanation of symbols for main parts of drawings **

116,216 Gate line 117,217 Data line

118,218: pixel electrode 121,121D, 221,221D, 221'D: gate electrode

122,122D, 222,222D: Source electrode

123,123D, 223,223D: Drain electrode

124,124D, 224,224D: Active pattern

160A, 260A: Gate insulating film for driving circuit

160B, 260B: Etch Stopper 180A ~ 180I, 280A ~ 280J: Contact Hole

190A ~ 190C, 290A ~ 290C: Connecting electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a manufacturing method thereof, and more particularly, to a driving circuit-integrated liquid crystal display device in which an amorphous silicon thin film transistor of a pixel portion and a polycrystalline silicon thin film transistor of a driving circuit portion are simultaneously formed through the same manufacturing process. It relates to a manufacturing method.

In today's information society, display is more important as a visual information transmission medium, and in order to gain a major position in the future, it is necessary to satisfy requirements such as low power consumption, thinness, light weight, and high definition. Liquid Crystal Display (LCD), the flagship product of Flat Panel Display (FPD), has not only the ability to satisfy these conditions of the display but also mass production. It has been established as a core parts industry that can gradually replace the existing cathode ray tube (CRT).

BACKGROUND ART In general, a liquid crystal display device is a display device in which data signals according to image information are individually supplied to pixels arranged in a matrix form so that a desired image can be displayed by adjusting light transmittance of the pixels.

To this end, the liquid crystal display is largely composed of a color filter substrate as a first substrate, an array substrate as a second substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate. .

In this case, a thin film transistor (TFT) is generally used as a switching element of the liquid crystal display, and an amorphous silicon thin film or a polycrystalline silicon thin film is used as a channel layer of the thin film transistor. use.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (ie, photolithography process) for fabricating an array substrate including a thin film transistor, a method of reducing the number of mask processes in terms of productivity is required. It is required.

Hereinafter, a structure of a general liquid crystal display device will be described in detail with reference to FIG. 1.

FIG. 1 is an exploded perspective view schematically illustrating a structure of a general liquid crystal display device. As described above, the liquid crystal display device is largely divided into a color filter substrate 5 and an array substrate 10, and the color filter substrate 5 and an array substrate ( It consists of a liquid crystal layer 40 formed between 10).

At this time, the color filter substrate 5 and the color filter (C) divided into a sub-color filter (7) for implementing the colors of Red (R), Green (G), Blue (B); A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 40, and a transparent common electrode 8 that applies a voltage to the liquid crystal layer 40. )

In the array substrate 10, gate lines 16 and data lines 17 are formed on the substrate 10 to be vertically and horizontally defined to define the pixel region P. In this case, a thin film transistor T, which is a switching element, is formed in an intersection region of the gate line 16 and the data line 17, and a pixel electrode 18 is formed in each pixel region P.

The pixel region P is a sub pixel corresponding to one sub color filter 7 of the color filter substrate 5. The color image is a sub-color filter 7 of the red, green, and blue colors. It is obtained by combining. That is, three subpixels of red, green, and blue are gathered to form one pixel, and the thin film transistor T is connected to the red and green subpixels, respectively.

Although not shown in detail, the thin film transistor T includes a gate electrode connected to the gate line 16, a source electrode and a drain electrode connected to the data line 17. In addition, the thin film transistor T forms a conductive channel between the source electrode and the drain electrode by an insulating film for insulating the gate electrode and the source / drain electrode and a gate voltage supplied to the gate electrode. Layer.

The channel layer is formed of an amorphous silicon thin film or a polycrystalline silicon thin film as described above, and the polycrystalline silicon thin film transistor using the polycrystalline silicon thin film has a structure different from that of the amorphous silicon thin film transistor, so that the polycrystalline silicon thin film transistor and the amorphous silicon thin film Thin film transistors are generally manufactured through different manufacturing processes.

In general, thin film transistors are classified into a staggered structure and a coplanar structure according to the formation positions of the electrodes.

2A and 2B are cross-sectional views illustrating an amorphous silicon thin film transistor having a general staggered structure and a polycrystalline silicon thin film transistor having a general coplanar structure, respectively.

Referring to the drawings, the staggered structure is a structure in which the gate electrode 21 'and the source / drain electrodes 22' and 23 'are disposed on top and bottom of the insulating film 15, respectively. The coplanar structure is a structure in which the gate electrode 21 "and the source / drain electrodes 22" and 23 "are both disposed on or below the insulating film 15. Semiconductor) and polycrystalline silicon thin film transistors.

For reference, reference numerals 24 'and 24 "denote channel layers of the thin film transistors, respectively, and represent an amorphous silicon active pattern and a polycrystalline silicon active pattern, respectively, reference numeral 10 denotes an array substrate, and reference numeral 25 denotes an ohmic contact layer. Indicates.

Since the two structures are independent of each other, it is difficult to implement the two structures in the same panel due to problems such as design, mask, manufacturing process, etc. in the current technology level.

On the other hand, in order to fabricate a driving circuit-integrated liquid crystal display device in which a driving circuit portion and a pixel portion are incorporated in a glass substrate, a polycrystalline silicon thin film transistor suitable for high speed operation of 1 MHz or more and relatively high mobility must be applied to the driving circuit portion.

Therefore, the general liquid crystal display device having an integrated driving circuit includes both a thin film transistor for driving a pixel and a thin film transistor for a driving circuit for driving a pixel driving thin film transistor and applying a signal to a gate line and a data line. The polycrystalline silicon thin film transistor using the polycrystalline silicon thin film, the polycrystalline silicon thin film transistor using the polycrystalline silicon thin film needs an additional heat treatment process to form the polycrystalline silicon thin film, and must be manufactured using a different manufacturing process than the amorphous silicon thin film transistor. There was a problem.

That is, the polycrystalline silicon thin film is formed by performing annealing on the amorphous silicon thin film after forming an amorphous silicon thin film, and the heat treatment process has a problem that requires expensive equipment such as laser equipment and a long process time. . In addition, since the polycrystalline silicon thin film transistor has a coplanar structure different from that of the amorphous silicon thin film transistor, there is a disadvantage in that an existing manufacturing line used for manufacturing the amorphous silicon thin film transistor cannot be used.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a liquid crystal display and a method of manufacturing the same, in which a single amorphous silicon thin film transistor for pixels and a polycrystalline silicon thin film transistor for a driving circuit are simultaneously formed in one panel.

In addition, another object of the present invention is to form an amorphous silicon thin film transistor for a pixel and a polycrystalline silicon thin film transistor for a driving circuit at the same time without changing the conventional amorphous silicon thin film transistor manufacturing process, thereby embedding the driver driving circuit in the panel. In addition, to provide a liquid crystal display device and a method of manufacturing the same that can simplify the manufacturing process.

Further objects and features of the present invention will be described in the configuration and claims of the invention to be described later.

In order to achieve the above object, the manufacturing method of the liquid crystal display device of the present invention comprises the steps of providing a substrate divided into a pixel portion and a driving circuit portion, forming a source / drain electrode in the driving circuit portion of the substrate, the gate portion Forming an electrode and a gate line, forming a first insulating film on the substrate, forming an active pattern on the driving circuit portion and the pixel portion of the substrate, forming a gate insulating film on the active pattern of the driving circuit portion, Forming an etch stopper on the active pattern of the pixel portion, forming a gate electrode on the gate insulating layer of the driving circuit portion, and forming an ohmic contact layer and a source / drain electrode on the active pattern of the pixel portion, A source / drain region is implanted into a predetermined region of an active pattern of the driving circuit portion by implanting high concentration impurity ions into the driving circuit portion. Forming a second insulating film on the entire surface of the substrate; forming a pixel electrode in a pixel portion of the substrate; and a first connection electrode and a drain region and a drain connecting the source region and the source electrode to a driving circuit portion. Forming a second connection electrode connecting the electrodes.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, comprising: providing a substrate divided into a pixel portion and a driving circuit portion, forming a source / drain electrode on the driving circuit portion of the substrate, and forming a gate electrode and a gate line on the pixel portion; Forming an active pattern on the driving circuit portion and the pixel portion of the substrate by using diffraction exposure; forming a first insulating layer on the substrate, and forming a gate insulating layer and the pixel portion on the active pattern of the driving circuit portion. Forming an etch stopper on the active pattern, forming a gate electrode (a first gate electrode and a second gate electrode) on the gate insulating layer of the driving circuit portion, and forming an ohmic contact layer and a source / Forming a drain electrode, and implanting a high concentration of impurity ions into the driving circuit to form a predetermined region of an active pattern of the driving circuit; Forming a source / drain region, forming a second insulating film on the entire surface of the substrate, forming a pixel electrode in the pixel portion of the substrate, and connecting the source region and the source electrode to a driving circuit portion; And forming a second connection electrode connecting the drain region and the drain electrode.

In another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, the method comprising: providing a substrate divided into a pixel portion and a driving circuit portion, forming a source / drain electrode on the driving circuit portion of the substrate, and a gate electrode and a gate line on the pixel portion; Forming a first insulating film on the substrate; forming an active pattern on the driving circuit portion and the pixel portion of the substrate; and etching the gate insulating layer on the active pattern on the driving circuit portion and the active pattern on the pixel portion. Forming a stopper; forming a gate electrode on the gate insulating layer of the driving circuit unit; and forming a source / drain electrode on the active pattern of the pixel unit; implanting high concentration impurity ions into the driving circuit unit; Forming a source / drain region in a predetermined region of the active pattern; Forming a pixel electrode in the pixel portion of the substrate, and forming a first connection electrode connecting the source region and the source electrode to a driving circuit portion and a second connection electrode connecting the drain region and the drain electrode to a driving circuit portion. It includes.

In addition, the liquid crystal display of the present invention includes a substrate divided into a pixel portion and a driving circuit portion, an amorphous silicon thin film transistor formed on a pixel portion of the substrate, the gate electrode and an active pattern and a source / drain electrode, and a driving circuit portion of the substrate. And a polycrystalline silicon thin film transistor including a source / drain electrode, an active pattern, and a gate electrode formed on the same layer corresponding to each of the gate electrode, the active pattern, and the source / drain electrode of the pixel portion.

Hereinafter, exemplary embodiments of a liquid crystal display and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

Fig. 3 is a plan view schematically showing the structure of the liquid crystal display device of the present invention, showing a drive circuit-integrated liquid crystal display device in which a drive circuit portion is integrated on an array substrate.

As shown in the drawing, the driving circuit-integrated liquid crystal display device 100 is largely composed of an array substrate 110 and a color filter substrate 105 and a liquid crystal layer formed between the array substrate 110 and the color filter substrate 105. Not shown).

The array substrate 110 includes a pixel portion 135, which is an image display area in which unit pixels are arranged in a matrix form, a gate driving circuit portion 132 and a data driving circuit portion 131 disposed outside the pixel portion 135. The driving circuit unit 130 is formed.

In this case, although not shown in the drawing, the pixel units 135 of the array substrate 110 are arranged horizontally and horizontally on the substrate 110 to define a plurality of gate lines and data lines, and the gate lines and data. A thin film transistor, which is a switching element formed in an intersection region of a line, and a pixel electrode formed in the pixel region.

The pixel thin film transistor is a switching element that applies and cuts off a signal voltage to a pixel electrode and is a type of field effect transistor (FET) that controls the flow of current by an electric field.

The driving circuit unit 130 of the array substrate 110 is positioned outside the pixel unit 135 protruding from the color filter substrate 105, and the data driving circuit unit is formed at one long side of the array substrate 110. 131 is positioned, and the gate driving circuit unit 132 is positioned at one end of the array substrate 110.

In this case, the data driving circuit unit 131 and the gate driving circuit unit 132 use a thin film transistor having a CMOS structure as an inverter to properly output the input signal.

For reference, the CMOS is an integrated circuit having a MOS structure which is used for a thin film transistor of a driving circuit unit requiring high speed signal processing, and requires a transistor of a P channel and an N channel, and the characteristics of speed and density are intermediate between NMOS and PMOS. It shows form.

The gate driving circuit unit 132 and the data driving circuit unit 132 are devices for supplying scan signals and data signals to pixel electrodes through gate lines and data lines, respectively, and are connected to an external signal input terminal (not shown). It controls the external signal input through the external signal input terminal to output to the pixel electrode.

In addition, although not shown in the drawing, an image display area 135 of the color filter substrate 105 includes a color filter for implementing color and a common electrode which is an opposite electrode of a pixel electrode formed on the array substrate 110. .

The array substrate 110 and the color filter substrate 105 configured as described above are provided with a cell gap so as to be uniformly spaced apart by a spacer (not shown), and formed on the outer side of the image display area 135. They are bonded by a seal pattern (not shown) to form a unit liquid crystal display panel.

In the meantime, the thin film transistor includes a driving circuit unit including each unit pixel of the pixel unit 135 of the array substrate 110, that is, an intersection region of a gate line and a data line, and a data driving circuit unit 131 and a gate driving circuit unit 132. In the present invention, an amorphous silicon thin film transistor is formed in the pixel unit 135 and a polycrystalline silicon thin film transistor is formed in the driving circuit unit 130.

In this case, the polycrystalline silicon thin film transistor is formed at the same time as the amorphous silicon thin film transistor through the manufacturing process within a range that does not deform the amorphous silicon thin film transistor manufacturing process, will be described in detail with reference to the drawings.

4 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a first exemplary embodiment of the present invention. In particular, FIG. 4 illustrates a driving circuit portion and a pixel portion including a thin film transistor.

In this case, a polycrystalline silicon thin film transistor using a polycrystalline silicon thin film as a channel layer is formed in the driving circuit part on the left side of the drawing, and an amorphous silicon thin film transistor using an amorphous silicon thin film as a channel layer is formed in the pixel part on the right side of the drawing. It is shown.

As shown in the drawing, a driving circuit part thin film transistor including a gate electrode 121D, source / drain electrodes 122D and 123D, and an active pattern (not shown) is formed on an array substrate of the driving circuit part. The first circuit line 116D and the second circuit line 117D electrically connected to the gate electrode 121D and the source / drain electrodes 122D and 123D of the thin film transistor to apply a signal are disposed.

In this case, the source electrode 122D connected to the second circuit line 116D is electrically connected to the source region of the active pattern through the first connection electrode 190A, and the drain electrode 123D is connected to the second connection. The electrode 190B is electrically connected to the drain region of the active pattern. In addition, the gate electrode 121D connected to the first circuit line 116D is electrically connected to the third connection electrode 190C to transmit a signal to another circuit element.

In addition, a gate line 116 and a data line 117 are formed on the array substrate of the pixel portion to be arranged in a vertical direction to define a pixel region. In addition, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 116 and the data line 117, and is connected to the pixel part thin film transistor in the pixel area so as to have a common color filter substrate (not shown). A pixel electrode 118 for driving a liquid crystal (not shown) is formed together with the electrode.

At this time, in the actual pixel unit array substrate, N gate lines and M data lines cross each other, and there are N × M pixels. However, for convenience of description, a portion of the pixel area adjacent to one pixel area is shown in the drawing.

The pixel portion thin film transistor includes a gate electrode (not shown) connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 connected to the pixel electrode 118. In addition, the pixel portion thin film transistor includes an insulating film (not shown) for insulating the gate electrode and the source / drain electrodes 122 and 123, and a source electrode 122 and a drain electrode 123 by a gate voltage supplied to the gate electrode. It includes an active pattern (not shown) to form a conductive channel between the ().

In this case, a part of the source electrode 122 is connected to the data line 117, and a part of the drain electrode 123 is connected to the pixel electrode 118 through the first contact hole 180A.

In addition, a portion of the front gate line 116 extends to the corresponding pixel region to form a storage first electrode (not shown), thereby forming a storage capacitor with the pixel electrode 118 of the pixel region. That is, the pixel electrode 118 overlapping the gate line 116 is electrically connected to the lower storage second electrode 140B through the second contact hole 180B, so that the storage first electrode and the storage second electrode are electrically connected to each other. A storage capacitor is formed between the electrodes 140B.

The pixel portion thin film transistor includes an amorphous silicon thin film transistor using an amorphous silicon thin film as an active pattern, and the driving circuit thin film transistor includes a polycrystalline silicon thin film transistor using a polycrystalline silicon thin film as an active pattern. In addition, the amorphous silicon thin film transistor of the pixel portion is formed in a staggered structure, and the polycrystalline silicon thin film transistor of the driving circuit portion is formed in a coplanar structure. Fabrication of the amorphous silicon thin film transistor of the pixel portion by forming a source / drain electrode in the driving circuit portion and forming a gate insulating film in the driving circuit portion using the etch stopper insulating material when forming the etch stopper of the pixel portion. It becomes possible to manufacture within the range which does not deform a process.

For reference, reference numerals 180C to 180G denote third to seventh contact holes of the driving circuit unit.

Hereinafter, a manufacturing process of the liquid crystal display device configured as described above will be described in detail with reference to the accompanying drawings.

5A through 5G are plan views sequentially illustrating a manufacturing process along lines IVa-IVa 'and IVb-IVb' of the array substrate illustrated in FIG. 4, and FIGS. 6A through 6G are IVa of the array substrate illustrated in FIG. 4. Sectional drawing which shows the manufacturing process along lines -IVa 'and IVb-IVb' sequentially.

6A to 6G sequentially illustrate a manufacturing process of the array substrate of the driving circuit unit, the pixel unit, and the pad unit in order from the left side.

As shown in FIGS. 5A and 6A, the first circuit line 117D and the source / drain electrodes are formed on the driving circuit part by using a photolithography process (first mask process) on a substrate 110 made of a transparent insulating material such as glass. The gate line 116, the gate electrode 121, and the storage first electrode 140A are formed in the pixel portion, and the gate pad 150 is formed in the pad portion.

In this case, the source electrode 122D of the driving circuit part extends from a portion of the first circuit line 117D, and the gate electrode 121 and the storage first electrode 140A of the pixel part are formed on the gate line 116. It extends from a part of) and is formed.

In addition, the first circuit line 117D and the source / drain electrodes 122D and 123D of the driving circuit unit, the gate line 116 and the gate electrode 121 of the pixel unit, and the storage first electrode 140A and the gate pad of the pad unit. 150 is formed through the first mask process using the same conductive material. That is, in order to form a staggered amorphous silicon thin film transistor in the pixel portion and to form a coplanar polycrystalline silicon thin film transistor in the driving circuit portion, the gate line 116 and the gate electrode 121 are formed in the pixel portion. The source / drain electrodes 122D and 123D are formed in the driving circuit part by using the gate metal in the process of forming the gate electrode.

The first circuit line 117D and the source / drain electrodes 122D and 123D of the driving circuit portion, the gate line 116 and the gate electrode 121 of the pixel portion, the storage first electrode 140A, and the gate pad 150 of the pad portion. ) Is a low resistance conductive material such as aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), etc. Can be formed.

Thereafter, as illustrated in FIGS. 5B and 6B, the first insulating layer 115A is formed on the entire surface of the substrate 110. The first insulating film 115A serves as a gate insulating film in the thin film transistor of the pixel portion, and the driving circuit portion serves as a buffer layer for the crystallization process to be described later.

After the amorphous silicon thin film is formed on the entire surface of the first insulating film 115A, patterning is performed using a photolithography process (second mask process) to form active patterns 124 and 124D in the pixel portion and the driving circuit portion, respectively. .

In this case, the amorphous silicon thin film in the active pattern 124D region of the driving circuit part is crystallized into a polycrystalline silicon thin film by performing a crystallization process before or after the second mask process. Crystallization of the amorphous silicon thin film of the driving circuit unit may use various crystallization methods, and in the case of using a laser annealing method using a laser, an excimer laser annealing (ELA) method using a pulse type laser is used. Although mainly used, in recent years, a sequential lateral solidification (SLS) method may be used in which grains are grown in a horizontal direction to dramatically improve crystallization characteristics.

The sequential horizontal crystallization takes advantage of the fact that grain grows in a direction perpendicular to the interface at the interface between the liquid phase silicon and the solid phase silicon, and appropriately controls the size of the laser energy and the irradiation range of the laser beam. It is a crystallization method that can improve the size of the silicon grain by controlling the side growth of the grain by a predetermined length.

Next, as shown in FIGS. 5C and 6C, an insulating material such as silicon oxide film (SiO ₂ ) is deposited on the entire surface of the substrate 110, and then the photolithography process (third mask process) is used. By selectively patterning an insulating material, a gate insulating layer 160A is formed in the driving circuit portion, and an etch stopper 160B is formed in the pixel portion. That is, according to the present invention, an amorphous silicon thin film transistor is formed in the pixel portion using the amorphous silicon thin film transistor manufacturing process within a range not to deform the manufacturing process of the amorphous silicon thin film transistor, and a polycrystalline silicon thin film transistor is formed in the driving circuit portion. In order to form the gate insulating layer 160A in the driving circuit portion through the third mask process, the insulating material is used as the etch stopper 160B of the pixel portion.

Next, as shown in FIGS. 5D and 6D, an n + amorphous silicon thin film and a conductive film are sequentially formed on the entire surface of the substrate 110, and then the conductive film and the conductive film are formed using a photolithography process (fourth mask process). By selectively patterning an n + amorphous silicon thin film, a gate electrode 121D is formed on the gate insulating layer 160A of the driving circuit portion, and an ohmic contact layer 125 and source / drain electrodes 122 and 123 and storage are formed on the pixel portion. The second electrode 140B is formed, and the data pad 155 is formed in the pad portion.

In this case, a second circuit line 116D connected to the gate electrode 121D is formed in the driving circuit unit, and a data line 117 connected to the source electrode 122 is formed in the pixel unit.

In addition, n + amorphous silicon thin films 125D and 125P remain in the driving circuit and the pad part in the same shape as the driving circuit gate electrode 121D and the data pad 155, and the n + amorphous silicon thin film in the pixel part An ohmic contact layer 125 is formed to form an ohmic contact between a predetermined region of the active pattern 124 of the pixel portion and a source / drain electrode to be described later. At this time, an etch stopper 160B is formed on the active pattern 124 of the pixel portion, so that the n + amorphous silicon thin film is removed only up to the surface of the etch stopper 160B.

In addition, the storage second electrode 140B of the pixel portion overlaps with the storage first electrode 140A under the pixel portion to form a storage capacitor with the first insulating layer 115A interposed therebetween.

5E and 6E, the pixel portion and the pad portion are covered using a blocking plate 170 that can block a part of light, such as a shadow mask, and then high concentration impurity ions only in the driving circuit portion. Doping to form a source region 124DS and a drain region 124DD in a predetermined region of the active pattern 124D.

In this case, the gate electrode 121D of the driving circuit part serves as an ion stopper to prevent the dopant from penetrating into the channel region 124DC of the active pattern 124D.

The electrical characteristics of the active pattern 124D are changed according to the type of dopant to be implanted. If the dopant to be implanted corresponds to a Group 3 element such as boron (B), a P-type thin film transistor is a group 5 such as phosphorus (P). If the element corresponds to an N-type thin film transistor to operate.

In this embodiment, the n-type thin film transistor is configured by doping n + impurity ions to the driving circuit, for example, but the present invention is not limited thereto. In the case of forming an N-type thin film transistor in the driving circuit portion as in the present embodiment, the impurity ions are partially patterned by narrowing the gate electrode 121D of the driving circuit portion to be smaller than the lower gate insulating film 160A. An LED region 124DL is formed between the source / drain regions 124DS and 124DD and the channel region 124DC by passing through the gate insulating layer 160A corresponding to the width to be injected into the active pattern 124D. It can be done.

Next, as shown in FIGS. 5F and 6F, after forming the second insulating film 115B on the entire surface of the substrate 110, the second insulating film of the pixel portion using the photolithography process (fifth mask process) is performed. The first contact hole 180A exposing a part of the drain electrode 123 and the second contact hole 180B exposing a part of the storage second electrode 140B are formed by removing a portion of the 115B. A part of the third contact hole 180C exposing a part of the driving circuit part gate electrode 121D by exposing a part of the second insulating layer 115B of the driving circuit part and a part of the source / drain regions 124DS and 124DD of the active pattern is removed. Source / drain electrodes 122D and 123D of the driving circuit portion are formed by forming the fourth contact hole 180D and the fifth contact hole 180E to expose and removing a portion of the second insulating film 115b and the first insulating film 115A. The sixth contact hole 180F and the seventh contact hole 180G exposing a part of the .

In addition, an eighth contact hole 180H exposing a part of the gate pad 150 is formed by removing a portion of the second insulating film 115B and the first insulating film 115A of the pad part and forming a portion of the second insulating film 115B. The ninth contact hole 180I exposing a part of the data pad 155 is formed by removing the partial region.

In this case, the fourth contact hole 180D and the sixth contact hole 180F of the driving circuit unit are formed to electrically connect the source region 124DS and the source electrode 122D of the driving circuit unit. The fifth contact hole 180E and the seventh contact hole 180G are formed to electrically connect the drain region 124DD and the drain electrode 123D of the driving circuit unit. That is, the source / drain electrodes 122D and 123D formed at the lowermost layer to form the polycrystalline silicon thin film transistor of the driving circuit portion through the same manufacturing process as the amorphous silicon thin film transistor of the pixel portion are formed in the fourth contact holes 180D to 7th. The contact hole 180G may be electrically connected to the source / drain regions 124DS and 124DD by using a connection electrode to be described later.

5G and 6G, a transparent conductive material is deposited on the entire surface of the substrate 110, and then selectively patterned by using a photolithography process (sixth mask process). The pixel electrode 118 is connected to the drain electrode 123 through the first contact hole 180A and is connected to the storage second electrode 140B through the second contact hole 180B. The fifth contact hole is formed through the fourth contact hole 180D and the sixth contact hole 180F to form a first connection electrode 190A electrically connecting the source region 124DS of the driving circuit unit to the source electrode 122D. A second connection electrode 190B electrically connecting the drain region 124DD and the drain electrode 123D of the driving circuit unit is formed through the 180E and the seventh contact hole 180G.

In addition, a third connection electrode 190C is electrically connected to the gate electrode 121D of the driving circuit unit through the third contact hole 180C and exposed to the outside. The gate pad electrode 151 and the data pad electrode 156 electrically connected to the gate pad 150 and the data pad 155 to be exposed to the outside through the eighth contact hole 180H and the ninth contact hole 180I, respectively. To form.

In this case, the transparent conductive material may be a transparent conductive material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO).

As described above, the driving circuit integrated liquid crystal display device of the present embodiment simultaneously forms polycrystalline silicon thin film transistors in the driving circuit portion within the range of not deforming the manufacturing process of the amorphous silicon thin film transistor in the pixel portion, thereby eliminating the additional manufacturing process. Built-in is possible.

In addition, unlike the general liquid crystal display of the integrated driving circuit, since the pixel portion may be formed of an amorphous silicon thin film transistor using an amorphous silicon thin film, laser irradiation is required only for the driving circuit portion requiring the crystallization process, which is more productive than laser crystallization on the entire surface of the substrate. There is an excellent advantage.

The first embodiment is an example in which amorphous silicon thin film transistors and polycrystalline silicon thin film transistors are formed in the pixel portion and the driving circuit portion through a total of six mask processes, but the present invention is not limited thereto. By simultaneously forming the active pattern, the gate insulating layer of the driving circuit portion, and the etch stopper of the pixel portion, one mask process can be reduced, which will be described in detail with reference to the following second embodiment.

7 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a second exemplary embodiment of the present invention.

In this case, a polycrystalline silicon thin film transistor using a polycrystalline silicon thin film as a channel layer is formed in the driving circuit part on the left side of the drawing, and an amorphous silicon thin film transistor using an amorphous silicon thin film as a channel layer is formed in the pixel part on the right side of the drawing. It is shown.

As shown in the drawing, a driving circuit part thin film transistor including gate electrodes 221D and 221'D, source / drain electrodes 222D and 223D, and an active pattern (not shown) is formed on the array substrate of the driving circuit part. The first circuit line 216D and the second circuit line 217D electrically connected to the gate electrodes 221D and 221'D and the source / drain electrodes 222D and 223D of the driving circuit part thin film transistor to apply a signal. This is arranged.

In this case, the source electrode 222D connected to the second circuit line 216D is electrically connected to the source region of the active pattern through the first connection electrode 290A, and the drain electrode 223D is connected to the second connection. The electrode 290B is electrically connected to the drain region of the active pattern. In addition, the gate electrodes 221D and 221'D connected to the first circuit line 216D are electrically connected to the third connection electrode 290C to transmit a signal to other circuit elements.

In this case, the gate electrodes 221D and 221'D of the driving circuit unit are cut differently from those of the first embodiment, and are disposed on the first gate electrode 221D and the first circuit line 216D positioned above the active pattern. And a second gate electrode 221'D extending from the second gate electrode 221'D. As described above, the first gate electrode 221D and the second gate electrode 221'D are connected to each other through a third connection electrode 290C. Electrical connection. The reason why the gate electrodes 221D and 221'D of the driving circuit unit are formed by cutting the active patterns therebetween is the first embodiment in the process of forming the active pattern and the gate insulating film in one mask process using diffraction exposure. Unlike the gate insulating layer, the gate insulating layer is patterned to have the same width (the width in the vertical direction) as the active pattern, thereby preventing short circuits with the gate electrodes occurring on the upper and lower surfaces of the active pattern.

In addition, a gate line 216 and a data line 217 are formed on the array substrate of the pixel portion, which are arranged vertically and horizontally to define the pixel region. In addition, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 216 and the data line 217, and is connected to the pixel part thin film transistor in the pixel area so as to have a common color filter substrate (not shown). A pixel electrode 118 for driving a liquid crystal (not shown) is formed together with the electrode.

At this time, in the actual pixel unit array substrate, N gate lines and M data lines cross each other, and there are N × M pixels. However, for convenience of description, a portion of the pixel area adjacent to one pixel area is shown in the drawing.

The pixel portion thin film transistor includes a gate electrode 221 connected to the gate line 216, a source electrode 222 connected to the data line 217, and a drain electrode 223 connected to the pixel electrode 218. In addition, the pixel portion thin film transistor includes an insulating film (not shown) for insulating the gate electrode 221 and the source / drain electrodes 222 and 223 and a source electrode 222 by a gate voltage supplied to the gate electrode 221. ) And an active pattern (not shown) forming a conductive channel between the drain electrode and the drain electrode 223.

In this case, a part of the source electrode 222 is connected to the data line 217, and a part of the drain electrode 223 is connected to the pixel electrode 218 through the first contact hole 280A.

In addition, a portion of the front gate line 216 extends to the corresponding pixel region to form a storage first electrode (not shown) to form a storage capacitor with the pixel electrode 218 of the pixel region. That is, the pixel electrode 218 overlapping the gate line 216 is electrically connected to the lower storage second electrode 240B through the second contact hole 280B, so that the storage first electrode and the storage second electrode are electrically connected to each other. The storage capacitor is formed between the electrodes 240B.

For reference, reference numerals 280C to 280H denote third to eighth contact holes of the driving circuit unit.

Hereinafter, a manufacturing process of the liquid crystal display device configured as described above will be described in detail with reference to the accompanying drawings.

8A to 8H are plan views sequentially illustrating a manufacturing process along lines VIIa-VIIa 'and VIIb-VIIb' of the array substrate shown in FIG. 7, and FIGS. 9A to 9F are views VIIa of the array substrate shown in FIG. 7. Sectional drawing which shows the manufacturing process along lines -VIIa 'and VIIb-VIIb' sequentially.

9A to 9F sequentially illustrate a manufacturing process of the array substrate of the driving circuit unit, the pixel unit, and the pad unit in order from the left side.

As shown in FIGS. 8A and 9A, a first circuit line 217D and a source / drain electrode are formed on a driving circuit part by using a photolithography process (first mask process) on a substrate 210 made of a transparent insulating material such as glass. The gate line 216, the gate electrode 221, and the storage first electrode 240A are formed in the pixel portion, and the gate pad 250 is formed in the pad portion.

In this case, the source electrode 222D of the driving circuit unit extends and is formed from a part of the first circuit line 217D, and the gate electrode 221 and the storage first electrode 240A of the pixel unit are the gate line 216. It extends from a part of) and is formed.

Thereafter, as illustrated in FIG. 9B, the first insulating layer 215A and the amorphous silicon thin film 220 are sequentially formed on the entire surface of the substrate 210.

In this case, the amorphous silicon thin film 220 of the driving circuit part is crystallized into a polycrystalline silicon thin film by performing a partial crystallization process.

After depositing an insulating material such as a silicon oxide film on the entire surface of the substrate 210, active patterns 224 and 224D are formed in the pixel portion and the driving circuit portion by a photolithography process (second mask process) using diffraction exposure. The gate insulating layer 260A is formed on the active pattern 224D of the driving circuit unit, and the etch stopper 260B is formed on the active pattern 224 of the pixel unit.

That is, the present embodiment can reduce the two mask processes of the second mask process and the third mask process of the first embodiment to one mask process by using diffraction exposure, which will be described in detail with reference to the drawings. .

10A to 10D are cross-sectional views specifically illustrating a second mask process of forming an active pattern, an etch stopper of a pixel portion, and a gate insulating film of a driving circuit portion using diffraction exposure in FIG. 9B.

As shown in FIG. 10A, an insulating film 260 made of an insulating material such as a silicon thin film 220 and a silicon oxide film is sequentially formed on an entire surface of the substrate 210 on which the first insulating film 215A is formed. A photosensitive film 300 made of a photosensitive material such as a photoresist is formed on the entire surface of the 210.

Thereafter, light is irradiated to the photosensitive film 300 through a diffraction mask M including a slit region.

In this case, the diffraction mask M is provided with a first transmission region I for transmitting all the light, a second transmission region II for transmitting only a part of the light, and a blocking region III for blocking all the irradiated light. Only the light transmitted through the mask M is irradiated to the photosensitive film 300.

In the diffraction mask M used in the present embodiment, the second transmission region II has a slit structure, and the exposure amount irradiated through the second transmission region II transmits all the light. It becomes less than the exposure amount irradiated to. Therefore, when the photoresist film 300 is applied and then exposed and developed using the mask M having the slit region II partially formed on the photoresist film 300, the thickness of the photoresist film remaining in the slit region II may be reduced. The thickness of the photosensitive film remaining in the first transmission region I or the blocking region III is different.

In this case, when the positive type photoresist is used as the photoresist film 300, the thickness of the photoresist film remaining in the slit region II is smaller than the thickness of the photoresist film remaining in the blocking region III and the photoresist is negative. In the case of using a ledge, the thickness of the photoresist remaining in the slit region II is less than the thickness of the photoresist remaining in the first transmission region I.

In this case, although a positive type photoresist is used in the present embodiment, the present invention is not limited thereto, and a negative type photoresist may be used.

Subsequently, after developing the photosensitive film 300 exposed through the diffraction mask M, as shown in FIG. 10B, all the light is blocked through the blocking region III and the second transmission region II. Photoresist patterns 300A to 300D having a predetermined thickness remain in regions where light is partially blocked, and the photoresist layer is removed in the first transmission region I region where all the light is irradiated to expose the surface of the insulating layer 260. .

In this case, the first photoresist pattern 300A and the second photoresist pattern 300B formed through the blocking region III may include the third photoresist pattern 300C and the fourth photoresist pattern 300D formed in the second transmission region II. Thicker than).

That is, the first photoresist pattern 300A having the first thickness and the fourth photoresist pattern 300D having the second thickness remain on the gate electrode 221 of the pixel portion, and the source electrode 222D and the drain electrode of the driving circuit portion remain. A second photoresist pattern 300B having a first thickness and a third photoresist pattern 300C having a second thickness remain on the predetermined region between the regions 223D.

The first photoresist pattern 300A of the pixel portion is for patterning an etch stopper to be described later, and the second photoresist pattern 300B of the driving circuit portion is for patterning a gate insulating film of the driving circuit portion.

Next, as shown in FIGS. 8B and 10C, the photoresist pattern 300A to 300D formed as described above is used as a mask, and the insulating layer 260 and the silicon thin film 220 formed thereunder are selectively removed to form the pixel. Active patterns 224 and 224D are formed in the portions and the driving circuit portions, respectively.

When the third photoresist pattern 300C and the fourth photoresist pattern 300D formed in the second transmission region II are completely removed by an ashing process, as shown in FIGS. 8C and 10D, the The first photoresist pattern 300A of the pixel portion and the second photoresist pattern 300B of the driving circuit portion are removed by the thickness of the third photoresist pattern 300C and the fourth photoresist pattern 300D of the second transmission region II. The fifth photoresist pattern 300A 'and the sixth photoresist pattern 300B' having a thickness of three remain.

Subsequently, when the remaining insulating patterns are patterned using the remaining photoresist patterns 300A 'and 300B' as a mask, as shown in FIGS. 8D and 9B, the gate insulating layer is formed on the active pattern 224D of the driving circuit unit. An 260A is formed and an etch stopper 260B is formed on the active pattern 224 of the pixel portion.

As described above, the active patterns 224 and 224D of the pixel portion and the driving circuit portion, the gate insulating layer 260A of the driving circuit portion, and the etch stopper 260B of the pixel portion use diffraction exposure, and thus, one mask is used as compared with the first embodiment. The process can be reduced.

Next, as shown in FIGS. 8E and 9C, the n + amorphous silicon thin film and the conductive film are sequentially formed on the entire surface of the substrate 210, and then the conductive film and the conductive film are formed using a photolithography process (third mask process). By selectively patterning an n + amorphous silicon thin film, gate electrodes 221D and 221'D are formed on the gate insulating layer 260A of the driving circuit portion, and an ohmic contact layer 225 and a source / drain electrode 222 are formed on the pixel portion. 223 and the storage second electrode 240B are formed, and a data pad 255 is formed in the pad portion.

In this case, as described above, the gate electrodes 221D and 221'D of the driving circuit unit are cut into the first gate electrode 221D and the second gate electrode 221'D with the active pattern 224D interposed therebetween. . This is to prevent a short circuit with the gate electrode occurring on the upper and lower surfaces of the driving circuit unit active pattern 224D.

In this case, a second circuit line 216D connected to the second gate electrode 121'D is formed in the driving circuit unit, and a data line 217 connected to the source electrode 222 is formed in the pixel unit. .

In addition, n + amorphous silicon thin films 225D and 225P remain in the driving circuit and the pad part in the same form as the driving circuit gate electrode 221D and the data pad 255, and the n + amorphous silicon thin film of the pixel part An ohmic contact layer 225 is formed to form an ohmic contact between a predetermined region of the active pattern 224 of the pixel portion and a source / drain electrode to be described later. At this time, an etch stopper 260B is formed on the active pattern 224 of the pixel portion, so that the n + amorphous silicon thin film is removed only up to the surface of the etch stopper 260B.

In addition, the storage second electrode 240B of the pixel portion overlaps with the storage first electrode 240A under the pixel portion to form a storage capacitor with the first insulating layer 215A therebetween.

8F and 9D, the pixel portion and the pad portion are covered by the blocking plate 270, and then doped with a high concentration of impurity ions only in the driving circuit portion so that the source region ( 224DS and drain region 224DD are formed.

In this case, when the N-type thin film transistor is configured in the driving circuit unit as in the present embodiment, the first gate electrode 221D of the driving circuit unit is patterned so as to have a smaller width than the lower gate insulating layer 260A. Impurity ions pass through the gate insulating film 260A corresponding to the width to be implanted into the active pattern 224D, so that the LED region 224DL is formed between the source / drain regions 224DS and 224DD and the channel region 224DC, respectively. Can be formed.

Next, as shown in FIGS. 8G and 9E, after forming the second insulating film 215B on the entire surface of the substrate 210, the second insulating film of the pixel portion using the photolithography process (fourth mask process) is formed. The first contact hole 280A exposing a part of the drain electrode 223 and the second contact hole 280B exposing a part of the storage second electrode 240B are formed by removing a part of the region 215B. The third contact hole 280C, the fourth contact hole 280D, and the active pattern exposing a part of the driving circuit part gate electrodes 221D and 221'D by removing a portion of the second insulating layer 215B of the driving circuit part are removed. A fifth contact hole 280E and a sixth contact hole 280F exposing portions of the source / drain regions 224DS and 224DD are formed, and partial regions of the second insulating layer 215b and the first insulating layer 215A are removed. The seventh contact hole 280G and a portion of the source / drain electrodes 222D and 223D of the driving circuit unit 8 A contact hole 280H is formed.

In addition, a part of the second insulating layer 215B and the first insulating layer 215A of the pad portion is removed to form a ninth contact hole 280I exposing a part of the gate pad 250 to form a ninth contact hole 280I. The tenth contact hole 280J exposing a portion of the data pad 255 is formed by removing the partial region.

In this case, the fifth contact hole 280E and the seventh contact hole 280G of the driving circuit unit are formed to electrically connect the source region 224DS and the source electrode 222D of the driving circuit unit. The sixth contact hole 280F and the eighth contact hole 280H are formed to electrically connect the drain region 224DD and the drain electrode 223D of the driving circuit unit. That is, the source / drain electrodes 222D and 223D formed at the lowermost layer to form the polycrystalline silicon thin film transistor of the driving circuit part through the same manufacturing process as the amorphous silicon thin film transistor of the pixel part are the fifth contact holes 280E to the eighth. The contact hole 280H is electrically connected to the source / drain regions 224DS and 224DD using a connection electrode to be described later.

8H and 9F, a transparent conductive material is deposited on the entire surface of the substrate 210, and then selectively patterned using a photolithography process (a fifth mask process). The pixel electrode 218 is connected to the drain electrode 223 through the first contact hole 280A and connected to the storage second electrode 240B through the second contact hole 280B. The sixth contact is formed by forming a first connection electrode 290A electrically connecting the source region 224DS and the source electrode 222D of the driving circuit unit through the fifth contact hole 280E and the seventh contact hole 280G. A second connection electrode 290B is formed to electrically connect the drain region 224DD and the drain electrode 223D of the driving circuit unit through the hole 280F and the eighth contact hole 280H.

In addition, the first gate electrode 221D and the second gate electrode 221'D of the driving circuit unit may be electrically connected to each other through the third contact hole 280C and the fourth contact hole 280D. A third connection electrode 290C exposed through the second electrode 290C, and the pad part is electrically connected to the gate pad 250 and the data pad 255 through the ninth contact hole 280I and the tenth contact hole 280J, respectively. A gate pad electrode 251 and a data pad electrode 256 are formed to be connected and exposed to the outside.

As described above, in the second embodiment, the amorphous silicon thin film transistor is formed on the pixel portion in five mask processes by forming the active pattern, the gate insulating layer of the driving circuit portion, and the etch stopper of the pixel portion through one mask process using diffraction exposure. The polycrystalline silicon thin film transistor can be formed in the driving circuit portion.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

As described above, the liquid crystal display device and the method of manufacturing the same according to the present invention form a polycrystalline silicon thin film transistor having a coplanar structure in the driving circuit portion, thereby making it possible to manufacture a high mobility device, thereby enabling the driver driving circuit to be embedded.

In addition, the polycrystalline silicon thin film transistor is formed at the same time in the driving circuit section within the range of not deforming the manufacturing process of the amorphous silicon thin film transistor in the pixel section, so that the driver driving circuit can be embedded in the panel without the addition of the manufacturing step. Provides cost savings

In addition, since the pixel portion is composed of an amorphous silicon thin film transistor using an amorphous silicon thin film, the pixel portion provides an effect of higher productivity than a general driving circuit integrated liquid crystal display device requiring laser crystallization of the entire surface of the substrate.

Claims (61)

Providing a substrate divided into a pixel portion and a driving circuit portion; Forming a source / drain electrode on the driving circuit portion of the substrate, and forming a gate electrode and a gate line on the pixel portion; Forming a first insulating film on the substrate; Forming an active pattern on the driving circuit portion and the pixel portion of the substrate; Forming a gate insulating layer on the active pattern of the driving circuit unit and forming an etch stopper on the active pattern of the pixel unit; Forming a gate electrode on the gate insulating layer of the driving circuit unit, and forming an ohmic contact layer and a source / drain electrode on the active pattern of the pixel unit; Implanting a high concentration of impurity ions into the driving circuit to form a source / drain region in a predetermined region of the active pattern of the driving circuit; Forming a second insulating film on the entire surface of the substrate; And Forming a pixel electrode in the pixel portion of the substrate, and forming a first connection electrode connecting the source region and the source electrode to a driving circuit portion and a second connection electrode connecting the drain region and the drain electrode to a driving circuit portion; Method for manufacturing a display device. 2. The method of claim 1, further comprising forming a first circuit line connected to the source electrode in a driving circuit portion of the substrate. The method of claim 1, further comprising forming a storage first electrode extending from the gate line in the pixel portion of the substrate. The method of claim 1, wherein the source / drain electrodes of the driving circuit unit, the gate electrode and the gate line of the pixel unit are formed through a first mask process using a first conductive material. 5. The method of claim 4, further comprising forming a gate pad in a predetermined region of the substrate using the first conductive material through the first mask process. 6. The method of claim 1, wherein the forming of the active pattern on the substrate is performed. Forming an amorphous silicon thin film on the entire surface of the substrate; Crystallizing an amorphous silicon thin film of the driving circuit unit to form a polycrystalline silicon thin film; And Patterning the silicon thin film through a second mask process to form a first active pattern made of an amorphous silicon thin film and a second active pattern made of a polycrystalline silicon thin film in the pixel portion and the driving circuit portion, respectively. Method of manufacturing a liquid crystal display device. 7. A method according to claim 6, wherein the amorphous silicon thin film is selectively crystallized by laser crystallization to form a polycrystalline silicon thin film. The liquid crystal of claim 1, wherein an insulating film, such as a silicon oxide film, is formed on the entire surface of the substrate, and then patterned through a third mask process to form a gate insulating film in the driving circuit and an etch stopper in the pixel. Method for manufacturing a display device. The method of claim 1, wherein forming a gate electrode of the driving circuit unit, an ohmic contact layer of the pixel unit, and a source / drain electrode is performed. Depositing an n + amorphous silicon thin film and a second conductive material over the substrate; And Patterning the second conductive material and the n + amorphous silicon thin film through a fourth mask process to form a gate electrode on the gate insulating layer of the driving circuit unit, and forming an ohmic contact layer and a source / drain electrode on the active pattern of the pixel unit Method of manufacturing a liquid crystal display device comprising the step. 10. The liquid crystal display of claim 9, further comprising forming a second circuit line connected to the gate electrode of the driving circuit part by using the second conductive material through the fourth mask process. Manufacturing method. The method of claim 9, further comprising forming a data line connected to the pixel portion source electrode in the pixel portion using the second conductive material through the fourth mask process. Way. 10. The method of claim 9, further comprising forming a storage second electrode on the storage first electrode of the pixel part using the second conductive material through the fourth mask process. . 10. The method of claim 9, further comprising forming a data pad in a predetermined region of the substrate using the second conductive material through the fourth mask process. The method of claim 9, wherein the n + amorphous silicon thin film is patterned through the fourth mask process to expose an etch stopper on the active part of the pixel part, and is connected to a left and right predetermined region of the active pattern to form an ohmic contact. A method of manufacturing a liquid crystal display device, characterized in that to form an ohmic contact layer for forming a. 2. A method according to claim 1, wherein a high concentration of impurity ions are implanted into the driving circuit portions other than the pixel portion to form source and drain regions in predetermined regions to the left and right of the active pattern of the driving circuit portion. The method of claim 15, wherein the pixel part is covered by a blocking plate that blocks a part of light, such as a shadow mask, and then high concentration impurity ions are injected only into the driving circuit part. The method of claim 15, wherein the gate electrode of the driving circuit unit prevents the dopant from penetrating into the active pattern under the driving circuit to form a channel region in the center region of the active pattern. 18. The gate electrode of claim 17, wherein the gate electrode of the driving circuit unit is patterned to have a smaller width than that of the lower gate insulating layer, and impurity ions are injected into a predetermined region of the active pattern by passing through the gate insulating layer corresponding to the width. A method for manufacturing a liquid crystal display device, comprising: forming an LED region between a source / drain region and a channel region of an active pattern. The method of claim 1, wherein forming the pixel electrode of the pixel portion, the first connection electrode and the second connection electrode of the driving circuit portion is performed. By removing the partial region of the second insulating layer of the pixel portion through the fifth mask process to form a first contact hole for exposing a part of the drain electrode of the pixel portion, and removing the partial region of the second insulating layer of the driving circuit portion gate electrode Forming a third contact hole and a fourth contact hole exposing a portion of the source / drain regions of the active pattern and the second contact hole exposing a portion of the active pattern, and removing a portion of the second insulating layer and the first insulating layer Forming a fifth contact hole and a sixth contact hole exposing a portion of the source / drain electrode of the second contact hole; Depositing a transparent third conductive material over the entire surface of the substrate; And Patterning the third conductive material through a sixth mask process to form a pixel electrode connected to the drain electrode through the first contact hole in the pixel portion, and forming the third contact hole and the fifth contact hole in the driving circuit portion. Forming a first connection electrode connecting the source region and the source electrode of the driving circuit unit and a second connection electrode connecting the drain region and the drain electrode of the driving circuit unit through the fourth contact hole and the sixth contact hole; Method of manufacturing a liquid crystal display device characterized in that. 20. The method of claim 19, further comprising removing a portion of the second insulating layer of the pixel portion through the fifth mask process to form a seventh contact hole exposing a portion of the storage second electrode. Method of manufacturing a liquid crystal display device. 21. The method of claim 20, wherein the pixel electrode is electrically connected to the storage second electrode through the seventh contact hole. The method of claim 19, wherein the third conductive material is formed through the sixth mask process, and the third connection electrode is electrically connected to the gate electrode of the driving circuit unit through the second contact hole and exposed to the outside. Method of manufacturing a liquid crystal display device further comprising. 20. The method of claim 19, wherein a portion of the second insulating film and the first insulating film is removed through the fifth mask process to form an eighth contact hole exposing a portion of the gate pad, and a portion of the second insulating film is removed. And forming a ninth contact hole exposing a portion of the data pad. The gate pad of claim 23, wherein the gate pad is formed of the third conductive material through the sixth mask process, and is electrically connected to the gate pad and the data pad through the eighth and ninth contact holes, respectively. A method of manufacturing a liquid crystal display device, comprising the step of forming an electrode and a data pad electrode. Providing a substrate divided into a pixel portion and a driving circuit portion; Forming a source / drain electrode on the driving circuit portion of the substrate, and forming a gate electrode and a gate line on the pixel portion; Forming a first insulating film on the substrate; Forming an active pattern on the driving circuit portion and the pixel portion of the substrate using diffraction exposure, and forming a gate insulating layer on the active pattern on the driving circuit portion and an etch stopper on the active pattern on the pixel portion; Forming a gate electrode (a first gate electrode and a second gate electrode) on the gate insulating layer of the driving circuit unit, and forming an ohmic contact layer and a source / drain electrode on the active pattern of the pixel unit; Implanting a high concentration of impurity ions into the driving circuit to form a source / drain region in a predetermined region of the active pattern of the driving circuit; Forming a second insulating film on the entire surface of the substrate; And Forming a pixel electrode in the pixel portion of the substrate, and forming a first connection electrode connecting the source region and the source electrode to a driving circuit portion and a second connection electrode connecting the drain region and the drain electrode to a driving circuit portion; Method for manufacturing a display device. 27. The method of claim 25, further comprising forming a first circuit line connected to the source electrode in a driving circuit portion of the substrate. 27. The method of claim 25, further comprising forming a storage first electrode extending from the gate line in the pixel portion of the substrate. 26. The method of claim 25, wherein the source / drain electrodes of the driving circuit unit, the gate electrode and the gate line of the pixel unit are formed through a first mask process using a first conductive material. 29. The method of claim 28, further comprising forming a gate pad in a predetermined region of the substrate with the first conductive material through the first mask process. The method of claim 25, wherein forming an active pattern on the substrate, and forming an etch stopper on the active pattern of the gate insulating layer and the pixel portion of the driving circuit portion, Forming an amorphous silicon thin film on the entire surface of the substrate; Crystallizing an amorphous silicon thin film of the driving circuit unit to form a polycrystalline silicon thin film; Depositing an insulating material such as a silicon oxide film on the entire surface of the substrate; Forming a photoresist film such as a photoresist on the entire surface of the substrate; A first photosensitive film having a first thickness in a predetermined region above the gate electrode of the pixel part by applying a mask having a first transmission region for transmitting all of the light, a second transmission region for transmitting only a part of the light, and a blocking region for blocking the light; Forming a pattern, forming a second photoresist pattern having a second thickness on the left and right sides of the first photoresist pattern, and forming a third photoresist pattern having a first thickness on a predetermined region between the source electrode and the drain electrode of the driving circuit unit Forming a fourth photoresist pattern having a second thickness on left and right sides of the third photoresist pattern; Patterning the insulating material and the silicon thin film using the first to fourth photoresist patterns as a mask to form a first active pattern and a second active pattern in the pixel portion and the driving circuit portion, respectively; Removing the second photoresist pattern and the fourth photoresist pattern; And Re-patterning the patterned insulating material using the remaining first photoresist pattern and the third photoresist pattern as a mask to form an etch stopper and a gate insulating layer on the first active pattern and the second active pattern, respectively; Method of manufacturing a liquid crystal display device, characterized in that. 31. The method of claim 30, wherein in the case of using a positive type photoresist, the blocking region of the mask defines an etch stopper region of the pixel portion and a gate insulating layer region of the driving circuit portion, and the second transmission region is formed on the left and right sides of the blocking region. And a first active pattern region and a second active pattern region defined in the pixel portion and the driving circuit portion, respectively. 31. The liquid crystal of claim 30, wherein the mask has a diffraction pattern formed in a second transmissive region that transmits only a part of the light to form a second photoresist pattern and a fourth photoresist pattern having a second thickness that is thinner than the first thickness. Method for manufacturing a display device. The method of claim 30, wherein the second photoresist pattern and the fourth photoresist pattern are removed through an ashing process, and the first photoresist pattern and the second photoresist pattern are only as large as a second thickness of the second photoresist pattern and the fourth photoresist pattern. A method of manufacturing a liquid crystal display device, characterized in that it remains with the removed third thickness. 31. The method of claim 30, wherein the amorphous silicon thin film is selectively crystallized by laser crystallization to form a polycrystalline silicon thin film. The method of claim 25, wherein forming the gate electrode of the driving circuit unit, the ohmic contact layer of the pixel unit, and a source / drain electrode is performed. Depositing an n + amorphous silicon thin film and a second conductive material over the substrate; And Patterning the second conductive material and the n + amorphous silicon thin film through a third mask process to form a gate electrode on the gate insulating layer of the driving circuit unit, and forming an ohmic contact layer and a source / drain electrode on the active pattern of the pixel unit Method of manufacturing a liquid crystal display device comprising the step. 36. The liquid crystal display device of claim 35, further comprising forming a second circuit line connected to the gate electrode of the driving circuit part with the second conductive material through the third mask process. Manufacturing method. The gate electrode of claim 36, wherein the gate electrode of the driving circuit unit is cut between the active patterns of the driving circuit unit, and includes a first gate electrode positioned on the active pattern and a second gate electrode connected to the second circuit line. Method of manufacturing a liquid crystal display device, characterized in that. 36. The liquid crystal display device of claim 35, further comprising forming a data line connected to the pixel portion source electrode in the pixel portion using the second conductive material through the third mask process. Way. 36. The method of claim 35, further comprising forming a storage second electrode on the storage first electrode of the pixel portion with the second conductive material through the third mask process. . 36. The method of claim 35, further comprising forming a data pad in a predetermined region of the substrate with the second conductive material through the third mask process. The n + amorphous silicon thin film of the pixel portion is patterned through the third mask process to expose an etch stopper on the active portion of the pixel portion, and is connected to a predetermined left and right region of the active pattern to form an ohmic contact. A method of manufacturing a liquid crystal display device, characterized in that to form an ohmic contact layer for forming a. 26. The method of claim 25, wherein a high concentration of impurity ions are implanted into the driving circuit portions other than the pixel portion to form source and drain regions in predetermined regions to the left and right of the active pattern of the driving circuit portion. 43. The manufacturing method of a liquid crystal display device according to claim 42, wherein the pixel portion is covered with a blocking plate that blocks a part of light, such as a shadow mask, and then high concentration impurity ions are injected only into the driving circuit portion. 43. The method of claim 42, wherein the gate electrode of the driving circuit unit prevents the dopant from penetrating into the active pattern under the driving circuit to form a channel region in the central region of the active pattern. 45. The gate electrode of claim 44, wherein the gate electrode of the driving circuit unit is patterned to have a smaller width than that of the lower gate insulating layer, and impurity ions are injected into a predetermined region of the active pattern by passing through the gate insulating layer corresponding to the width. A method for manufacturing a liquid crystal display device, comprising: forming an LED region between a source / drain region and a channel region of an active pattern. The method of claim 25, wherein the forming of the pixel electrode of the pixel unit, the first connection electrode and the second connection electrode of the driving circuit unit is performed. The first contact hole exposing a part of the drain electrode of the pixel part is formed by removing a part of the second insulating film of the pixel part through the fourth mask process, and removing the part of the second insulating film of the driving circuit part by removing the partial area of the second insulating film of the pixel part. Forming a second contact hole and a third contact hole exposing a portion of the gate electrode and the second gate electrode, and a fourth contact hole and a fifth contact hole exposing a portion of the source / drain region of the active pattern, and forming the second contact hole. Removing a portion of the first insulating layer to form a sixth contact hole and a seventh contact hole exposing a portion of the source / drain electrode of the driving circuit unit; Depositing a transparent third conductive material over the entire surface of the substrate; And Patterning the third conductive material through a fifth mask process to form a pixel electrode connected to the drain electrode through the first contact hole in the pixel portion, and forming the fourth contact hole and the sixth contact hole in the driving circuit portion. Forming a first connection electrode connecting the source region and the source electrode of the driving circuit unit and a second connection electrode connecting the drain region and the drain electrode of the driving circuit unit through the fifth contact hole and the seventh contact hole; Method of manufacturing a liquid crystal display device characterized in that. 48. The method of claim 46, further comprising forming an eighth contact hole exposing a portion of the storage second electrode by removing a portion of the second insulating layer of the pixel portion through the fourth mask process. Method of manufacturing a liquid crystal display device. 48. The method of claim 47, wherein the pixel electrode is electrically connected to the storage second electrode through the eighth contact hole. The method of claim 46, wherein the third conductive material is formed through the fifth mask process, and the first gate electrode and the second gate electrode of the driving circuit unit are connected to the outside through the second contact hole and the third contact hole. And forming a third connection electrode to expose the liquid crystal display. 48. The method of claim 46, wherein a portion of the second insulating film and the first insulating film is removed through the fourth mask process to form a ninth contact hole exposing a portion of the gate pad, and a portion of the second insulating film is removed. And forming a tenth contact hole exposing a portion of the data pad. 51. The gate pad of claim 50, wherein the gate pad is formed of the third conductive material through the fifth mask process, and is electrically connected to a gate pad and a data pad through the ninth and tenth contact holes, respectively. A method of manufacturing a liquid crystal display device, comprising the step of forming an electrode and a data pad electrode. Providing a substrate divided into a pixel portion and a driving circuit portion; Forming a source / drain electrode on the driving circuit portion of the substrate, and forming a gate electrode and a gate line on the pixel portion; Forming a first insulating film on the substrate; Forming an active pattern on the driving circuit portion and the pixel portion of the substrate, and forming an gate insulating layer on the active pattern on the driving circuit portion and an etch stopper on the active pattern on the pixel portion; Forming a gate electrode on the gate insulating layer of the driving circuit unit, and forming a source / drain electrode on the active pattern of the pixel unit; Implanting a high concentration of impurity ions into the driving circuit to form a source / drain region in a predetermined region of the active pattern of the driving circuit; Forming a second insulating film on the entire surface of the substrate; And Forming a pixel electrode in the pixel portion of the substrate, and forming a first connection electrode connecting the source region and the source electrode to a driving circuit portion and a second connection electrode connecting the drain region and the drain electrode to a driving circuit portion; Method for manufacturing a display device. A substrate divided into a pixel portion and a driving circuit portion; An amorphous silicon thin film transistor formed in the pixel portion of the substrate, the amorphous silicon thin film transistor comprising a gate electrode, an active pattern, and a source / drain electrode; And A polycrystalline silicon thin film transistor formed on a driving circuit of the substrate and comprising a source / drain electrode, an active pattern, and a gate electrode formed on the same layer corresponding to each of the gate electrode, the active pattern, and the source / drain electrode of the pixel unit; LCD display device. 54. The liquid crystal display device according to claim 53, wherein the source / drain electrodes of the driving circuit portion are made of the same first conductive material as the gate electrode of the pixel portion. 54. The liquid crystal display device according to claim 53, wherein the gate electrode of the driving circuit part is made of the same second conductive material as the source / drain electrode of the pixel part. 54. The liquid crystal display device according to claim 53, further comprising an etch stopper formed of an insulating material such as a silicon oxide film and formed over a predetermined region of the active pattern of the pixel portion. 58. The liquid crystal display of claim 56, further comprising a gate insulating film formed on the same layer as the etch stopper of the pixel portion using the insulating material, and formed between the active pattern of the driving circuit portion and the gate electrode. Device. 54. The liquid crystal display device of claim 53, further comprising a pixel electrode connected to the drain electrode of the pixel portion and made of a transparent third conductive material. 59. The first and second connection electrodes of claim 58, wherein the third conductive material is formed on the same layer as the pixel electrode, and connects a predetermined region of the active pattern of the driving circuit unit to a source / drain electrode. Liquid crystal display comprising a further. 59. The method of claim 58, further comprising a third connection electrode formed on the same layer as the pixel electrode by using the third conductive material, and connected to the gate electrode of the driving circuit to expose to the outside. LCD display device. 54. The liquid crystal display device according to claim 53, wherein the active pattern of the pixel portion is made of an amorphous silicon thin film, and the active pattern of the driving circuit portion is made of a polycrystalline silicon thin film crystallized from the amorphous silicon thin film.

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