KR20060074991A - Method for fabricating capacitor - Google Patents

Method for fabricating capacitor Download PDF

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KR20060074991A
KR20060074991A KR1020040113534A KR20040113534A KR20060074991A KR 20060074991 A KR20060074991 A KR 20060074991A KR 1020040113534 A KR1020040113534 A KR 1020040113534A KR 20040113534 A KR20040113534 A KR 20040113534A KR 20060074991 A KR20060074991 A KR 20060074991A
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capacitor manufacturing
capacitor
forming
film
dielectric
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KR1020040113534A
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Korean (ko)
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길덕신
염승진
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 단일 반응 용기에서 300℃이하의 온도로 유전막을 형성하는 캐패시터의 누설전류 특성을 개선하는데 적합한 캐패시터 제조 방법을 제공하기 위한 것으로 이를 위한 본 발명의 캐패시터 제조 방법은 하부 전극용 폴리실리콘막을 형성하는 단계; 상기 폴리실리콘막을 활성화된 산소로 표면 처리하는 단계; 상기 표면 처리된 폴리실리콘막 상에 HfO2/Al2O3 유전막을 형성하는 단계; 및 상기 유전막 상에 상부 전극을 형성하는 단계를 포함한다.
The present invention is to provide a capacitor manufacturing method suitable for improving the leakage current characteristics of the capacitor forming the dielectric film at a temperature of 300 ℃ or less in a single reaction vessel for the capacitor manufacturing method of the present invention to form a polysilicon film for the lower electrode Doing; Surface treating the polysilicon film with activated oxygen; Forming an HfO 2 / Al 2 O 3 dielectric film on the surface-treated polysilicon film; And forming an upper electrode on the dielectric layer.

원자층 증착, 캐패시터, 유전막, 오존, 산소, 플라즈마Atomic layer deposition, capacitors, dielectric films, ozone, oxygen, plasma

Description

캐패시터 제조 방법{METHOD FOR FABRICATING CAPACITOR} Capacitor Manufacturing Method {METHOD FOR FABRICATING CAPACITOR}             

도 1은 종래 기술에 따른 캐패시터 제조 방법을 나타낸 공정 단면도,1 is a process cross-sectional view showing a capacitor manufacturing method according to the prior art,

도 2a 내지 도 2e는 본 발명의 실시예에 따른 캐패시터 제조 방법을 나타낸 공정 단면도,2a to 2e is a cross-sectional view showing a capacitor manufacturing method according to an embodiment of the present invention,

도 3은 본 발명의 일실시예에 적용되는 원자층 증착법을 설명한 그래프.
3 is a graph illustrating an atomic layer deposition method applied to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 하부 전극 22 : 자연산화막21: lower electrode 22: natural oxide film

23 : SiN 24 : SiON23: SiN 24: SiON

25 : Al2O3 26 : HfO2 25: Al 2 O 3 26: HfO 2

27 : 상부 전극
27: upper electrode

본 발명은 반도체 제조 기술에 관한 것으로 특히 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method of manufacturing a capacitor.

현재 반도체 소자의 고집적화를 달성하기 위하여 셀 면적의 감소 및 동작 전압의 저전압화에 관한 연구, 개발이 활발하게 진행되고 있다. 더구나, 반도체 소자의 고집적화가 이루어질수록 캐패시터의 면적이 급격하게 감소되지만 기억소자의 동작에 필요한 전하, 즉 단위 면적에 확보되는 정전 용략은 증가되어야만 한다.In order to achieve high integration of semiconductor devices, researches and developments on reducing the cell area and lowering the operating voltage have been actively conducted. In addition, as the integration of semiconductor devices increases, the area of the capacitor is drastically reduced, but the charge necessary for the operation of the memory device, that is, the electrostatic capacity secured in the unit area must be increased.

캐패시터의 충분한 유전 용량을 확보하기 위해서는 유전막의 박막화, 유효 표면적의 증대 등의 구조적인 연구와 기존 실리콘 산화막으로 사용하던 유전막을 NO(Nitride-Oxide) 구조 또는 ONO(Oxide-Nitride-Oxide) 등으로 대체하려는 재료적인 연구가 진행되고 있다.In order to secure a sufficient dielectric capacity of the capacitor, structural studies such as thinning the dielectric film and increasing the effective surface area, and replacing the dielectric film used as a silicon oxide film with a structure of NO (Nitride-Oxide) or ONO (Oxide-Nitride-Oxide) There is material research going on.

하지만, DRAM(Dynamic Random Access Memory)의 집적도가 증가함에 따라서 캐패시터의 면적이 작아지게 되어 요구되는 유전용량의 확보가 점점 어려워지게 되었다. 요구되는 유전용량을 확보하기 위해서는 유전박막의 두께를 낮추거나 유전 상수가 큰 물질을 적용하여야 한다.However, as the integration degree of DRAM (Dynamic Random Access Memory) increases, the area of the capacitor becomes smaller, and it becomes increasingly difficult to secure the required dielectric capacity. To secure the required dielectric capacity, it is necessary to reduce the thickness of the dielectric thin film or apply a material having a high dielectric constant.

따라서, 기존의 ONO 물질 대신 유전 상수가 큰 Al2O3나 HfO2 또는 Al2 O3와 HfO2를 적층 형성한 구조가 개발되고 있다. Accordingly, a structure in which Al 2 O 3 or HfO 2 or Al 2 O 3 and HfO 2 having a large dielectric constant is laminated instead of the conventional ONO material has been developed.

도 1은 종래 기술에 따른 캐패시터 제조 방법을 도시한 공정 단면도이다.1 is a process cross-sectional view showing a capacitor manufacturing method according to the prior art.

도 1에 도시된 바와 같이, 하부 전극(11) 상에 존재하는 자연산화막(도시 생략)을 제거한다. 자연산화막은 HF가 희석된 HF 용액, NH4F와 혼합한 HF 용액 또는 BOE 용액을 사용한 세정 공정을 실시하므로써 제거된다. As shown in FIG. 1, a natural oxide film (not shown) existing on the lower electrode 11 is removed. The natural oxide film is removed by performing a washing step using HF diluted HF solution, HF solution mixed with NH 4 F or BOE solution.

계속해서, 저온(300℃ 이하)의 원자층 증착법(Atomic Layer Deposition)을 이용하여 캐패시터 유전막 Al2O3(12)와 HfO2(13)를 적층 형성한다. 이어서, HfO2(13) 상에 상부 전극(14)을 형성한다. Subsequently, the capacitor dielectric films Al 2 O 3 (12) and HfO 2 (13) are laminated and formed by using an atomic layer deposition method of low temperature (300 ° C. or lower). Subsequently, the upper electrode 14 is formed on the HfO 2 13.

상술한 바와 같이 종래 기술은, 양산성의 확보를 위해 Al2O3 및 HfO2를 단일 반응 용기에서 형성할 경우 HfO2의 반응 온도 때문에 300℃ 이하의 온도에서 전체 공정을 진행하여야만 한다. 이 경우 누설전류 특성에 기여하는 폴리실리콘 전극 계면에서의 SiO2 형성의 부족으로 누설전류 특성이 급격히 열화되고, 또 후속 열공정에서도 전기적 특성이 저하되는 문제가 있다. 또한 저온 공정에 기인한 박막 내의 C, H 등의 불순물 역시 누설전류 특성을 저해하는 요인이 되고 있다.
As described above, in order to ensure mass productivity, when the Al 2 O 3 and HfO 2 are formed in a single reaction vessel, the entire process must be performed at a temperature of 300 ° C. or lower due to the reaction temperature of HfO 2 . In this case, there is a problem that the leakage current characteristic is rapidly deteriorated due to the lack of SiO 2 formation at the polysilicon electrode interface contributing to the leakage current characteristic, and the electrical characteristics are deteriorated in subsequent thermal processes. In addition, impurities such as C and H in the thin film due to the low temperature process are also a factor to inhibit the leakage current characteristics.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 단일 반응 용기에서 300℃이하의 온도로 유전막을 형성하는 캐패시터의 누설전류 특성을 개선하는데 적합한 캐패시터 제조 방법을 제공하는데 그 목적이 있다.
The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a capacitor suitable for improving the leakage current characteristics of a capacitor forming a dielectric film at a temperature of 300 ° C. or less in a single reaction vessel. .

상기 목적을 달성하기 위한 일 특징적인 본 발명의 캐패시터 제조 방법은 하부 전극용 폴리실리콘막을 형성하는 단계, 상기 폴리실리콘막을 활성화된 산소로 표면 처리하는 단계, 상기 표면 처리된 폴리실리콘막 상에 HfO2/Al2O3 유전막을 형성하는 단계, 및 상기 유전막 상에 상부 전극을 형성하는 단계를 포함한다.
According to one aspect of the present invention, there is provided a capacitor manufacturing method for forming a polysilicon film for a lower electrode, surface treatment of the polysilicon film with activated oxygen, and HfO 2 on the surface-treated polysilicon film. Forming an / Al 2 O 3 dielectric layer, and forming an upper electrode on the dielectric layer.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

도 2a 내지 도 2e는 본 발명의 일실시예에 따른 캐패시터 제조 방법을 도시한 공정 단면도이다.2A to 2E are cross-sectional views illustrating a method of manufacturing a capacitor according to an embodiment of the present invention.

도 2a에 도시된 바와 같이, 하부 전극(21) 상에 형성된 자연산화막(22)을 제거한다. 이 때, 자연산화막(22)은 HF가 희석된 HF 용액, NH4F와 혼합한 HF 용액 또는 BOE 용액을 사용한 세정 공정을 통해 제거된다.As shown in FIG. 2A, the native oxide film 22 formed on the lower electrode 21 is removed. At this time, the natural oxide film 22 is removed through a cleaning process using HF diluted HF solution, HF solution mixed with NH 4 F or BOE solution.

이어서, 도 2b에 도시된 바와 같이, 자연산화막(22)이 제거된 하부 전극(21) 표면에 질화 처리를 실시한다. Next, as shown in FIG. 2B, nitriding treatment is performed on the surface of the lower electrode 21 from which the natural oxide film 22 is removed.

질화 처리는 산소 분위기의 후속 고온 열처리과정에 의해 하부 전극(21)이 산화되는 것을 억제하기 위한 산화저항막을 형성하는 과정으로서, 먼저 NH3 또는 N2 분위기에서 800℃∼900℃의 온도 범위에서 급속 열질화(RTN)를 실시하여 하부 전극(21) 표면을 질화시켜 SixNy(23)을 형성한다. Nitriding is a process of forming an oxidation resistant film for inhibiting the lower electrode 21 from being oxidized by a subsequent high temperature heat treatment process in an oxygen atmosphere, which is rapidly performed in a temperature range of 800 ° C. to 900 ° C. in an NH 3 or N 2 atmosphere. Thermal nitriding (RTN) is performed to nitride the surface of the lower electrode 21 to form Si x N y (23).

또한, 질화 처리의 다른 방법으로 250℃∼450℃의 온도 범위로 플라즈마 처리하는 방법이 있다.  As another method of nitriding treatment, there is a method of plasma treatment in a temperature range of 250 ° C to 450 ° C.                     

이어서, 도 2c에 도시된 바와 같이, SixNy(23)이 형성된 하부 전극(21) 전면에 산화 처리를 실시한다. 이 때, 산화 처리는 300℃∼450℃의 온도 범위에서 오존 플라즈마 또는 산소 플라즈마를 노출시켜 진행하는데 산화 처리를 진행한 후, 10Å∼50Å의 두께를 갖는 SiON(24)이 형성된다. SiON(24)은 누설 전류 특성을 개선할 수 있는 산소확산방지막으로서의 역할을 한다. Subsequently, as illustrated in FIG. 2C, an oxidation process is performed on the entire surface of the lower electrode 21 on which the Si x N y 23 is formed. At this time, the oxidation treatment is performed by exposing the ozone plasma or the oxygen plasma in the temperature range of 300 ° C to 450 ° C. After the oxidation treatment is performed, a SiON 24 having a thickness of 10 Pa to 50 Pa is formed. SiON 24 serves as an oxygen diffusion prevention film that can improve leakage current characteristics.

한편, SiON(24)의 두께를 조절하기 위하여 오존 또는 산소 플라즈마를 실시할 때, 일정 시간 동안 밸브의 개폐 횟수를 조절하므로써 산화 정도를 결정한다.On the other hand, when performing ozone or oxygen plasma to adjust the thickness of the SiON 24, the degree of oxidation is determined by adjusting the number of opening and closing of the valve for a predetermined time.

이어서, 도 2d에 도시된 바와 같이, SiON(24) 상에 유전막 Al2O3박막(25)과 HfO2박막(26)을 순차적으로 형성한다. Al2O3박막(25)은 단원자 증착법으로 Al(CH3)3를 반응 소스로 사용하고, Hf(O-tBu)4, Hf(Hf(MMP)4, Hf[N(CH3) 2]4, Hf[N(C2H5)(CH3)]4, Hf[N(C2H5)2 ]4, HfCl4, HfI4의 그룹에서 선택된 반응 가스를 사용하여 형성한다.Subsequently, as shown in FIG. 2D, the dielectric film Al 2 O 3 thin film 25 and the HfO 2 thin film 26 are sequentially formed on the SiON 24. The Al 2 O 3 thin film 25 uses Al (CH 3 ) 3 as the reaction source by monoatomic deposition, Hf (O-tBu) 4 , Hf (Hf (MMP) 4 , Hf [N (CH 3 ) 2 ] 4 , Hf [N (C 2 H 5 ) (CH 3 )] 4 , Hf [N (C 2 H 5 ) 2 ] 4 , HfCl 4 , HfI 4 .

또한, Al2O3박막(25)과 HfO2박막(26)은 H2O, 오존, 산소 플라즈마를 반응 가스로 사용하여 형성한다.The Al 2 O 3 thin film 25 and the HfO 2 thin film 26 are formed using H 2 O, ozone, and oxygen plasma as reaction gases.

이어서, 도 2e에 도시된 바와 같이, 유전막(25/26) 상에 상부 전극(27)을 형성한다. 상부 전극(27)은 P, As가 도핑된 폴리실리콘, TiN, Ru, RuO2, Pt, Ir, IrO2의 그룹에서 선택된 물질을 사용한다.Subsequently, as shown in FIG. 2E, an upper electrode 27 is formed on the dielectric film 25/26. The upper electrode 27 uses a material selected from the group of polysilicon doped with P, As, TiN, Ru, RuO 2 , Pt, Ir, IrO 2 .

도 3은 본 발명의 일실시예에 적용되는 원자층 증착법을 나타내는 그래프이 다. 먼저, 제 1단계에서 챔버 내에 웨이퍼를 로딩(loading)시킨 후 챔버 내에 소스가스를 공급하여 웨이퍼 표면에 소스가스의 화학 흡착(Chemical absorption)을 유도하고, 제 2단계인 퍼지 스텝(Purge step)에서 퍼지가스를 주입하여(예컨대 불활성 가스(inert gas)) 여분의 미흡착/반응한 소스가스 혹은 반응 부가물을 제거한다.3 is a graph showing an atomic layer deposition method applied to an embodiment of the present invention. First, in the first step, the wafer is loaded into the chamber, and then source gas is supplied into the chamber to induce chemical absorption of the source gas on the wafer surface. In the second step, purge step Purge gas is injected (eg inert gas) to remove excess unadsorbed / reacted source gas or reaction adducts.

이어서, 제 3단계에서 반응가스를 공급하여 웨이퍼 표면에 화학 흡착된 화합물 표면 그룹과 반응을 유도하여 원자층을 증착하는 과정을 수행한다. 계속해서, 제 4단계에서 다시 불활성가스와 같은 퍼지가스를 주입하여 여분의 반응가스 및 반응 부가물을 배출시키는 과정을 수행한다.Subsequently, in the third step, a reaction gas is supplied to induce a reaction with a compound surface group chemisorbed on the wafer surface to deposit an atomic layer. Subsequently, in the fourth step, a purge gas such as an inert gas is injected again to discharge excess reaction gas and reaction adducts.

한편, 1단계∼4단계로 진행하는 1 사이클 동안 반응 챔버 외부에 핫 필라멘트 와이어(Hot Filament Wire)가 있어서, 반응이 진행되는 동안 계속적인 열공급을한다.On the other hand, there is a hot filament wire (Hot Filament Wire) to the outside of the reaction chamber during one cycle proceeding from step 1 to step 4, the continuous heat supply during the reaction.

상술한 과정들을 1 사이클로 하여 반복 진행하므로써, 원하는 두께의 원자층 박막을 증착한다.By repeating the above processes in one cycle, an atomic layer thin film of a desired thickness is deposited.

ALD 방법은 표면 반응 제한 방법을 이용하기 때문에 원자층 단위로 박막의 두께 제어가 가능하고, 하지막의 토폴로지(topology)에 무관하게 증착 가능하여 컨포멀(conformal)하고 균일(uniformity)한 박막을 얻을 수 있다. 뿐만 아니라, 소스가스와 반응가스를 불활성가스로 서로 분리하여 챔버에 공급하기 때문에 화학기상증착법(CVD)에 비하여 가스 위상 반응(gas phase reaction)에 의한 파티클 생성을 억제할 수 있다. 또한, 소스가스와 웨이퍼의 다중 충돌에 의해 소스가스의 사용 효 율을 개선시키고 주기를 줄일 수 있다.Because ALD method uses surface reaction limiting method, it is possible to control the thickness of thin film by atomic layer and to deposit regardless of the topology of the underlying film to obtain conformal and uniform thin film. have. In addition, since the source gas and the reaction gas are separated from each other as an inert gas and supplied to the chamber, particle generation by gas phase reaction can be suppressed as compared with chemical vapor deposition (CVD). In addition, multiple collisions between the source gas and the wafer can improve the use efficiency of the source gas and reduce the period.

본 발명은 100nm 이하의 DRAM 공정에서 필요로하는 유전막인 Al2O3와 HfO2 박막을 단일 반응 용기에서 형성할 때, 저온 공정에 기인하는 누설전류 특성을 개선함으로써, 기존 하부 전극으로 사용되고 있는 폴리실리콘 전극의 사용을 100nm 이하의 공정에 적용할 수 있다.In the present invention, when the Al 2 O 3 and HfO 2 thin films, which are required for the DRAM process of 100 nm or less, are formed in a single reaction vessel, the present invention improves the leakage current characteristics caused by the low temperature process, thereby reducing the poly-electrode. The use of silicon electrodes can be applied to processes up to 100 nm.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 하부 전극 상에 단일 반응 챔버에서 형성된 Al2O3와 HfO2가 적층된 유전막을 형성하므로써, TiN과 같은 금속 전도막 대신 폴리실리콘 전극의 사용을 가능하게 하여 비용 절감을 가능하게 하는 효과가 있다.
The present invention described above forms a dielectric film in which Al 2 O 3 and HfO 2 are stacked in a single reaction chamber on the lower electrode, thereby enabling the use of polysilicon electrodes instead of a metal conductive film such as TiN, thereby enabling cost reduction. It is effective.

Claims (11)

하부 전극용 폴리실리콘막을 형성하는 단계;Forming a polysilicon film for the lower electrode; 상기 폴리실리콘막을 활성화된 산소로 표면 처리하는 단계;Surface treating the polysilicon film with activated oxygen; 상기 표면처리된 폴리실리콘막 상에 HfO2/Al2O3 유전막을 형성하는 단계; 및Forming an HfO 2 / Al 2 O 3 dielectric film on the surface-treated polysilicon film; And 상기 유전막 상에 상부 전극을 형성하는 단계Forming an upper electrode on the dielectric layer 를 포함하는 캐패시터 제조 방법.Capacitor manufacturing method comprising a. 제 1항에 있어서,The method of claim 1, 상기 산소로 표면 처리하는 단계와 상기 유전막을 형성하는 단계는 동일 장비에서 진행되는 캐패시터 제조 방법.Surface treatment with the oxygen and the step of forming the dielectric film is a capacitor manufacturing method performed in the same equipment. 제 1항에 있어서,The method of claim 1, 상기 활성화된 산소로 표면 처리하기 전에 상기 폴리실리콘막의 표면을 질화시키는 단계를 더 포함하는 캐패시터 제조 방법.And nitriding the surface of the polysilicon film prior to surface treatment with the activated oxygen. 제 3항에 있어서,The method of claim 3, wherein 상기 질화는 NH3 또는 N2를 포함하는 분위기에서 급속 열질화로 이루어지는 캐패시터 제조 방법.The nitriding is a capacitor manufacturing method consisting of rapid thermal nitriding in an atmosphere containing NH 3 or N 2 . 제 4항에 있어서,The method of claim 4, wherein 상기 급속 열질화는 800℃∼900℃의 온도로 실시하는 캐패시터 제조 방법.The rapid thermal nitriding is a capacitor manufacturing method carried out at a temperature of 800 ℃ to 900 ℃. 제 3항에 있어서,The method of claim 3, wherein 상기 질화는 플라즈마 처리에 의해 이루어지는 캐패시터 제조 방법.The method of manufacturing a capacitor, wherein the nitriding is performed by a plasma treatment. 제 6항에 있어서,The method of claim 6, 상기 플라즈마 처리는 250℃∼450℃의 온도로 실시하는 캐패시터 제조 방법.The said plasma processing is a capacitor manufacturing method performed at the temperature of 250 degreeC-450 degreeC. 제 1항에 있어서,The method of claim 1, 상기 활성화된 산소로 표면처리하는 단계는,Surface treatment with the activated oxygen, 오존 플라즈마 또는 산소 플라즈마를 사용하는 캐패시터 제조 방법.Capacitor manufacturing method using ozone plasma or oxygen plasma. 제 8항에 있어서,The method of claim 8, 상기 오존 플라즈마는 300℃∼450℃의 온도로 실시하는 캐패시터 제조 방법.The ozone plasma is a capacitor manufacturing method performed at a temperature of 300 ℃ to 450 ℃. 제 8항에 있어서,The method of claim 8, 상기 산소 플라즈마는 300℃∼450℃의 온도로 실시하는 캐패시터 제조 방법.The said oxygen plasma is a capacitor manufacturing method performed at the temperature of 300 degreeC-450 degreeC. 제 1항에 있어서,The method of claim 1, 상기 상부 전극은 P, As가 도핑된 폴리실리콘, TiN, Ru, RuO2, Pt, Ir, IrO2의 그룹에서 선택된 물질을 사용하는 캐패시터 제조 방법.The upper electrode is a capacitor manufacturing method using a material selected from the group of polysilicon doped with P, As, TiN, Ru, RuO 2 , Pt, Ir, IrO 2 .
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