KR20060073131A - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device suitable for preventing defects occurring when C halo ion implantation, the method for manufacturing a semiconductor device of the present invention for this purpose is a predetermined process having a bit line contact junction between the spaced gate pattern Preparing the advanced semiconductor substrate; Applying an SOG to include an upper portion of the gate pattern; Performing a heat treatment to cure a portion of the SOG from a surface to at least the gate pattern upper surface in a depth direction; Forming a mask to open the bitline contact junction; Etching the cured SOG with the mask as an etch barrier; And simultaneously removing the mask and the uncured SOG to open the bit line contact junction.

C-halo, ion implantation mask, SOG, defect

Description

Semiconductor device manufacturing method {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}             

1 is a cross-sectional view and a plan view of a gate pattern according to the prior art,

2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art;

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 device isolation film

33: gate insulating film 34: gate conductive film

35: gate hard mask 36: gate pattern

37: first bonding layer 38: second bonding layer

39: uncured SOG 40: cured SOG

41: photoresist 100: SOG

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a semiconductor device which prevents defects occurring when C-halo ions are implanted.

In recent years, the refresh time is also shortened as the pitch of the semiconductor element becomes smaller in DRAM. In order to increase the refresh time, a method of ion implantation by blocking the storage node contact area with a photoresist and selectively opening only the bit line contact area has been proposed.

As semiconductor devices become highly integrated, each cell becomes finer and the internal electric field strength increases. This increase in electric field strength causes a hot-carrier effect in which the carrier of the channel region is accelerated and injected into the gate oxide layer in the depletion layer near the drain during operation of the device. The carrier injected into the gate oxide film generates a level at the interface between the semiconductor substrate and the gate oxide film, thereby changing the threshold voltage (V _TH ) or lowering the mutual conductance, thereby degrading device characteristics. Therefore, in order to reduce the deterioration of device characteristics due to the hot-carrier effect, a structure in which the drain structure is changed such as a lightly doped drain (LDD) or the like should be used.

In order to prevent the punch-through phenomenon caused by the shortening of the channel, fluorine (F), chlorine (Cl), and bromine in the Group 17 element of the periodic table to increase the impurity concentration of the active region of the substrate after the gate formation and before the LDD formation. Halo implantation is carried out using halogen elements such as (Br), iodine (I) and asatin (At).

As the high integration of devices is required, the source / drain formation method of the LDD method also reaches its limit due to the short channel effect. To solve this problem, a halo LDD scheme is introduced.

Meanwhile, in a semiconductor device manufacturing process to which a design rule of 0.1 μm or less is applied, a process such as ion implantation is more difficult than a critical layer forming process.

An example of an ion implantation mask forming process for halo ion implantation is as follows.

After forming a device isolation layer (Isolation) and a gate electrode, which is one of DRAM (Dynamic Random Access Memory) semiconductor device patterns, bromine (Br) or the like is implanted in order to provide electrical characteristics between the fine patterns.

When a design rule of 0.1 μm is applied, a space between the gate electrodes is secured at least about 60 nm. At this time, since the vertical height (Height) of the patterned gate electrode is about 2000 게이트, the height of the gate electrode has a very high step compared to the width of the space.

The photolithography process for forming a halo ion implantation mask uses an exposure apparatus one step lower than the exposure apparatus for forming a gate electrode pattern, which is a critical process on such a step. This is an essential process condition for reducing manufacturing costs. When forming a halo ion implantation mask, the photoresist positioned between the gate electrode patterns requiring ion implantation should be removed through development, and the photoresist should be covered between the gate electrode patterns where ion implantation should be blocked.

However, due to the above step, light is not transmitted in the space (bone) between the deep gate electrodes and remains in the form of a scum even after development, and the remaining scum is a barrier in the halo ion implantation process. Works.

1 is a process cross-sectional view showing a semiconductor device manufacturing method according to the prior art.

As illustrated in FIG. 1, referring to (a), a plurality of device isolation layers 12 are formed on a semiconductor substrate 11, and a plurality of device isolation layers 12 are formed in a vertical direction so that a predetermined region overlaps with an active region A in a horizontal direction. Gate electrode 16 is formed.

Subsequently, referring to cross-sectional view (b) in which (a) is shown in the I-I 'direction, the element isolation film 12 is formed in a predetermined region of the semiconductor substrate 11. The device isolation layer 12 is formed by a local oxide of silocom (LOCOS) method or a shallow trench isolation (STI) method.

Next, a plurality of gate patterns 16 are formed on the active region of the semiconductor substrate 11 defined by the device isolation film 12. In this case, the gate pattern 16 is a pattern stacked in the order of the gate insulating film 13, the gate conductive film 14, and the gate hard mask 15.

In the method of forming the gate pattern 16, first, the gate conductive film 14 and the gate hard mask 15 are stacked on the gate insulating film 13 on the semiconductor substrate 11, and then the gate hard mask. (15) A photoresist (not shown) is applied on the upper surface and patterned by exposure and development to form a gate mask, and the gate mask is etched mask black gate hard mask 15, gate conductive film 14, and gate insulating film. Etch (13).

Next, an ion implantation process using the gate pattern 16 as an ion implantation mask is performed to form first and second junction layers 17 and 18 in the active region of the semiconductor substrate 11. At this time, the first bonding layer 17 of the bonding layer will be connected to the bit line contact, the remaining second bonding layer 18 will be connected to the storage node contact. The first bonding layer 17 and the second bonding layer 18 are formed by ion implantation of arsenic (As) or phosphorus (P) which are N-type impurities.

2A to 2C are cross sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

As shown in FIG. 2A, the device isolation layer 22 is formed in a predetermined region of the semiconductor substrate 21. The device isolation layer 22 may be formed by a local oxide of silocom (LOCOS) method or a shallow trench isolation (STI) method.

Next, a plurality of gate patterns 26 are formed on the active region of the semiconductor substrate 21 defined by the device isolation layer 22. In this case, the gate pattern 26 is a pattern stacked in the order of the gate insulating film 23, the gate conductive film 24, and the gate hard mask 25.

In the method of forming the gate pattern 26, first, the gate conductive film 24 and the gate hard mask 25 are stacked on the gate insulating film 23 on the semiconductor substrate 21, and then the gate hard mask. (25) A photoresist (not shown) is applied on the top and patterned by exposure and development to form a gate mask, and the gate mask is used as an etching mask for the gate hard mask 25, the gate conductive film 24, and the gate insulating film. Etch (23).

Next, an ion implantation process using the gate pattern 26 as an ion implantation mask is performed to form first and second junction layers 27 and 28 in the active region of the semiconductor substrate 21. At this time, the first bonding layer 27 of the bonding layer will be connected to the bit line contact, the remaining second bonding layer 28 will be connected to the storage node contact. The first bonding layer 27 and the second bonding layer 28 are formed by ion implantation of arsenic (As) or phosphorus (P) which are N-type impurities.

Subsequently, as shown in FIG. 2B, a photoresist 29 is applied to the entire surface of the structure including the plurality of gate patterns 26. This photoresist 29 is for forming a C-halo mask.

As shown in FIG. 2C, the photoresist 29a formed on the entire surface of the structure is formed to open the first junction layer 27 to be connected to the bit line contact and to cover the second junction layer 28 to be connected to the storage node contact. . This photoresist 29a is referred to as a C-halo mask for halo ion implantation in the cell region. That is, the C-halo step is performed only with the photoresist 29a.

Next, halo ion implantation using a C-halo mask as an ion implantation mask is performed to dope impurities into the first bonding layer 27 to which the bit line contacts are to be connected.

As described above, according to the related art, the first junction layer 27 to which the bit line contacts are connected to the second junction layer 28 that is connected to the storage node of the capacitor to be connected to the storage node of the capacitor without applying halo ion implantation is improved. Only halo ion implantation is applied.

As described above, the prior art has a simple process advantage when using a photoresist using a C-halo mask.

However, when the photoresist strips do not sufficiently reach the bottom of the deep valley of exposure energy, all of the photoresist residues 30 generated are not removed, which prevents subsequent C-halo ion implantation, resulting in transistor characteristics. There remains a problem of deterioration and deterioration of the refresh characteristics.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a semiconductor device suitable for preventing defects occurring during C halo ion implantation.

The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of preparing a semiconductor substrate subjected to a predetermined process having a bit line contact junction between the gate pattern spaced apart, applying a SOG to include an upper portion of the gate pattern, Performing heat treatment to cure a portion of the SOG from the surface to the at least the upper surface of the gate pattern in a depth direction, forming a mask for opening the bit line contact junction, and etching the mask into an etch barrier. Etching and removing the mask and the uncured SOG simultaneously to open the bit line contact junction.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

3A through 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 3A, the device isolation layer 32 is formed in a predetermined region of the semiconductor substrate 31. The device isolation layer 32 may be formed by a local oxide of silocom (LOCOS) method or a shallow trench isolation (STI) method.

Next, a plurality of gate patterns 36 are formed on the active region of the semiconductor substrate 31 defined by the device isolation layer 32. In this case, the gate pattern 36 is a pattern stacked in the order of the gate insulating film 33, the gate conductive film 34, and the gate hard mask 35.

In the method of forming the gate pattern 36, first, the gate conductive film 34 and the gate hard mask 35 are stacked on the gate insulating film 33 on the semiconductor substrate 31, and then the gate hard mask. (35) A photoresist (not shown) is applied on the upper surface and patterned by exposure and development to form a gate mask, and the gate mask is used as an etching mask for the gate hard mask 35, the gate conductive film 34, and the gate insulating film. Etch (33).

Next, an ion implantation process using the gate pattern 36 as an ion implantation mask is performed to form first and second junction layers 37 and 38 in the active region of the semiconductor substrate 31. At this time, the first bonding layer 37 of the bonding layer will be connected to the bit line contact, the remaining second bonding layer 38 will be connected to the storage node contact. The first bonding layer 37 and the second bonding layer 38 are formed by ion implantation of arsenic (As) or phosphorus (P) which are N-type impurities.                     

Subsequently, as shown in FIG. 3B, before forming the C-halo mask, the inorganic SOG 100 is applied until the valleys between the gate electrode patterns 36 on the semiconductor substrate 31 are filled. In this case, the inorganic spin on glass (SOG) is an inorganic oxide film of the HSG series,

In addition, an inorganic SOG-based FOX, T-12, or the like may be used. In addition to the organic SOG material or the SOG-based material, a material such as APL having a good wet etching rate may be used.

Next, as shown in FIG. 3C, annealing or plasma treatment is performed to cure the SOG 100 over the entire semiconductor substrate 31. The annealing step is preferably performed at least 10 minutes in a nitrogen atmosphere of 600 ° C to 750 ° C in order to completely separate the bonds of the SOG (100) Si-H and to obtain an oxide film. Or N ₂ / O ₂ plasma treatment.

Subsequently, after annealing, curing of the SOG 39 inside the gate pattern 36 does not occur, and curing of the SOG 40 above the gate pattern 36 occurs. The cured SOG 40 has an etch rate that is almost similar to that of a normal oxide, and the uncured SOG 39 exists as a very fast wet etch rate.

Subsequently, as shown in FIG. 3C, a photoresist 41 is applied to the entire structure including the cured SOG 40. At this time, the photoresist 41 is applicable to all photoresists including i-line and DUV (KrF, ArF).

Next, as shown in FIG. 3D, the photoresist 41 is patterned by exposure and development to open the first junction layer 37 to which the bit line contacts are to be opened, and the second junction layer to which the storyboard contact is to be connected. A photoresist pattern covering 38 is formed. This patterned photoresist 41 is referred to as a "C _halo mask" for the halo ion implantation in the cell region.

Since the hardened SOG 40 is positioned under the photoresist 41 during the exposure process for forming the mask, the exposure energy reaches the photoresist 41 sufficiently to allow sufficient exposure.

Subsequently, as illustrated in FIG. 3E, the SOG 40 cured with the C halo mask is etched. At this time, the hardened SOG 40 is generally removed by wet etching using hydrofluoric acid solution (HF) or BOE.

Subsequently, as shown in FIG. 3F, the photoresist pattern 41 and the uncured SOG 39a are simultaneously removed with an aqueous KOH solution to completely open the first bonding layer 37. Both the photoresist pattern 41 and the uncured SOG 39 are removed. Residues do not remain in the opened first bonding layer 37. Subsequently, halo ion implantation is performed on the entire substrate.

As described above, the present invention can prevent the C-halo ion implantation defect caused by the photoresist residues by using inorganic SOG, in which a photoresist pattern is possible instead of the photoresist and the wet etch rate is high, so that no residue remains during wet etching. .

Therefore, although the present invention and the technical idea have been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, the photoresist residue used as a mask during the halo ion implantation is not completely removed from the bit line contact hole, thereby curing the SOG-based oxide film to prevent the residue from being generated. .

In addition, the present invention has the effect of increasing the process margin by improving the process stability by fundamentally preventing voids and residues of the photoresist by stably proceeding halo ion implantation to the bonding layer.

In addition, the present invention has the effect of ensuring a stable refresh time, improve the characteristics and yield of the device by proceeding halo ion implantation to the bonding layer stably.

Claims (8)

Preparing a semiconductor substrate having a predetermined process having a bit line contact junction between the spaced gate patterns; Applying an SOG to include an upper portion of the gate pattern; Performing a heat treatment to cure a portion of the SOG from a surface to at least the gate pattern upper surface in a depth direction; Forming a mask to open the bitline contact junction; Etching the cured SOG with the mask as an etch barrier; And Simultaneously removing the mask and the uncured SOG to open the bitline contact junction Semiconductor device manufacturing method comprising a. The method of claim 1, The SOG is a semiconductor device manufacturing method using inorganic SOG. The method of claim 1, The SOG is a semiconductor device manufacturing method using organic SOG. The method of claim 1, A method of manufacturing a semiconductor device to anneal for 10 minutes at a temperature of 600 ℃ to 750 ℃ to cure a portion of the SOG. The method of claim 1, A semiconductor device manufacturing method comprising N ₂ or O ₂ plasma treatment so that a portion of the SOG is cured. The method of claim 1, And removing the photoresist and the uncured SOG simultaneously with a KOH solution. The method of claim 1, The hardened SOG is removed by wet etching. The method of claim 7, wherein The hardened SOG is a semiconductor device manufacturing method using a hydrofluoric acid solution (HF) or BOE.

Images