KR20060062755A - Manufacturing method of a capacitor - Google Patents

Manufacturing method of a capacitor Download PDF

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KR20060062755A
KR20060062755A KR1020040101705A KR20040101705A KR20060062755A KR 20060062755 A KR20060062755 A KR 20060062755A KR 1020040101705 A KR1020040101705 A KR 1020040101705A KR 20040101705 A KR20040101705 A KR 20040101705A KR 20060062755 A KR20060062755 A KR 20060062755A
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storage node
capacitor
metal
polysilicon
manufacturing
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KR1020040101705A
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KR101174022B1 (en
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박상혁
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 스토리지 노드를 Ti 실리사이드화 공정으로 분리하여 스토리지 노드의 특성 열화를 방지하고 세정공정을 용이하게 하는 것을 목적으로 한다.An object of the present invention is to separate the storage node into a Ti silicide process to prevent deterioration of characteristics of the storage node and to facilitate the cleaning process.

본 발명에 의한 커패시터 제조 방법은 커패시터가 형성될 홀에 폴리 실리콘 재질의 스토리지 노드를 형성하는 단계, 홀의 전면에 소정의 금속을 증착하는 단계, 금속과 스토리지 노드가 인접하는 부분을 반응시켜 금속을 실리사이드화 하는 단계 및 금속 중 실리사이드화 되지 않은 부분을 식각하여 이웃하는 홀의 스토리지 노드가 분리되도록 하는 단계를 포함한다.In the capacitor manufacturing method according to the present invention, forming a storage node made of polysilicon in a hole where a capacitor is to be formed, depositing a predetermined metal on the front surface of the hole, and reacting a portion of the metal and the storage node adjacent to silicide. And etching the unsilicided portion of the metal to separate the storage nodes in neighboring holes.

커패시터, Salicide, 습식Capacitors, Salicide, Wet

Description

커패시터의 제조 방법{Manufacturing Method of a Capacitor}Manufacturing Method of a Capacitor

도1a 내지 도1c는 종래 기술에 의한 커패시터 제조 방법을 나타내는 공정도.1A to 1C are process drawings showing a capacitor manufacturing method according to the prior art.

도2a 내지 도2f는 본 발명에 의한 커패시터 제조 방법을 나타내는 공정도.Figures 2a to 2f is a process diagram showing a capacitor manufacturing method according to the present invention.

본 발명은 커패시터 제조 방법에 관한 것으로서 특히 컵(cup) 형태의 커패시터 제조 방법에 있어서 스토리지 노드를 분리하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor, and more particularly to a technique for separating storage nodes in a cup manufacturing method of a capacitor.

도1a 내지 도1c는 종래 기술에 의한 커패시터를 제조하는 방법을 나타낸다.1A-1C show a method of manufacturing a capacitor according to the prior art.

먼저 도1a는 층간 절연막(1)에 스토리지 노드 플러그(2)를 형성하고, 그 상부에 스토리지 노드 정지 니트(NIT)(3), 캡 산화막(4)를 순차적으로 적층하고 커패시터 홀을 형성한 후 스토리지 노드용 하부 전극(5)을 적층하고 그 내부에 스토리지 노드 PR(6)을 매립한 모양을 나타낸다.First, FIG. 1A illustrates the formation of the storage node plug 2 on the interlayer insulating film 1, sequentially stacking the storage node stop knits (NIT) 3 and the cap oxide film 4 on top of each other, and forming capacitor holes. The lower electrode 5 for the storage node is stacked and the storage node PR 6 is embedded therein.

이 상태에서 스토리지 노드용 하부 전극(5)를 분리하기 위하여 금속 드라이 에치 백(metal dry etch back)을 실시한다. 이 경우 금속 에치는 PR 과의 선택비가 좋지 않아 식각이 잘 안되는 문제가 있다. 이로 인하여 도1b의 A와 같이 스토리지 노드 PR(5)의 손실이 커지고 그 결과 도1b의 B와 같이 홀 내부에서 노출되는 금속 면적이 증가하게 된다.In this state, a metal dry etch back is performed to separate the lower electrode 5 for the storage node. In this case, the metal etch has a problem that the etching ratio is not good because the selectivity with the PR. As a result, the loss of the storage node PR 5 is increased as in A of FIG. 1B, and as a result, the metal area exposed in the hole as in B of FIG. 1B is increased.

마지막으로 도1c와 같이 스토리지 노드 PR(6)을 제거하고 세정을 수행한다. 이때 PR제거는 산소 플라스마 방식을 사용하는데 이로 인하여 금속 전극(5)의 산화가 유발되어 전기적인 특성이 열화되는 문제가 발생한다. 더구나 금속 전극(5)이 금속인 관계로 세정 작업을 강하게 진행하는 경우 금속 자체가 식각될 우려가 있어서 세정 공정이 용이하지 않은 문제가 있다.Finally, the storage node PR 6 is removed and cleaned as shown in FIG. 1C. At this time, the PR removal uses an oxygen plasma method, which causes the oxidation of the metal electrode 5, resulting in a problem of deterioration of electrical characteristics. In addition, when the cleaning operation is strongly performed since the metal electrode 5 is metal, there is a fear that the metal itself may be etched, and thus the cleaning process is not easy.

이상과 같이 종래의 MIM 커패시터 제조 방법에서는 스토리지 노드를 분리하는데 금속 드라이 에치 백 방식을 사용함으로써 금속 전극의 특성 열화와 같은 여러가지 부작용이 발생하는 문제가 있었다.As described above, the conventional MIM capacitor manufacturing method has a problem in that various side effects such as deterioration of characteristics of the metal electrode are generated by using the metal dry etch back method to separate the storage nodes.

본 발명은 이러한 종래 기술의 문제를 해결하고자 스토리지 노드 분리시 실리사이드화 공정을 채택한 커패시터 제조 방법을 제공하는 것을 목적으로 한다.An object of the present invention is to provide a capacitor manufacturing method employing a silicidation process when the storage node is separated to solve the problems of the prior art.

본 발명에 의한 커패시터 제조 방법은 커패시터가 형성될 홀에 폴리 실리콘 재질의 스토리지 노드를 형성하는 단계, 홀의 전면에 소정의 금속을 증착하는 단계, 금속과 스토리지 노드가 인접하는 부분을 반응시켜 금속을 실리사이드화 하는 단계 및 금속 중 실리사이드화 되지 않은 부분을 식각하여 이웃하는 홀의 스토리지 노드가 분리되도록 하는 단계를 포함한다.In the capacitor manufacturing method according to the present invention, forming a storage node made of polysilicon in a hole where a capacitor is to be formed, depositing a predetermined metal on the front surface of the hole, and reacting a portion of the metal and the storage node adjacent to silicide. And etching the unsilicided portion of the metal to separate the storage nodes in neighboring holes.

이하에서는 첨부한 도면을 참조하여 본 발명의 실시예에 대해서 상세히 설명한다. Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.                     

도2a내지 도2c는 종래 기술에 의한 MIM 커패시터 제조 방법과 유사하다. 2A to 2C are similar to the MIM capacitor manufacturing method according to the prior art.

먼저 도2a와 같이 층간 절연막(10)에 스토리지 노드 플러그(20)를 형성하고, 그 상부에 스토리지 노드 정지 니트(NIT)(30), 캡 산화막(40)을 순차적으로 증착하고, 커패시터 홀을 형성한 후 폴리 실리콘(50)을 증착하고 그 내부에 스토리지 노드 PR(60)을 매립한다. First, as shown in FIG. 2A, the storage node plug 20 is formed on the interlayer insulating layer 10, and the storage node stop knit (NIT) 30 and the cap oxide layer 40 are sequentially deposited on the interlayer insulating layer 10 to form a capacitor hole. Then, polysilicon 50 is deposited and the storage node PR 60 is embedded therein.

본 발명은 하부 전극을 위하여 금속을 증착하는 대신에 폴리 실리콘을 증착하는 점에 있어서 종래 기술과 상이하다.The present invention differs from the prior art in that it deposits polysilicon instead of depositing metal for the bottom electrode.

이 상태에서 도2b와 같이 스토리지 노드를 분리하기 위하여 폴리 실리콘 드라이 에치 백(dry etch back)을 실시한 후, 도2c와 같이 스토리지 노드 PR(60)을 제거하고 세정을 수행한다.In this state, a polysilicon dry etch back is performed to separate the storage node as shown in FIG. 2B, and then the storage node PR 60 is removed and cleaned as shown in FIG. 2C.

스토리지 노드가 분리된 후 도2d와 같이 전면에 Ti 막(60)을 증착한다.After the storage node is separated, the Ti film 60 is deposited on the front surface as shown in FIG. 2D.

다음으로 도2e와 같이 열처리 공정을 진행하여 적층된 Ti 막 중 폴리 실리콘(50)과 인접한 부분이 Ti 실리사이드(70)로 변화되도록 한다. 이때 캡 산화막(40)과 인접한 Ti 막(60)은 결정화되지 않고 Ti 상태로 존재하게 된다.Next, a heat treatment process is performed as shown in FIG. 2E so that the portion adjacent to the polysilicon 50 in the stacked Ti films is changed to the Ti silicide 70. At this time, the Ti film 60 adjacent to the cap oxide film 40 is not crystallized and exists in the Ti state.

최종적으로 세정를 실시하면 Ti 막(60)은 녹아 없어지고 Ti 실리사이드(70)는 세정 물질에 반응하지 않아 본래의 형태를 유지하므로 스토리지 노드를 분리할 수 있다. 이때 사용되는 세정 물질로는 NH4OH/H2O2/H2O 등을 사용할 수 있다.Finally, the Ti film 60 is melted away and the Ti silicide 70 does not react to the cleaning material and maintains its original shape, thereby separating the storage node. NH 4 OH / H 2 O 2 / H 2 O and the like may be used as the cleaning material used at this time.

본 발명을 적용함으로써 PR과의 선택비가 우수하고 식각특성이 좋은 폴리 실리콘을 이용하여 스토리지 노드 구조를 형성함으로써 스토리지 노드의 높이 손실을 줄일 수 있으며, 세정 물질에 반응하지 않는 Ti 실리사이드의 성질로 인하여 세정 공정을 보다 용이하게 진행할 수 있다. 이로써 스토리지 노드의 높이 손실을 최소화 하면서 스토리지 노드의 분리가 가능해지는 효과가 있다.The present invention can reduce the height loss of the storage node by forming the storage node structure using polysilicon having excellent selectivity with PR and good etching characteristics, and can be cleaned due to the nature of Ti silicide that does not react with the cleaning material. The process can be carried out more easily. As a result, the storage node can be separated while minimizing the height loss of the storage node.

Claims (4)

(a) 커패시터가 형성될 홀에 폴리 실리콘 재질의 스토리지 노드를 형성하는 단계;(a) forming a storage node made of polysilicon in the hole where the capacitor is to be formed; (b) 상기 홀의 전면에 소정의 금속을 증착하는 단계;(b) depositing a predetermined metal on the front surface of the hole; (c) 상기 금속과 상기 스토리지 노드가 인접하는 부분을 반응시켜 상기 금속을 실리사이드화 하는 단계; 및(c) reacting the portion of the metal with an adjacent portion of the storage node to suicide the metal; And (d) 상기 금속 중 실리사이드화 되지 않은 부분을 식각하여 이웃하는 홀의 스토리지 노드가 분리되도록 하는 단계(d) etching the unsilicided portion of the metal to separate storage nodes in neighboring holes 를 포함하는 커패시터 제조 방법.Capacitor manufacturing method comprising a. 제1항에 있어서, 상기 (a) 단계는The method of claim 1, wherein step (a) 층간 절연막에 다수 개의 스토리지 노드 플러그를 생성하는 공정;Generating a plurality of storage node plugs in the interlayer insulating film; 상기 층간 절연막의 상부에 스토리지 노드 정지 니트 및 캡 산화막을 증착하는 공정;Depositing a storage node stop knit and cap oxide film over the interlayer insulating film; 상기 스토리지 노드 정지 니트 및 캡 산화막을 식각하여 다수 개의 커패시터 홀을 형성하는 공정;Etching the storage node stop knit and cap oxide layer to form a plurality of capacitor holes; 상기 다수개의 커패시터 홀에 폴리 실리콘 재질의 스토리지 노드를 증착하는 공정; 및Depositing a storage node made of polysilicon in the plurality of capacitor holes; And 상기 폴리 실리콘을 식각하여 이웃하는 커패시터 홀간의 스토리지 노드를 분 리하는 공정Etching the polysilicon to separate storage nodes between adjacent capacitor holes 을 포함하는 커패시터 제조 방법.Capacitor manufacturing method comprising a. 제1항에 있어서, 상기 소정의 금속은 Ti인 것을 특징으로 하는 커패시터 제조 방법.The method of claim 1 wherein the predetermined metal is Ti. 제1항에 있어서, 상기 (d) 단계는The method of claim 1, wherein step (d) NH4OH/H2O2/H2O를 이용한 습식 공정으로 수행되는 것을 특징으로 하는 커패시터 제조 방법.Method for producing a capacitor, characterized in that carried out in a wet process using NH4OH / H2O2 / H2O.
KR1020040101705A 2004-12-06 2004-12-06 Manufacturing Method of a Capacitor KR101174022B1 (en)

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KR100379528B1 (en) * 2000-12-21 2003-04-10 주식회사 하이닉스반도체 Capacitor and method for fabricating the same
KR20030057604A (en) * 2001-12-29 2003-07-07 주식회사 하이닉스반도체 Method for fabricating capacitor
KR20040057635A (en) * 2002-12-26 2004-07-02 주식회사 하이닉스반도체 method for fabricating storage node electrodes of capacitor
KR20040059966A (en) * 2002-12-30 2004-07-06 주식회사 하이닉스반도체 Method for fabricating capacitor in semiconductor device

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