JP2007134435A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of forming a stack cell capacitor which prevents the bottom of a stack cell from becoming a square shape, prevents a liner nitride film from being side-etched, prevents the reduction in coverage of a capacitor electrode layer and a capacitor insulation film layer, and also prevents the formation of weak spots where an electric field concentrates. <P>SOLUTION: Prior to forming the bottom electrode 121 of the capacitor, a side wall 119 having a positive curvature in the upper part while having a negative curvature in the lower part, is formed between the bottom electrode of the capacitor and the stack cell, using a silicon nitride film deposited by atomic layer deposition wherein a dry etching rate becomes lower in the depthwise direction. The bottom of the stack cell is thereby prevented from becoming a square shape, and the liner nitride film 114 is not side-etched, and since there are no formation of weak spots where an electric field concentrates, the reliability of the capacitor is improved. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for improving the electrical performance of a capacitor element such as a DRAM, for example, and more particularly to a semiconductor device with an improved structure near a capacitor lower electrode and a method for manufacturing the same.

  In recent years, with the miniaturization of the processing dimensions of semiconductor elements, DRAM memory cells having charge storage capacitive elements have been highly integrated, and the memory cell area has been reduced.

  Generally, a DRAM memory cell forms a capacitor dielectric film between a lower electrode and an upper electrode, and the capacitor capacitance is proportional to the effective capacitor area composed of two electrodes facing the dielectric constant of the capacitor dielectric film, It is inversely proportional to the thickness of the capacitor dielectric film.

When the capacitor memory cell area is reduced, it is difficult to secure the capacitor capacity. For example, when the design rule is the 130 nm generation, the capacitor cell shape is a three-dimensional shape called a cylinder type or a concave type, and the lower electrode HSG (Hemi Spherical Grain) technology was used to increase the effective capacitor area. Further, the capacitor dielectric film is made of tantalum oxide (Ta ₂ O ₅ ) or BST (BaSrTiO ₃ ), which is a high dielectric constant material, to realize a desired capacitor capacity.

  Since the design rule is 90nm generation and later, the process temperature is lowered and the cell area is further reduced, so that HSG technology is rarely used, and MIM (titanium nitride (TiN) or ruthenium (Ru) is used for the upper and lower electrodes. Metal-Insulator-Metal) Capacitor structure has become mainstream.

  An example of the MIM capacitor formation process will be described with reference to FIGS. The DRAM cell shown in FIGS. 28 to 34 includes a capacitor element having a stack structure.

  First, a silicon nitride film 52 and a silicon oxide film 53 are deposited on an insulating film on which a tungsten plug 51 is formed following the diffusion layer of the semiconductor substrate 50 (FIG. 28). Next, a photoresist (not shown) is applied, and the photoresist is opened by exposing a place where a stack cell is to be formed. Then, the silicon oxide film 53 is dry-etched using a gas having selectivity between the silicon oxide film and the silicon nitride film. Subsequently, the stack cell 54 is formed by dry etching the silicon nitride film 52 so that the tungsten plug surface is exposed (FIG. 29).

  Next, 20 nm of TiN55 is deposited using, for example, tetradimethylamino titanium (TDMAT) (FIG. 30). Thereafter, a photoresist is applied to the entire surface and the entire surface is exposed to embed the inside of the cell with the photoresist 56 (FIG. 31). Further, TiN other than the inside of the cell is removed by dry etching on the entire surface, and then the resist remaining inside the cell is removed by washing to form a capacitor lower electrode 57 (FIG. 32).

  Next, a capacitor dielectric film 58, for example, aluminum hafnium oxide (AlHfO) is formed by atomic layer deposition (ALD: Atomic Layer Deposition), and then an upper electrode 59 is formed using TiN (FIG. 33).

Finally, the upper electrode 59 and the capacitor dielectric film 58 in the peripheral circuit region are removed by lithography and etching techniques to form a DRAM capacitor having an MIM structure (FIG. 34).
JP 2000-156379 A

  In the above prior art, as shown in FIG. 35, when the bottom of the stack cell becomes square due to dry etching at the time of forming the stack cell, the capacitor lower electrode 57 also has an acute shape, and then the capacitor dielectric film 58 and the upper electrode 59 Since the apex portion is also formed in FIG. 3, the electric field concentration portion such as the corner portion 61 is formed, and the capacitor leakage current is increased as compared with the case where the planar electrode is formed.

  In addition, after the stack cell is formed, the outer surface of the tungsten plug is cleaned using argon sputtering or nitrogen trifluoride, or by repeating cleaning using hydrofluoric acid for the purpose of removing byproducts during dry etching. As shown in FIG. 36, side etch 62 occurs in liner nitride film 52. As shown in FIG. 37, if the capacitor lower electrode 57 or the like is formed while side etching occurs, the coverage deteriorates and the electric field concentration portion is generated, leading to deterioration of reliability.

  Accordingly, an object of the present invention is to improve the coverage of the capacitor formation film at the bottom of the capacitor cell, reduce the electric field concentration, and improve the reliability of the capacitor in a semiconductor device having a columnar or cylindrical capacitor called a stack cell or a cylinder cell. It is an object to provide an improved semiconductor device and a manufacturing method thereof.

  In order to achieve the above object, a semiconductor device according to claim 1 of the present invention includes an interlayer insulating film provided on a semiconductor substrate, a stack cell selectively opening the interlayer insulating film, and an inside of the stack cell. A semiconductor device having a stack type capacitor composed of a capacitor lower electrode, a capacitor dielectric film and a capacitor upper electrode provided in order, the upper portion having a positive curvature between the capacitor lower electrode and the side wall of the stack cell, A sidewall having a negative curvature at the bottom was formed.

  According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the sidewall is made of a silicon nitride film, and the nitrogen / silicon ratio in the depth direction of the film increases continuously or stepwise.

  According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the nitrogen / silicon ratio changes from 1.0 to 1.25 with respect to the depth direction of the film.

  5. The method of manufacturing a semiconductor device according to claim 4, wherein a step of forming an interlayer insulating film on a semiconductor substrate, a step of selectively opening the interlayer insulating film to form a stack cell, and the stack cell are formed. Forming a silicon nitride film on the semiconductor substrate; dry etching the silicon nitride film to form a sidewall on the sidewall of the stack cell; and an interior of the stack cell in which the sidewall is formed. Forming a capacitor lower electrode, a capacitor dielectric film, and a capacitor upper electrode in order, wherein the silicon nitride film has a nitrogen source gas purge time ratio with respect to the silicon source gas for each cycle using atomic layer deposition. Films are formed continuously or stepwise.

  The semiconductor device manufacturing method according to claim 5 is the semiconductor device manufacturing method according to claim 4, wherein the purge time ratio is changed from 10 times to 1/2 times.

  The method of manufacturing a semiconductor device according to claim 6 is the method of manufacturing a semiconductor device according to claim 5, wherein the silicon nitride film is etched by increasing a nitrogen / silicon ratio in a depth direction. Dry etching is performed to reduce the rate from 10 times to 1 time in the depth direction to give a negative curvature to the lower portion of the sidewall.

  The method of manufacturing a semiconductor device according to claim 7, further comprising a step of forming a liner nitride film between the semiconductor substrate and the interlayer insulating film in the method of manufacturing a semiconductor device according to claim 4, 5 or 6. In the step of forming the sidewall, the silicon nitride film is etched and the liner nitride film is continuously etched.

  9. The method for manufacturing a semiconductor device according to claim 8, wherein a step of forming an interlayer insulating film on a semiconductor substrate, a step of selectively opening the interlayer insulating film to form a stack cell, and the stack cell are formed. Forming a laminated film composed of a lower layer film and an upper layer film on the semiconductor substrate; dry etching the laminated film to form a sidewall made of the lower layer film on a side wall of the stack cell; and Forming a capacitor lower electrode, a capacitor dielectric film and a capacitor upper electrode in order inside the stack cell in which a wall is formed, and in the step of forming the stacked film, the upper layer film is formed with respect to the dry etching. It is a low resistance layer, and the lower layer film is a high resistance layer.

  The method for manufacturing a semiconductor device according to claim 9 is the method for manufacturing a semiconductor device according to claim 8, wherein the step of forming the stacked film includes a step of forming a silicon film to be the lower layer film, and a step of forming the silicon film. Forming a silicon oxide film to be the upper film by plasma oxidizing the surface, and the step of forming the sidewall is performed by dry etching with a silicon oxide film / silicon film selection ratio of 10 times or more. The negative curvature is given to the lower part of the sidewall.

  The method for manufacturing a semiconductor device according to claim 10 is the method for manufacturing a semiconductor device according to claim 8, wherein the step of forming the laminated film includes a step of forming a silicon nitride film to be the lower layer film using CVD. And a step of forming a silicon oxide film to be the upper layer film. The step of forming the sidewall is performed by performing dry etching with a silicon oxide film / silicon nitride film selection ratio of 10 times or more and performing the side etching. Give negative curvature at the bottom of the wall.

  According to the semiconductor device of claim 1 of the present invention, between the capacitor lower electrode and the side wall of the stack cell, the sidewall having a shape in which the upper portion has a positive curvature and the lower portion has a negative curvature, The sidewall shape is rounded at the bottom of the capacitor cell. As a result, the corner of the capacitor lower electrode is not formed, the electric field concentration at the bottom of the capacitor is mitigated, the capacitor cell leakage current is reduced, and the dielectric breakdown of the capacitor dielectric film is improved. it can. Further, by forming a sidewall on the side wall of the stack cell, it is possible to prevent side etch due to cleaning or the like from occurring in a liner nitride film or the like formed between the semiconductor substrate for forming the cell and the interlayer insulating film. For this reason, the coverage of the capacitor forming film at the bottom of the capacitor cell can be improved.

  According to the second aspect of the present invention, the sidewall is made of a silicon nitride film, and the nitrogen / silicon ratio with respect to the depth direction of the film increases continuously or stepwise, so that the dry etching rate decreases with respect to the depth direction. Nitride film can be formed, and the etching rate is different with respect to the depth direction, so the upper part can be rounded with a positive curvature and the lower part can be rounded with a negative curvature. it can.

  According to the third aspect of the present invention, since the nitrogen / silicon ratio changes from 1.0 to 1.25 with respect to the depth direction of the film, the nitride film has a dry etching rate that decreases with respect to the depth direction of the film.

  According to the method of manufacturing a semiconductor device according to claim 4 of the present invention, the silicon nitride film uses atomic layer deposition to continuously or stepwise change the purge time ratio of the nitrogen source gas to the silicon source gas for each cycle. Therefore, the sidewalls can be formed using silicon nitride films having different etching rates in the depth direction. That is, since the number of silicon-nitrogen bonds in each layer is different, a nitride film whose dry etching rate changes stepwise or continuously is formed. Therefore, the sidewall of the capacitor cell sidewall is formed by performing dry etching with high anisotropy after the above-described nitride film is formed. The structure is such that corners are not formed. For this reason, electric field concentration at the bottom of the capacitor cell can be relaxed, and reliability such as reduction of capacitor cell leakage current and prevention of dielectric breakdown of the capacitor dielectric film can be improved.

  In claim 5, since the purge time ratio is changed from 10 times to 1/2, the ratio of nitrogen / silicon in the thin layer formed in one cycle is changed from about 1.0 to 1.25. The nitride film has a dry etching rate that decreases with respect to the depth direction of the film.

  According to the sixth aspect of the present invention, the silicon nitride film is dry-etched by increasing the nitrogen / silicon ratio in the depth direction so that the etching rate of the film is reduced from 10 to 1 times in the depth direction. Thus, a negative curvature is given to the lower portion of the sidewall, so that the electric field concentration at the bottom of the capacitor is alleviated.

  According to a seventh aspect of the present invention, the method further includes a step of forming a liner nitride film between the semiconductor substrate and the interlayer insulating film. In the step of forming the sidewall, the silicon nitride film is etched and the liner nitride film is continuously etched. When forming the stack cell, a sidewall having a negative curvature at the bottom can be formed on the side wall of the stack cell without etching the liner nitride film after etching the interlayer insulating film. In addition, since the side wall can be formed without etching the liner nitride film after etching the interlayer insulating film at the time of forming the stack cell in this way, side etching due to cleaning of the liner nitride film is prevented, and the capacitor The coverage of the capacitor formation film at the cell bottom can be improved.

  According to the method for manufacturing a semiconductor device according to claim 8 of the present invention, a step of forming a laminated film composed of a lower layer film and an upper layer film on the semiconductor substrate on which the stack cell is formed, and stacking by dry etching the laminated film Including a step of forming a side wall made of a lower layer film on the side wall of the cell, and in the step of forming a laminated film, the upper layer film is a low resistance layer and the lower layer film is a high resistance layer against dry etching. A sidewall with negative curvature at the bottom can be formed on the side wall of the stack cell, reducing electric field concentration at the bottom of the capacitor cell, reducing capacitor cell leakage current, and preventing dielectric breakdown of the capacitor dielectric film Can be improved.

  According to a ninth aspect of the present invention, the step of forming the laminated film includes a step of forming a silicon film to be a lower layer film, and a step of forming a silicon oxide film to be an upper layer film by plasma oxidizing the surface of the silicon film. In the step of forming the wall, dry etching is performed so that the selection ratio of silicon oxide film / silicon film is 10 times or more to give a negative curvature to the lower portion of the side wall. Becomes a high etching resistance layer, and a sidewall having a negative curvature at the bottom can be formed on the side wall of the stack cell.

  According to a tenth aspect of the present invention, the step of forming the laminated film includes a step of forming a silicon nitride film to be a lower layer film and a step of forming a silicon oxide film to be an upper layer film by using CVD to form a sidewall. In this step, dry etching is performed so that the selection ratio of silicon oxide film / silicon nitride film is 10 times or more and negative curvature is given to the lower portion of the sidewall. Therefore, a silicon nitride film and a low resistance layer as a high resistance layer against dry etching By using a silicon oxide film, a sidewall having a negative curvature at the bottom can be formed on the side wall of the stack cell.

Hereinafter, embodiments of the present invention will be described in detail.
(First embodiment)
A first embodiment of the present invention will be described with reference to FIGS.

  As shown in FIG. 11, an interlayer insulating film 115 provided on a semiconductor substrate 101, a stack cell 116 selectively opening the interlayer insulating film 115, a capacitor lower electrode 121 provided in order inside the stack cell 116, a capacitor A stack type capacitor including a dielectric film 122 and a capacitor upper electrode 123 is provided. Further, a sidewall 119 is formed between the capacitor lower electrode 121 and the stack cell side wall, having a shape in which the upper portion has a positive curvature and the lower portion has a negative curvature.

  A method for manufacturing the semiconductor device having the above structure will be described. First, as shown in FIG. 1A, an element isolation 102 is formed on the surface of a semiconductor substrate 101 such as a silicon substrate to form an element active region. Next, well formation (not shown), a gate insulating film 103, a gate electrode 104, sidewalls 105, and source / drain regions (not shown) are formed.

  Next, as shown in FIG. 1B, two layers of metal films 106 and 107 are sequentially deposited. Preferably, the lower metal film 106 is nickel (Ni), and the upper metal is titanium nitride (TiN).

  Subsequently, first annealing is performed at 250 to 350 degrees to react the Ni film 106 and the silicon substrate 101. As a result, as shown in FIG. 2A, a compound of a semiconductor and a metal (silicide) 108 is formed on the surface of the silicon substrate 101.

  Thereafter, the unreacted portion of the Ni film 106 and the TiN film 107 are removed, and second annealing is performed at about 350 to 550 degrees to form a nickel silicide (NiSi) layer 108.

NiSi has poor heat resistance, and there is a possibility of phase transition from low-resistance NiSi to high-resistance NiSi ₂ even when heat treatment is performed at a phase transition temperature of 500 ° C. or less. Therefore, it is necessary to lower the temperature after the silicide process to 400 ° C. or lower.

  Next, as shown in FIG. 2B, after a liner nitride film 109 serving as a dry etch stopper for forming a contact hole and a silicon oxide film 110 serving as an interlayer insulating film are formed, CMP (Chemical Mechanical Polish) is performed. ).

  Here, the nitride film used in the dry etch stopper is preferably formed at 350 ° to 450 ° using atomic layer deposition, and the interlayer insulating film is also formed at a high density plasma CVD in the range of 350 ° to 450 °. The film is formed using a method.

  Next, as shown in FIG. 3A, a contact hole 111 is formed by lithography and dry etching. Subsequently, as shown in FIG. 3B, after forming titanium nitride serving as the barrier metal 112 on the side wall of the contact hole by sputtering and CVD, tungsten serving as the contact plug 113 is formed by atomic layer deposition and CVD. After that, the entire surface is planarized by the CMP method.

  Subsequently, as shown in FIG. 4, a dry etch stopper layer 114 and an interlayer insulating film 115 for forming a stack cell are formed. The dry etch stopper layer 114 is a liner nitride film formed by atomic layer deposition as in the contact hole formation, and has a film thickness of about 10 nm to 50 nm at a film formation temperature of 350 to 450 degrees. The interlayer insulating film 115 is also deposited by about 400 nm to 800 nm at a film forming temperature of 350 to 450 degrees using the high density plasma CVD method as in the case of forming the contact holes.

  Next, as shown in FIG. 5, in order to form a stack type cell, a photoresist is applied on the entire surface, the cell formation portion is exposed, the interlayer insulating film 115 is opened by dry etching, and then The liner nitride film 114 is etched to form a stack type cell 116.

  The short side length of the upper part of the stack type cell is 100 nm to 300 nm, and the long side length is 200 nm to 500 nm.

  When the liner nitride film 114 is etched, over-etching is performed so that the etching reaches the tungsten plug 113 without variation in the wafer surface, so that the stack cell bottom portion 117 has a square shape. If the lower electrode and the capacitor insulating film are formed as they are, electric field concentration occurs at the corners, which causes an increase in leakage current and deterioration in reliability.

  Therefore, the electric field concentration is reduced by making the bottom of the capacitor cell round. That is, after the liner nitride film 114 is dry etched to form the stack type cell 116, a sidewall having a curvature at the bottom is formed on the side wall of the capacitor cell by using an atomic layer deposition method.

  As shown in FIG. 12, the film formation cycle immediately after starting the nitride film formation by atomic layer deposition is set to a dichlorosilane: ammonia purge ratio of about 1:10 times, and as the film formation cycle proceeds, The nitride film 118 is formed so that the purge ratio is gradually changed and the purge ratio is 1: 1 or 2: 1 in the cycle immediately before the film formation is completed. That is, the nitride film has a nitrogen / silicon ratio varying from about 1.0 to about 1.25 with respect to the depth direction of the film, so that the dry etching rate decreases with respect to the depth direction of the film ( FIG. 13).

  The film forming temperature is 350 to 450 ° C., and the film forming pressure is about 500 to 1500 Pa at the time of dichlorosilane purging and 30 to 130 Pa at the time of ammonia purging.

  In this way, as shown in FIG. 6, the nitride film 118 in which the dry etching rate decreases in the depth direction is formed.

  The dichlorosilane: ammonia purge ratio may be changed for each cycle, or the purge ratio may be changed stepwise for every fixed cycle, for example, every 50 cycles.

Subsequently, anisotropic dry etching is performed, for example, at a pressure of 5 Pa, a gas flow rate ratio CHF ₃ : O ₂ = 15: 1, and an RF power of 200 W to leave a nitride film only on the side wall of the cell. At this time, since the etching rate differs in the depth direction, the shape has a negative curvature at the bottom of the sidewall, unlike the conventional sidewall shape.

  The change in the etching shape is shown using FIG. 14 shows only one side of the stack cell. As shown in FIG. 14A, two layers of nitride films having different dry etch rates are formed by atomic layer deposition by the above method, and then anisotropic etching is performed. In FIG. 14A, the upper nitride film has a thickness of 20 nm and a nitrogen / silicon ratio of 1.0, that is, a dry etching rate of about 100 nm / min. The lower nitride film is a nitride film having a thickness of 10 nm and a nitrogen / silicon ratio of 1.25, that is, a dry etching rate of 8 nm / min.

  As shown in FIG. 14B, after 20 seconds of anisotropic etching, the etching reaches the lower nitride film in the plane portion, but the remaining film of the upper nitride film still exists on the cell side wall portion. The upper part is rounded with a positive curvature and the lower part is vertical.

  After the etching time of 80 seconds, the shape is as shown in FIG. 14C, and after 100 seconds, as shown in FIG. 14D, a side wall with a negative curvature is formed at the cell bottom. .

  Note that the tail distance 31 at the bottom of the sidewall shown in FIGS. 14E and 14F is proportional to the thickness of the upper nitride layer. The side wall thus formed has a positive curvature at the upper part 33 and a negative curvature at the lower part 34, the side wall height 32 is larger than the tail distance 31, and the ratio is larger than 1.0. Become.

  Although the results shown here were performed with two-layer films having different etching rates, a sidewall having a curvature at the bottom can be formed in the same manner even with a multilayer film of three or more layers using atomic layer deposition. The curvature is related to the stacking degree of nitride films having different etching rates.

  As shown in FIGS. 7 and 8, in order to form a capacitor lower electrode after the sidewall 119 having the above characteristics is formed inside the stack cell, for example, titanium nitride 120 is formed by an organic source-derived CVD method or atomic layer deposition method. Is used to form a film.

  Next, as shown in FIG. 9, in order to leave titanium nitride only inside the stack cell, a resist (not shown) is applied to the entire surface, and then the entire surface is exposed to leave the resist only inside the stack cell. Further, the titanium nitride other than the stack cell is removed by dry etching the entire surface, the resist inside the stack cell is removed, and the titanium nitride lower electrode 121 is formed.

Subsequently, as shown in FIG. 10, the capacitor insulating film layer 122 is formed of, for example, alumina hafnium oxide (AlHfO) or hafnium oxide (HfO ₂ ), and the upper electrode 123 is formed using titanium nitride. .

  Finally, as shown in FIG. 11, the upper electrode and the capacitor dielectric film in the peripheral circuit region that form the contact hole that continues to the wiring layer are removed by lithography and etching techniques to form a DRAM capacitor.

  As described above, according to the present embodiment, a nitride film formed by an atomic layer deposition method is used as the sidewall formed on the capacitor cell sidewall. When forming a nitride film using an atomic layer deposition method, for example, it is formed by alternately purging dichlorosilane and plasma-treated ammonia, but the ammonia purge time is 10 times to 2 times the dichlorosilane purge time. By changing to 1 / minute, the ratio of nitrogen / silicon in a thin layer formed in one cycle can be changed to about 1.0 to 1.25. That is, since the number of silicon-nitrogen bonds in each layer is different, a nitride film in which the dry etching rate changes stepwise or continuously can be formed.

  Therefore, the sidewall of the capacitor cell side wall is formed by performing dry etching with high anisotropy after the above-described nitride film is formed, and thus the sidewall of the stack cell formed in this way has a negative curvature. By forming, the electric field concentration at the bottom of the capacitor cell is relaxed, and the reliability of the capacitor cell leakage current can be reduced and the dielectric breakdown of the capacitor dielectric film can be improved.

Further, by forming the side wall on the cell side wall, it is possible to prevent side etch from occurring when the liner nitride film for cell formation cleans the outermost surface of the tungsten plug.
(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIGS.

  In this embodiment, in order to prevent side etching due to cleaning or the like, a nitride film having a different etching rate with respect to the depth direction is etched without etching the liner nitride film after etching the interlayer insulating film at the time of stack cell formation. After film formation by atomic vapor deposition, a sidewall having a negative curvature at the bottom is formed by anisotropic dry etching.

  Basically, the same structure as that of the first embodiment is shown in FIGS. The difference is that, as shown in FIG. 15, after etching the interlayer film 115, which is a silicon oxide film, at the stage of dry etching for forming a stack cell, it continues in the depth direction as shown in FIG. The nitride film 124 whose dry etching rate is lowered gradually or stepwise is formed by atomic layer deposition.

  The change in the etching shape is shown using FIG. The figure shown in FIG. 19 shows only one side of the stack cell. The difference from FIG. 14 is that the nitride film thickness at the bottom of the stack cell is raised by the liner nitride film that was not etched when the stack cell was formed. It is a point. Similar to the first embodiment, two layers of nitride films having different dry etch rates are formed, and anisotropic etching is performed. In FIG. 19A, the upper nitride film is a nitride film formed by atomic layer deposition having a thickness of 20 nm and a nitrogen / silicon ratio of 1.0, that is, a dry etching rate of about 100 nm / min. The nitride film has a thickness of 40 nm, including the liner nitride film thickness of 30 nm, and has a nitrogen / silicon ratio of 1.25, that is, a dry etching rate of 8 nm / min.

  As shown in FIG. 19 (b), after 20 seconds of anisotropic etching, etching reaches the lower nitride film in the planar portion, but the upper layer remaining film still exists on the cell side wall, and the conventional side wall is present. The upper part, which is the same shape as, is rounded and the lower part is vertical.

  After an etching time of 80 seconds, the shape is as shown in FIG. 19C, and further etching proceeds to form a rounded sidewall at the cell bottom as shown in FIG. 19D. In this way, the sidewall 125 having a negative curvature at the bottom is formed on the side wall of the stack cell as shown in FIG.

  The capacitor is formed by forming the lower electrode 121, the capacitor dielectric film 122, and the upper electrode 123 as in the first embodiment (FIG. 18).

  As described above, when forming the stack cell, anisotropic dry etching is performed after forming a nitride film having etching rate resistance in the depth direction without etching the liner nitride film after etching the interlayer film. As a result, a sidewall having a negative curvature at the bottom is formed on the side wall of the stack cell.

This allows liner nitridation by reverse sputtering using argon to lower the contact resistance between the contact plug and the lower electrode, cleaning the outermost surface of the plug with a gas using nitrogen trifluoride, or cleaning with hydrofluoric acid. The side wall of the cell side wall can be prevented from retreating like the side etch 62 (FIG. 36), and the concentration of the electric field at the bottom of the capacitor cell is suppressed to reduce the leakage current, the dielectric breakdown over time, etc. Reliability can be improved.
(Third embodiment)
A third embodiment of the present invention will be described with reference to FIGS.

  1 to 5 has the same structure as that of the first embodiment. The difference is that after the stack cell is formed, the sidewall is formed using amorphous silicon having a film forming temperature of 350 ° C. to 450 ° C.

  As shown in FIGS. 20 and 21, after the amorphous silicon 126 is formed to a thickness of about 10 nm to 50 nm, a silicon oxide film layer 127 is formed about 2 to 10 nm isotropically on the amorphous silicon surface by plasma oxidation.

Subsequently, anisotropic dry etching having selectivity such that the dry etching rate of silicon: silicon oxide film is 1:10 at a pressure of 3 Pa and a gas mixture ratio of CF ₄ : H ₂ = 7: 3. Then, sidewalls made of amorphous silicon are formed on the cell sidewalls. Note that dry etching in which the silicon oxide film / silicon film selection ratio is 10 times or more may be used. By further increasing the gas mixing ratio of H ₂ , the selection ratio of silicon: silicon oxide film is improved. In this dry etching, since the upper layer is a low etching resistant layer and the lower layer is a high etching resistant layer, the change in etching shape is as shown in FIG. That is, the shape has a negative curvature at the bottom of the sidewall, and the tail distance 31 is proportional to the plasma oxide film thickness.

  In this manner, after forming the sidewall 128 having a negative curvature on the side wall of the stack cell with amorphous silicon as shown in FIG. 22, the lower electrode 121, the capacitor dielectric film, and the like, as in the first embodiment. 122 and the upper electrode 123 are formed (FIG. 23).

As described above, by forming the sidewall having a negative curvature at the bottom of the stack cell with amorphous silicon having a film forming temperature of 350 to 450 ° C., the electric field concentration at the bottom of the capacitor cell is alleviated and the capacitor cell leakage current is reduced. Reduces and improves reliability such as dielectric breakdown of capacitor dielectric film.
(Fourth embodiment)
A fourth embodiment of the present invention will be described with reference to FIGS.

  In this embodiment, a sidewall having a positive curvature at the upper part and a negative curvature at the lower part is formed of a laminated film formed by CVD (chemical vapor deposition), and the lower layer film has a dry etching rate of 10 with respect to the upper layer film. A double-fold insulating film is formed after the stack cell is formed, and the sidewall is formed by performing anisotropic dry etching.

Basically, it has the same structure as that of the first embodiment shown in FIG. The difference is that cobalt silicide 129 is used in the silicide region as shown in FIG. 24, and the dry etch stopper nitride film 130 used in forming the stack cell is SiH ₂ (NHC (CH ₃ ) ₃ ) ₂ , which is an organic source. BBTAS-SiN using [BTBAS: Bis Tertiary Butyl Amino Silane] and HCD-SiN using Si ₂ Cl ₆ [HCD: Hexa Chloro Disilane] are used.

  The first, second and third embodiments are cases where the design rule is smaller than 65 nm, that is, nickel silicide is used in the silicide region, and the fourth embodiment corresponds to the case where the design rule is 90 nm or more. Since cobalt silicide has heat resistance up to about 600 ° C., BTBAS-SiN or HCD-SiN having a film formation temperature of 550 ° C. to 600 ° C. can be used. The first embodiment using atomic layer deposition is possible even when cobalt silicide is used as the silicide.

The fourth embodiment is similar to FIGS. 1 to 5 of the first embodiment. However, as shown in FIGS. 24 and 25, a high resistance layer 130 against dry etching at the time of stack cell sidewall formation is formed on the upper side. An oxide film or BTBAS-derived BTBAS-SiO ₂ [BTO] using the listed BTBAS-SiN or HCD-SiN and using Si (OC ₂ H ₅ ) ₄ [TEOS: Tetra Ethyl Ortho Silane] for the low resistance layer 131 Then, the silicon flow rate ratio is set to, for example, a pressure of 3.3 Pa, C ₄ F ₆ : CF ₄ : Ar: O ₂ = 2: 1: 4: 2, RF power 1800 W, and a silicon nitride film and a silicon oxide film A selective anisotropic dry etching is performed to form the same structure as shown in FIG.

  Thus, as shown in FIG. 26, after forming a sidewall 132 having a negative curvature at the lower part on the side wall of the stack cell using BTBAS-SiN or HCD-SiN, the lower electrode is formed as in the first embodiment. 121, capacitor dielectric film 122, and upper electrode 123 are formed (FIG. 27).

  As described above, by forming the sidewall having a negative curvature at the bottom of the stack cell with BTBAS-SiN or HCD-SiN, the electric field concentration at the bottom of the capacitor cell is alleviated, and the capacitor cell leakage current is reduced. Improves reliability such as dielectric breakdown prevention of dielectric film.

  The semiconductor device and the manufacturing method thereof according to the present invention have a structure in which the corner of the capacitor lower electrode is not formed, the electric field concentration at the bottom of the capacitor is alleviated, the capacitor cell leakage current is reduced, and the dielectric breakdown of the capacitor dielectric film is prevented. This is effective for improving the reliability of the semiconductor device and is useful for a semiconductor device having a capacitor element such as a DRAM.

It is sectional drawing of the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 2 is a process cross-sectional view subsequent to FIG. 1. FIG. 3 is a process sectional view subsequent to FIG. 2. FIG. 4 is a process sectional view subsequent to FIG. 3. FIG. 5 is a process sectional view subsequent to FIG. 4. FIG. 6 is a process sectional view subsequent to FIG. 5; FIG. 7 is a process sectional view subsequent to FIG. 6; FIG. 8 is a process sectional view subsequent to FIG. 7; FIG. 9 is a process sectional view subsequent to FIG. 8. FIG. 10 is a cross-sectional view of the next step of FIG. 9. FIG. 11 is a process sectional view subsequent to FIG. 10; It is the figure which showed the gas cycle about the formation method of an ALD silicon nitride film. It is the figure which showed the relationship between nitrogen / silicon ratio of a silicon nitride film, and a dry etching rate. (a)-(e) is the figure which showed the simulation result based on 1st Embodiment, 2nd Embodiment, and 4th Embodiment of this invention, (f) is an actual cross-sectional SEM image. It is sectional drawing of the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. FIG. 16 is a process sectional view subsequent to FIG. 15; FIG. 17 is a process sectional view subsequent to FIG. 16; FIG. 18 is a process sectional view subsequent to FIG. 17; It is the figure which showed the simulation result which concerns on the 3rd Embodiment of this invention. It is sectional drawing of the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. FIG. 21 is a process sectional view subsequent to FIG. 20; FIG. 22 is a process sectional view subsequent to FIG. 21; FIG. 23 is a process sectional view subsequent to FIG. 22; It is sectional drawing of the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. FIG. 25 is a process cross-sectional view subsequent to FIG. 24. FIG. 26 is a process sectional view subsequent to FIG. 25; FIG. 27 is a process sectional view subsequent to FIG. 26; It is sectional drawing of the manufacturing process of the semiconductor device which concerns on a prior art. FIG. 29 is a process sectional view subsequent to FIG. 28; FIG. 30 is a process sectional view subsequent to FIG. 29; FIG. 31 is a process sectional view subsequent to FIG. 30; FIG. 32 is a process cross-sectional view subsequent to FIG. 31. FIG. 33 is a process sectional view subsequent to FIG. 32; FIG. 34 is a process sectional view subsequent to FIG. 33; It is a figure explaining the subject of the capacitor formation process in a prior art. It is a figure explaining the subject of the capacitor formation process in a prior art. It is a figure explaining the subject of the capacitor formation process in a prior art.

Explanation of symbols

101 Semiconductor substrate 102 Element isolation region 103 Gate insulating film 104 Gate electrode 105 Side wall 106 Nickel layer 107 Cap titanium nitride 108 Nickel silicide layer 109 Liner nitride film 110 for contact hole Interlayer insulating film 111 Contact hole 112 Barrier metal layer 113 Tungsten 114 Stack cell liner nitride film 115 Interlayer insulation film 116 Stack cell 117 Stack cell bottom corner 118 Side wall forming atomic layer deposited silicon nitride film 119 Stack cell side wall (atomic layer deposited silicon nitride film)
120 Titanium nitride for lower electrode 121 Lower electrode 122 Capacitor insulating film 123 Atomic layer deposited silicon nitride film for forming titanium nitride sidewall for upper electrode 125 Stack cell sidewall (atomic layer deposited silicon nitride film)
126 Amorphous silicon for sidewall formation 127 Plasma oxide film 128 Stack cell sidewall (amorphous silicon)
129 Cobalt silicide 130 CVD silicon nitride film 131 for sidewall formation CVD silicon oxide film 132 for sidewall formation Stack cell sidewall (CVD silicon nitride film)
31 Stack cell side wall width 32 Stack cell side wall height 33 Stack cell side wall upper part 34 Stack cell side wall bottom part 50 Semiconductor substrate 51 Contact plug 52 Stack cell liner nitride film 53 Interlayer insulation film 54 Stack cell 55 Lower electrode CVD metal film 56 Photo Resist 57 Lower electrode 58 Capacitor insulating film 59 Upper electrode 61 Electric field concentration portion 62 Etching seed 63 Polymer layer 64 Micro trench 65 Electric field concentration portion 66 Side etching portion 67 Electric field concentration portion

Claims (10)

An interlayer insulating film provided on the semiconductor substrate;
A stack cell selectively opening the interlayer insulating film;
A stack type capacitor comprising a capacitor lower electrode, a capacitor dielectric film, and a capacitor upper electrode provided in order in the stack cell;
A semiconductor device comprising a sidewall having a shape in which an upper portion has a positive curvature and a lower portion has a negative curvature between the capacitor lower electrode and the side wall of the stack cell.   The semiconductor device according to claim 1, wherein the sidewall is made of a silicon nitride film, and a nitrogen / silicon ratio with respect to a depth direction of the film increases continuously or stepwise.   The semiconductor device according to claim 2, wherein the nitrogen / silicon ratio changes from 1.0 to 1.25 with respect to a depth direction of the film. Forming an interlayer insulating film on the semiconductor substrate;
Selectively opening the interlayer insulating film to form a stack cell;
Forming a silicon nitride film on the semiconductor substrate on which the stack cell is formed;
Forming a sidewall on the side wall of the stack cell by dry etching the silicon nitride film;
Forming a capacitor lower electrode, a capacitor dielectric film and a capacitor upper electrode in order inside the stack cell in which the sidewall is formed,
The silicon nitride film is formed by using atomic layer deposition and continuously or stepwise decreasing the purge time ratio of the nitrogen source gas to the silicon source gas for each cycle. Method.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the purge time ratio is changed from 10 times to 1/2 times.   When the silicon nitride film has a nitrogen / silicon ratio that increases in the depth direction, dry etching is performed to reduce the etching rate of the film from 10 times to 1 time in the depth direction. 6. The method of manufacturing a semiconductor device according to claim 5, wherein a negative curvature is given to the lower portion. Forming a liner nitride film between the semiconductor substrate and the interlayer insulating film;
7. The method of manufacturing a semiconductor device according to claim 4, wherein in the step of forming the sidewall, the silicon nitride film is etched and the liner nitride film is continuously etched. Forming an interlayer insulating film on the semiconductor substrate;
Selectively opening the interlayer insulating film to form a stack cell;
Forming a laminated film composed of a lower layer film and an upper layer film on the semiconductor substrate on which the stack cell is formed;
Dry etching the laminated film to form a sidewall made of the lower layer film on the side wall of the stack cell;
Forming a capacitor lower electrode, a capacitor dielectric film and a capacitor upper electrode in order inside the stack cell in which the sidewall is formed,
In the step of forming the stacked film, the upper layer film is a low resistance layer and the lower layer film is a high resistance layer with respect to the dry etching. The step of forming the laminated film includes a step of forming a silicon film to be the lower layer film, and a step of forming a silicon oxide film to be the upper layer film by plasma oxidizing the surface of the silicon film.
9. The method of manufacturing a semiconductor device according to claim 8, wherein in the step of forming the sidewall, dry etching is performed so that the silicon oxide film / silicon film selection ratio is 10 times or more to give a negative curvature to the lower portion of the sidewall. The step of forming the laminated film includes a step of forming a silicon nitride film to be the lower layer film and a step of forming a silicon oxide film to be the upper layer film by using CVD.
9. The method of manufacturing a semiconductor device according to claim 8, wherein in the step of forming the sidewall, a negative curvature is given to the lower portion of the sidewall by performing dry etching with a silicon oxide film / silicon nitride film selection ratio of 10 times or more. .

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