KR20060059168A - Input/output circuit and semiconductor input/output device - Google Patents

Abstract

(Problem) Provided are an input / output circuit and a semiconductor input / output device capable of preventing an increase in power consumption.

(Resolution) The tristate output circuit 1 (input / output circuit) includes a P-MOS transistor 65 for driving the output pad PADo based on the enable signal oe, and a gate of the P-MOS transistor 65. Outputting pulse signals oe5 and -oe5 having a predetermined time width when the signal level of the enable signal oe and the P-MOS transistor 64 for controlling the potential of the node pg connected thereto are shifted. In the period during which the one-short pulse generating circuit 10 and the pulse signals oe5 and -oe5 are output, a bias voltage Vbias is generated for controlling the P-MOS transistor 64, and the bias voltage Vbias is generated. Is applied to the gate of the P-MOS transistor 64.

I / O Circuit, Semiconductor I / O Device

Description

I / O Circuit and Semiconductor I / O Device {INPUT / OUTPUT CIRCUIT AND SEMICONDUCTOR INPUT / OUTPUT DEVICE}

1 is a circuit diagram showing the configuration of a tristate output circuit 1 according to a first embodiment of the present invention.

Fig. 2 is a diagram showing signal waveforms inside the one short pulse generating circuit 10 in the tristate output circuit 1 according to the first embodiment of the present invention.

Fig. 3 is a circuit diagram showing the configuration of the tristate output circuit 2 according to the second embodiment of the present invention.

Fig. 4 is a circuit diagram showing the configuration of the allowable input circuit 3 according to the third embodiment of the present invention.

Fig. 5 is an equivalent circuit diagram showing the configuration of the bidirectional circuit 4 according to the fourth embodiment of the present invention.

Fig. 6 is an equivalent circuit diagram showing the configuration of the bidirectional circuit 5 according to the fifth embodiment of the present invention.

Fig. 7 is a diagram showing an example of use of the semiconductor input / output device 9 according to the sixth embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

1, 2: tristate output circuit

3: permissible input circuit

4, 5, 6, 7, 8: bidirectional circuit

9: semiconductor input / output circuit

10: one short pulse generating circuit

11, 12, 13, 14, 16, 25, 62, 72, 73, 82, 83: inverter

15, 61: 2-input NAND circuit

20: OE PAD potential determination circuit

21, 22c, 33d, 31, 32, 33a to 33g, 35b, 52, 66, 67, 81: N-MOS transistor

22: clock inverter

22a, 22b, 23, 34, 35a, 41, 42, 43, 51, 64, 65, 71: P-M0S transistor

24, 63: 2-input NOR circuit

30: bias circuit

35, 50: transfer gate

40: floating well charging circuit

68: resistance

A: input terminal

OE: output enable signal input terminal

PAD: I / O pad

PADo: Output Pad

PADi: Input Pad

Y: output terminal

bias, pg: node

oe: output enable signal

oe1, oe2, oe3, oe4: signal

oe5, -oe5: pulse signal

t _da , t _di : delay time

[Patent Document 1] Japanese Patent Application Laid-Open No. 9-139087

[Patent Document 2] Japanese Unexamined Patent Publication No. 2002-280892

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output circuit and a semiconductor input / output device, in particular, having a tolerant function that enables to apply an external power supply voltage higher than an operating voltage to an output terminal, and to enable the output potential to be pulled up to an external power supply voltage. An input / output circuit and a semiconductor input / output device.

BACKGROUND ART In recent years, the semiconductor integrated circuit has been undergoing lower voltage along with lower power consumption. However, when connecting between semiconductor integrated circuits having different power supply voltages, that is, having different signal levels, specifically, for example, a semiconductor integrated circuit operating at a power supply voltage of 3.3V (hereinafter, simply referred to as a semiconductor integrated circuit of 3V system). And a semiconductor integrated circuit (hereinafter, simply referred to as a 5V semiconductor integrated circuit) operating at a power supply voltage of 5V, a semiconductor integrated circuit operating at a lower supply voltage (here, a 3V semiconductor integrated circuit). ) Cannot withstand the higher power supply voltage (here 5V) and may be damaged.

In order to cope with such a problem, conventionally, an input / output circuit capable of applying an external power supply voltage higher than an internal power supply voltage, or an input / output circuit capable of pulling up an external power supply voltage higher than an internal power supply voltage may be used as a signal for a semiconductor integrated circuit on the low voltage side. It was common to use it as an interface.

Such an input-output circuit is disclosed by the said patent document 1 or patent document 2, for example. The present prior art uses a first p-channel MOS (Metal-0xide Semiconductor) transistor (hereinafter referred to simply as P-M0S transistor) for pull-up and a first n-channel MOS transistor (hereinafter, simply N-MOS) for pull-down. A transistor) is connected in series, and an external pad is connected to this connection part. A switch by the second P-MOS transistor is formed between the gate and the output pad of the first P-MOS transistor. Further, a second N-MOS transistor is formed between the drain of the first N-MOS transistor and the output pad to reduce the voltage applied between the source and the drain of the first N-MOS transistor. In this configuration, for example, when an external voltage higher than the internal power supply voltage is applied to the output pad, the second P-MOS transistor is turned on. As a result, the second P-M0S transistor functions as an output transistor. At this time, since the gate potential of the first P-M0S transistor becomes an external voltage, the first P-M0S transistor is turned off, so that current does not flow from the output pad to the internal power supply voltage side. Further, even when a voltage equal to or higher than the breakdown voltage of the first N-MOS transistor is applied to the output pad, the voltage applied between the source and the drain of the first N-MOS transistor by the second N-MOS transistor is reduced. Therefore, the first N-MOS transistor is prevented from being damaged by the voltage applied to the output pad.

In the conventional input / output circuit, when an external voltage higher than the internal power supply voltage is applied to the output pad, the gate is connected to the gate of the first P-M0S transistor through the second P-MOS transistor to which the internal power supply voltage is applied to the gate. Current flows into a closed node. As a result, since the gate of the node, that is, the first P-M0S transistor, is pulled up to an external voltage, the first P-M0S transistor is turned off, so that the current path from the output pad to the internal power supply voltage side is interrupted.

However, in such a configuration, for example, when an external power supply voltage equal to or greater than the internal power supply voltage is applied to the output pad while the first P-M0S transistor is turned on in normal operation, until the first P-M0S transistor is turned off. It takes time. That is, until the gate potential of the first P-M0S transistor is pulled up to the external power supply voltage level, the first P-M0S transistor is continuously turned on, so that the current from the external power supply voltage charges the gate of the first P-M0S transistor. A component and a component flowing to the internal power supply voltage side through the first P-M0S transistor are included. Therefore, it takes time for the gate potential of the first P-M0S transistor to pull up until the first P-M0S transistor is turned off (that is, a step occurs in the pull-up waveform), and as a result, consumption There is a problem of increased power.

Then, this invention is made | formed in view of the said problem, and an object of this invention is to provide the input / output circuit and semiconductor input / output device which can prevent the increase of power consumption.

In order to achieve this object, an input / output circuit according to the present invention includes a first transistor for driving an output unit based on a predetermined signal, a second transistor for controlling a potential of a node connected to a gate of the first transistor, and a predetermined signal. A pulse generating circuit for outputting a pulse having a predetermined time width when the signal level transitions, and a bias voltage for controlling the second transistor in a period in which the pulse is output, generating the bias voltage to the gate of the second transistor. It consists of a bias circuit to apply.

When a predetermined signal, for example, an enable signal transitions from the H level to the L level, a pulse having a predetermined time width is generated, and during the period in which the pulse is output, the gate bias voltage of the second transistor is applied from the bias circuit. With this configuration, even if an external voltage higher than the internal voltage is applied to the output portion in this period, the potential of the node connected to the gate of the first transistor can be quickly pulled up through the second transistor up to the external voltage. It becomes possible. Thereby, even in the above-described situation, the first transistor can be reliably turned off, thereby preventing the current path from the output portion to the internal voltage side. As a result, increase in power consumption can be prevented.

In addition, since the bias circuit is capable of outputting a bias voltage for facilitating the flow of a current, for example, by the second transistor only during a period in which a pulse is output, the gate of the second transistor is turned off except for this period. It can be set as the structure which applies a voltage. Therefore, for example, even after the output unit is in an indeterminate state, even if the potential of the output unit becomes a potential (intermediate potential) for simultaneously turning on the N-MOS transistor and the P-MOS transistor, the second transistor is not in the above-mentioned period. It can be set as the structure which does not turn on. Thereby, even in the above situation, it is possible to prevent the current path through the second transistor from the node connected to the gate of the first transistor to the output section to be formed, and as a result, increase in power consumption can be prevented. Will be.

To practice the invention  Best form for

EMBODIMENT OF THE INVENTION Hereinafter, the best form for implementing this invention is demonstrated in detail with drawing.

Example  One

First, Embodiment 1 according to the present invention will be described in detail with reference to the drawings. In this embodiment, as an input / output circuit according to the present invention, a tri-state output circuit having an allowable function for applying an external power supply voltage higher than an operating voltage to an output terminal and allowing an output potential to be pulled up to an external power supply voltage is provided. Take as an example. This tristate output circuit is an output interface.

〔Configuration〕

1 is a circuit diagram showing the configuration of the tristate output circuit 1 according to the present embodiment. As shown in Fig. 1, the tristate output circuit 1 includes a one-short pulse generator circuit 10, an OE PAD potential determination circuit 20, a bias circuit 30, a floating well charging circuit 40, and a transfer gate. 50, two input exclusive AND circuit (61; hereinafter referred to as two input NAND circuit), inverter 62, two input exclusive OR circuit (63; hereinafter referred to as two input NOR circuit) and P-MOS transistor (64; second transistor) and P-MOS transistor 65 (first transistor) and N-MOS transistor 66 (third transistor) and N-MOS transistor 67 (fourth transistor) and resistor 68; The input signal a input from the input terminal A is output from the output pad PADo.

However, the tristate output circuit 1 is provided with a configuration in which the output is allowed or denied based on the output enable signal oe (predetermined signal). That is, for example, when the enable signal (oe (here, a signal for enabling the output)) of the H level is input to the input terminal OE, the tristate output circuit 1 enters the input terminal A. The input signal (a) inputted to the output is output from the output pad PADo (output permission). For example, when an L-level enable signal (oe (here, a signal for disabling the output)) is input to the input terminal OE, the tristate output circuit 1 causes the output to be negative. That is, the output from the output pad PADo is interrupted (output disallowed) with high impedance (hereinafter, simply referred to as high Z state).

The configuration of the tristate output circuit 1 will be described in more detail. As shown in Fig. 1, the input terminal A is connected to one input of the two input NAND circuit 61 formed at the input terminal of the tristate output circuit 1 and one input of the two input NOR circuit 63, respectively. do. An input terminal OE is connected to the other input of the two-input NAND circuit 61. Therefore, the two-input NAND circuit 61 outputs the L level only when the input signal a and the enable signal oe are together at the H level. The output of the two-input NAND circuit 61 is connected to the gate of the P-MOS transistor 65 formed at the output terminal of the tristate output circuit 1 via the transfer gate 50 described later.

In addition, the input terminal OE is connected to the other input of the two-input NOR circuit 63 via the inverter 62. Therefore, the two-input NOR circuit 63 outputs the H level only when the input signal a is at the L level and the enable signal oe is at the H level (the output of the inverter 62 is at the L level). The output of the two-input NOR circuit 63 is connected to the gate of the N-MOS transistor 67 formed at the output terminal of the tristate output circuit 1.

At the output end of the tristate output circuit 1, the output of the two-input NAND circuit 61 is a P-MOS transistor 65 connected to a gate through a transfer gate 50 described later, and a two-input NOR circuit 63. An N-MOS transistor 67 is formed in which the output of the signal is connected to the gate. The P-MOS transistor 65 and the N-MOS transistor 67 are transistors for driving the output pad PADo.

The operation of the P-MOS transistor 65 and the N-MOS transistor 67 will be described in detail. When the enable signal oe and the input signal a are both at the H level, the operation of the P-MOS transistor 65 is performed. The L level output from the two-input NAND circuit 61 is applied to the gate through the transfer gate 50. As a result, the P-MOS transistor 65 is turned on so that the power supply line (hereinafter referred to simply as the internal power supply voltage VDDIO) to which the output pad PADo and the internal power supply voltage VDDIO are applied is shorted, so that the output The potential of the pad PADo becomes H level. At this time, since the L level is output from the two-input NOR circuit 63, the N-MOS transistor 67 is turned off.

In addition, when the enable signal oe is at the H level and the input signal a is at the L level, the H level output from the two-input NOR circuit 63 is applied to the gate of the N-MOS transistor 67. As a result, since the N-MOS transistor 67 is turned on and the output pad PADo is grounded through the N-MOS transistors 66 and 67, the potential of the output pad PADo becomes L level. At this time, since the H level is output from the two-input NAND circuit 61, the P-MOS transistor 65 is turned off.

When the enable signal oe is at the L level, the two-input NAND circuit 61 outputs the H level, and the two-input NOR circuit 63 outputs the L level. For this reason, the P-MOS transistor 65 and the N-MOS transistor 67 are turned off, and the output pad PADo becomes a high Z state.

In addition, the potential of the floating well of the P-MOS transistor 65 (hereinafter, simply referred to as well potential), that is, the potential of the back gate is set by the floating well charging circuit 40 to be described later. It is charged to the level). The floating well charging circuit 40 is discussed later. In this description, the internal power supply voltage VDDIO is set to 3.3 V (volts), for example, and the external power supply voltage VTT is set to 5 V, for example.

In addition, the internal power supply voltage VDDIO is always applied to the gate of the N-MOS transistor 66 formed between the N-MOS transistor 67 and the ground. That is, it is always on.

This N-MOS transistor 66 is a protective element for preventing breakage of the N-MOS transistor 67. That is, it is a circuit element for realizing the function which makes it possible to apply external power supply voltage VTT among the permissible functions by this embodiment.

For example, when the external power supply voltage VTT (= 5V) higher than the internal power supply voltage VDDIO (= 3.3V) is applied to the output pad PADo, the potential difference between the external power supply voltage VTT and the ground potential. If the external power supply voltage (VTT = 5V) is applied between the drain and the source of the N-MOS transistor 67 as it is, the N-MOS transistor 67 may not withstand this potential difference and may be damaged.

Thus, as shown in FIG. 1, the normally turned on N-MOS transistor 66 is formed between the output pad PADo and the N-MOS transistor 67. As shown in FIG. Thus, the voltage applied to the drain of the N-MOS transistor 67 is reduced from the voltage applied to the gate of the N-MOS transistor 66 by the threshold voltage Vthn of the N-MOS transistor 66. Therefore, the potential difference between the output pad (PADo) and the ground between the drain and the source of the N-MOS transistor 67 can be avoided as it is (so-called Vt drop). As a result, breakage of the N-MOS transistor 67 can be prevented.

1, the enable signal oe input from the input terminal OE is also input to the one short pulse generation circuit 10. As shown in FIG. The one short pulse generating circuit 10 is a pulsed signal having a predetermined time width when the enable signal oe transitions from the H level to the L level (corresponding to the pulse signals oe5 and -oe5 as will be described below). It serves as a means for outputting the.

As shown in Fig. 1, this one short pulse generator circuit 10 includes an inverter 11 (first inverter) and an odd number of inverters (three in Fig. 1) 12, 13 and 14 (second inverter). It has an input NAND circuit 15 and an inverter 16 (third inverter). The number of inverters (inverters 12 to 14 in FIG. 1) formed in series between the inverter 11 and the two-input NAND circuit 15 determines the time widths of the pulse signals oe5 and -oe5 described later. It is an element to do this. The number of these inverters is not limited to the three illustrated in FIG. 1, and can be changed in various ways as needed. However, since the one-short pulse generator circuit 10 according to the present embodiment generates the pulse signal oe5 using the two-input NAND circuit 15, the number of the inverters needs to be an odd number.

The inverter 11 in the one short pulse generator circuit 10 is formed at an input terminal of the one short pulse generator circuit 10. The enable signal oe input from the input terminal OE is first input to the input of this inverter 11. The output of the inverter 11 is divided into two. One of the branches is connected to one input of the two-input NAND circuit 15 formed at the output terminal of the one short pulse generator circuit 10. The other side of the branch is similarly connected to the other input of the two-input NAND circuit 15 via inverters 12, 13 and 14.

Here, the enable signal oe input to the one-short pulse generator circuit 10, the signals oe1, oe2, oe3 and oe4 output by the inverters 11, 12, 13 and 14, respectively, and two inputs. The waveform of the pulse signal oe5 which the NAND circuit 15 outputs is shown in FIG.

As shown in Fig. 2, from the input terminal OE, for example, an enable signal oe that changes from H level to L level, that is, a signal state when the output is disabled from enable to disable is input. do. This enable signal oe is inverted by the inverter 11 (see the signal oe1 in FIG. 2) and then input to one input of the inverter 12 and the two-input NAND circuit 15.

However, the signal passing through the inverter 11 receives a delay. In the operation described later, the signals passing through the inverters 12, 13, and 14 are similarly delayed. Here, let the delay times by each inverter 11, 12, 13, and 14 be _tdi , respectively. Thus, as shown in Fig. 2, the up edge of the signal oe1 is delayed by the delay time t _di than the down edge of the enable signal oe. Similarly, since the signal passing through the inverters 12, 13 and 14 also receives a circuit delay, the down edge of the signal oe2 is delayed by the delay time t _di than the up edge of the signal oe1, and the signal oe3 The up edge of is delayed by the delay time t _di than the down edge of the signal oe2, and the down edge of the signal oe4 is delayed by the delay time t _di than the up edge of the signal oe3.

As a result, the signal oe4 whose delay is delayed by 3 x t _{di from} the up edge of the signal oe1 input to the other input of the two-input NAND circuit 15 to the other input of the two-input NAND circuit 15. Is input. In other words, the signal oe4 is input to the two-input NAND circuit 15 with a delay of 3 x t _di than the signal oe1.

Since the two-input NAND circuit 15 takes a logical product of the signal oe1 and the signal oe4, it outputs a pulse signal oe5 having a time width (3 x t _di ) equal to the sum of the delay times (Fig. 2). However, since there is a circuit delay caused by the two-input NAND circuit 15 itself, when this delay time is set to t _da , the down edge of the pulse signal oe5 has a delay time t _da than the up edge of the signal oe1. Delayed, and the up edge of the pulse signal oe5 is delayed by the delay time t _{da from} the up edge of the signal oe4 (see FIG. 2).

Returning to FIG. 1, the circuit configuration will be described. As shown in FIG. 1, the pulse signal oe5 output from the two-input NAND circuit 15 of the one-short pulse generator circuit 10 is input directly to the OE / PAD potential determination circuit 20, and the inverter 16. After inverting by passing through), it is input to the OE / PAD potential determination circuit 20.

This configuration will be described in detail. The output of the two-input NAND circuit 15 formed at the output terminal of the one short pulse generator circuit 10 is branched. One of the branches constitutes the clock inverter 22 in the OE / PAD potential determination circuit 20 similarly to the one input of the two-input NOR circuit 24 in the OE / PAD potential determination circuit 20. It is connected to the gate of the P-MOS transistor 22a. That is, the pulse signal oe5 is a P-MOS for controlling one input of the two-input NOR circuit 24 in the OE / PAD potential determination circuit 20 and the operation / inoperation of the clock inverter 22. It is input to the control terminal (gate) of the transistor 22a, respectively.

In addition, the other side of the branch passes through the inverter 16, and then similarly to the gate of the N-MOS transistor 22d constituting the clock inverter 22 in the OE / PAD potential determination circuit 20, similarly to the OE / PAD. It is connected to the gate of the P-MOS transistor 23 in the potential determination circuit 20, respectively. That is, the inverted pulse signal oe5 (hereinafter simply referred to as pulse signal -oe5) is connected to the control terminal (gate) of the N-MOS transistor 22d for controlling the operation / disoperation of the clock inverter 22. Input to the control terminal (gate) of the P-MOS transistor 23 for inputting the internal power supply voltage VDDIO to the other input of the two-input NOR circuit 24 when the clock inverter 22 is inactive. .

In this way, the OE / PAD potential determination circuit 20 to which the pulse signals oe5 and -oe5 are inputted has a signal level of the enable signal oe during the period in which the pulse signals oe5 and -oe5 are output. Means for determining the potential of the output pad PADo when the transition is made, and outputting a voltage for outputting the bias voltage Vbias from the bias circuit 30 described later based on the determination result (potential determination output circuit). Function as.

As shown in Fig. 1, the OE / PAD potential determination circuit 20 includes an N-MOS transistor 21, a clock inverter 22, a P-MOS transistor 23, a two-input NOR circuit 24, and an inverter ( 25).

The internal power supply voltage VDDIO is always applied to the gate of the N-MOS transistor 21 formed at the input terminal of the OE / PAD potential determination circuit 20. That is, it is always on. The source of the N-MOS transistor 21 is connected to the output pad PADo via a resistor 68. The drain of the N-MOS transistor 21 is connected to the gates of the P-MOS transistor 22b and the N-MOS transistor 22c, which respectively constitute a clock inverter 22 located at the rear end as viewed from the output pad PADo. .

This N-MOS transistor 21 is a protection element for preventing the breakage of the N-MOS transistor 22c in particular in the clock inverter 22. That is, it is a circuit element for realizing the function which makes it possible to apply external power supply voltage VTT among the permissible functions by this embodiment.

The clock inverter 22 is monitoring the potential of the output pad PADo via the resistor 68, but in particular the external power supply voltage (higher than the internal power supply voltage VDDIO (= 3.3 V)). In the case of VTT (= 5V), when the potential of the output pad PADo is applied to the gate of the N-MOS transistor 22c as it is, the N-MOS transistor is similar to the N-MOS transistor 67 described above. The 22c may not withstand the external power supply voltage VTT and may be broken.

Thus, as shown in FIG. 1, the normally turned on N-MOS transistor 21 is formed between the output pad PADo and the clock inverter 22. As shown in FIG. Thus, since the Vt drop occurs in the N-MOS transistor 21, the potential applied to the gate of the N-MOS transistor 22c is the gate potential of the N-MOS transistor 21 (in this case, the internal power supply voltage ( VDDIO)) minus the threshold voltage Vthn, that is, VDDIO-Vthn, which is lower than the external voltage VTT applied to the output pad PADo.

Thus, by forming the N-MOS transistor 21, the potential difference of the output pad PADo is not applied to the gate of the N-MOS transistor 22c as it is, and as a result, the N-MOS transistor 22c Breakage is prevented.

In addition, the clock inverter 22 formed in the OE / PAD potential determination circuit 20 monitors the potential of the output pad PADo as described above, and based on the result, the bias circuit 30 to be described later is performed. It functions as a means for operating. This clock inverter 22 has a configuration in which the P-MOS transistors 22a and 22b and the N-MOS transistors 22c and 22d are connected in series between the internal power supply voltage VDDIO and ground, as shown in FIG. .

In this embodiment, however, four transistors (two P-MOS transistors 22a and 22b and two N-MOS transistors 22c and 22d) are connected in series between the internal power supply voltage (VDDIO) and ground. Although a clock inverter 22 is used, the present invention is not so limited, and three or more transistors including at least one P-M0S transistor and at least one N-MOS transistor are connected in series between an internal power supply voltage (VDDIO) and ground. The configuration may be connected. At this time, the output of the two-input NAND circuit 15 or the inverter 16 is connected to the gates of the transistors other than the one of the P-MOS transistors and the N-MOS transistors that monitor the output pad PADo, thereby providing a pulse signal. It is configured to cut off the internal power supply voltage (VDDIO) to ground except for the period during which (oe5 or -oe5) is being output.

In the clock inverter 22, the gates of the P-MOS transistor 22b and the N-MOS transistor 22c having drains connected to each other are connected to the output pad PADo through the N-MOS transistor 21 and the resistor 68. Is connected to. The source of the P-MOS transistor 22b is connected to the internal power supply voltage VDDIO via the P-MOS transistor 22a. The gate of the P-MOS transistor 22a is connected to the output of the two-input NAND circuit 15 in the one short pulse generator circuit 10. That is, the P-MOS transistor 22a is turned on only when the pulse signal oe5 is input.

In addition, the source of the N-MOS transistor 22c is grounded to ground through the N-MOS transistor 22d. The gate of the N-MOS transistor 22d is connected to the output of the inverter 16 in the one short pulse generator circuit 10. That is, the N-MOS transistor 22d is turned on only when the pulse signal -oe5 is input.

By these configurations, the clock inverter 22 operates by connecting the internal power supply voltage VDDIO-ground only when the pulse signals oe5 and -oe5 are input, and monitors the potential of the output pad PADo. In addition, in this description, "time / period / case" in which the pulse signal oe5 is "input / output" means the period from the down edge to the up edge of the pulse signal oe5 shown in FIG. Similarly, the "time / period / case" in which the pulse signal (-oe5) is "input / output" refers to the period from the up edge to the down edge of the pulse signal (-oe5).

Also, when the pulse signals oe5 and -oe5 are input, if the potential of the output pad PADo is at the L level, the clock inverter 22 passes through the two-input NOR circuit 24 via the P-MOS transistors 22a and 22b. Input the internal power supply voltage (VDDIO) to the other input of. On the other hand, when the pulse signals oe5 and -oe5 are input, if the potential of the output pad PADo is at the H level, the clock inverter 22 passes through the two-input NOR circuit 24 through the N-MOS transistors 22c and 22d. Input the ground potential to the other input.

The output of the clock inverter 22, i.e., the drain of the P-MOS transistor 22b and the N-MOS transistor 22c, is connected to the drain of the P-MOS transistor 23 and the other input of the two-input NOR circuit 24. Connected. The gate of the P-MOS transistor 23 is connected to the output of the inverter 16 in the one short pulse generator circuit 10. That is, the P-MOS transistor 23 is turned on only when the pulse signal -oe5 is not input, thereby applying the internal power supply voltage VDDIO to the other input of the two-input NOR circuit 24.

Thus, the output of the clock inverter 22 in the period in which the pulse signals oe5 and -oe5 are output to the other input of the two-input NOR circuit 24 in the OE / PAD potential determination circuit 20, That is, the result of monitoring the output pad PADo is input, and the internal power supply voltage VDDIO is input in the period in which the pulse signals oe5 and -oe5 are not output. Therefore, the two-input NOR circuit 24 is a period during which the pulse signals oe5 and -oe5 are being output, and the potential of the output pad PADo is at the H level (in this case, the internal power supply voltage VDDIO or the external power supply voltage VTT). In the period of), the H level is output, and other than this period, the L level is output.

The output of the two-input NOR circuit 24 in the OE / PAD potential determination circuit 20 includes the gates of the N-MOS transistors 31 and 32 and the P-MOS transistors (in the bias circuit 30 described later). 34) and the gate of the P-MOS transistor 35a constituting the transfer gate 35 described later.

The output of the inverter 25 in which the output of the two-input NOR circuit 24 is input to the input in the OE / PAD potential determination circuit 20 is the N-MOS transistor 33e in the bias circuit 30. , 33f, 33g) and the gate of the N-MOS transistor 35b in the transfer gate 35 of the bias circuit 30.

The bias circuit 30 to which two outputs from the OE / PAD potential determination circuit 20 (the output of the two-input NOR circuit 24 and the output of the inverter 25) are inputted is the one short pulse generator circuit 10. In the period in which the pulse signals oe5 and -oe5 are outputted from the above, a bias voltage Vbias for controlling the P-MOS transistor 65 formed at the output terminal of the tristate output circuit 1 is generated, and this is P-. It serves as a means for applying to the gate of the MOS transistor 64, that is, the node pg (see FIG. 1). The P-MOS transistor 64 whose gate is connected to the output of the bias circuit 30 is connected to the gate of the P-MOS transistor 65 based on the bias voltage Vbias from the bias circuit 30. By controlling the potential of the node pg, it serves as a means for pulling this up to the potential of the output pad PADo.

The bias circuit 30 has N-MOS transistors 31, 32, and 33a to 33g, a P-MOS transistor 34, and a transfer gate 35 as shown in FIG. In addition, the P-MOS transistor 64 has a gate connected to an output of the bias circuit 30, that is, a node bias in FIG. 1, a drain connected to an output pad PADo through a resistor 68, The source is connected to the gate of the P-MOS transistor 65 via node pg.

The N-MOS transistors 31, 33a to 33d in the bias circuit 30 are connected in series at the N stage (N = 5 in Fig. 1) between the internal power supply voltage VDDIO and ground. That is, the source of the N-MOS transistor 31 is connected to the internal power supply voltage VDDIO, and the drain is connected to the drain of the N-MOS transistor 33a. The source of the N-MOS transistor 33a is connected to the drain of the N-MOS transistor 33b, and the source of the N-MOS transistor 33b is connected to the drain of the N-MOS transistor 33c. The source of the MOS transistor 33c is connected to the drain of the N-MOS transistor 33d. In addition, the gates of the N-MOS transistors 33a to 33c are connected to respective drains. Further, the source and the gate of the N-MOS transistor 33d are grounded.

In the following description, the structure composed of the N-MOS transistors 31 and the N-MOS transistors 33a to 33d is referred to as a vertical stack configuration. In this vertical stack configuration, the drains of the N-MOS transistors 31 and 33a function as output terminals.

The output terminal of the vertical stack component in the bias circuit 30, that is, the drain of the N-MOS transistor 31 and the drain and gate of the N-MOS transistor 33a are also connected to the drain of the N-MOS transistor 33e. . The source of the N-MOS transistor 33e is grounded, and a gate thereof is connected to the output of the inverter 25 in the OE / PAD potential determination circuit 20. The source of the N-MOS transistor 33a and the drain and gate of the N-MOS transistor 33b are connected to the drain of the N-MOS transistor 33f. The source of the N-MOS transistor 33f is grounded, and a gate thereof is connected to the output of the inverter 25 in the OE / PAD potential determination circuit 20. The source of the N-MOS transistor 33b and the drain and gate of the N-MOS transistor 33c are connected to the drain of the N-MOS transistor 33g. The source of the N-MOS transistor 33g is grounded, and a gate thereof is connected to the output of the inverter 25 in the OE / PAD potential determination circuit 20.

In this configuration, the N-MOS transistors 33e to 33g are controlled on / off based on the output of the inverter 25 in the OE / PAD potential determination circuit 20. The N-MOS transistors 33a to 33d are controlled on / off so as to follow the on / off of the N-MOS transistors 33e to 33g.

In addition, the output terminal of the vertical stack component in the bias circuit 30, that is, the drain of the N-MOS transistor 31 and the drain and gate of the N-MOS transistor 33a are also applied to the source of the N-MOS transistor 32. Connected. The drain of the N-MOS transistor 32 is connected to the gate of the P-MOS transistor 64 via node bias. The gate of the N-MOS transistor 32 is connected to the output of the two-input NOR circuit 24 in the OE / PAD potential determination circuit 20. The gate of the N-MOS transistor 31 in the vertical stack configuration is also connected to the output of the two-input NOR circuit 24 in the OE / PAD potential determination circuit 20.

In addition, an internal power supply voltage VDDIO is applied to the source of the P-MOS transistor 34 in the bias circuit 30. The drain of the P-MOS transistor 34 is connected to the gate of the P-MOS transistor 64 via a node bias and a transfer gate 35 composed of the P-MOS transistor 35a and the N-MOS transistor 35b. .

The gate of the P-MOS transistor 34 and the gate of the P-MOS transistor 35a in the transfer gate 35 have an output of the two-input NOR circuit 24 in the OE / PAD potential determination circuit 20. Connected. The output of the inverter 25 in the OE / PAD potential determination circuit 20 is connected to the gate of the N-MOS transistor 35b in the transfer gate 35.

In this configuration, when the L level is output from the two-input NOR circuit 24 and the H level is output from the inverter 25, i.e., the period and / or the output pad where the pulse signal -oe5 is not output. In the period where the potential of PADo is at the L level, the P-MOS transistor 34, the transfer gate 35, and the N-MOS transistors 33e to 33g are turned on, and the N-MOS transistors 31, 32, and 33a to. 33d) is turned off. Thereby, the internal power supply voltage VDDIO applied to the source of the P-MOS transistor 34 is transferred to the gate of the P-MOS transistor 64 through the P-MOS transistor 34, the transfer gate 35 and the node bias. Is applied to.

On the other hand, when the H level is output from the two-input NOR circuit 24 and the L level is output from the inverter 25, that is, as the period during which the pulse signals oe5 and -oe5 are output, the output pad PADo is also output. In a period where the potential of H is the H level (here, the internal power supply voltage VDDIO or the external power supply voltage VTT), specifically, the potential of the output pad PADo is H level, and the enable signal oe transitions to the L level. In this case, the N-MOS transistors 31, 32 and 33a to 33d are turned on, and the P-MOS transistor 34, the transfer gate 35 and the N-MOS transistors 33e to 33g are turned off. Thereby, a bias voltage Vbias is generated based on the internal power supply voltage VDDIO applied to the source of the N-MOS transistor 31, which is applied to the gate of the P-MOS transistor 64 via node bias. .

However, the voltage passing through the N-MOS transistors 31 and 32 in the bias circuit 30, that is, the period during which the pulse signals oe5 and -oe5 are being output, and the potential of the output pad PADo is H level. The bias voltage Vbias output in the period (here, the internal power supply voltage VDDIO or the external power supply voltage VTT) is reduced by the threshold voltages Vthn of these N-MOS transistors 31 and 32. For this reason, the bias voltage Vbias is the voltage applied to the source of the N-MOS transistor 31, that is, the internal power supply voltage VDDIO, minus the threshold voltages Vthn of the N-MOS transistors 31 and 32. Voltage (= VDDIO-2Vthn). That is, a bias voltage Vbias (= VDDIO-2Vthn) having a value twice as low as the threshold voltage Vthn than the internal power supply voltage VDDIO is applied to the gate of the P-MOS transistor 64 through the node bias. . As a result, the P-MOS transistor 64 is in a state in which current easily flows. In other words, the amount of current flowing through the P-MOS transistor 64 can be increased. As a result, the potential of the node pg, that is, the gate potential of the P-MOS transistor 65 can be quickly pulled up to the external power supply voltage VTT applied to the output pad PADo.

In addition, the floating well charging circuit 40 in FIG. 1 functions as a means for charging the floating wells of the P-MOS transistors 51, 64, and 65 formed on the floating well substrate. This floating well charging circuit 40 has three P-MOS transistors 41, 42 and 43, as shown in FIG.

The gate of the P-MOS transistor 41 in the floating well charging circuit 40 is connected to the output pad PADo via a resistor 68. That is, the potential of the output pad PADo is applied to the gate of the P-MOS transistor 41. The internal power supply voltage VDDIO is applied to the source of the P-MOS transistor 41. The drain of the P-MOS transistor 41 is connected to the back gates (also called floating wells) of the P-MOS transistors 41, 42 and 43, and the back gates of the P-MOS transistors 51 and 65 are connected.

In addition, the sources of the P-M0S transistors 42 and 43 in the floating well charging circuit 40 are connected to the output pad PADo via the resistor 68. An internal power supply voltage VDDIO is applied to the gate of the P-MOS transistor 42. On the other hand, the gates of the P-MOS transistors 42 are connected to the drains and back gates of these P-MOS transistors 41, 42 and 43, and the back gates of the P-MOS transistors 51 and 65. That is, the well potentials of the P-MOS transistors 41, 42, 43, 51, 64, and 65 are applied to the gate of the P-MOS transistor 43.

In this configuration, for example, when the potential of the output pad PADo is at the L level, since the P-MOS transistor 41 in the floating well charging circuit 40 is turned on, from the internal power supply voltage VDDIO, Charge flows into the well, and the well potential of the p-MOS transistors 41, 42, 43, 51 and 65 is pulled up to the VDDIO level. At this time, the internal power supply voltage VDDIO is applied to the gate of the P-MOS transistor 42 in the floating well charging circuit 40, and the well potential is fed back to the gate of the P-MOS transistor 43. Therefore, no current flows through the output pad PADo. Thereafter, when the well potential becomes VDDIO, the P-MOS transistor 41 is turned off to terminate the charging.

Also, for example, when the potential of the output pad PADo is at the H level (however, the VDDIO level), the P-MOS transistor 41 in the floating well charging circuit 40 is turned off, and instead, the P-MOS Since the transistor 43 is turned on, electric charge flows into the well from the output pad PADo, and the well potentials of the P-MOS transistors 41, 42, 43, 51 and 65 are pulled up to the VDDIO level. At this time, since the internal power supply voltage VDDIO is applied to the gate of the P-MOS transistor 42 in the floating well charging circuit 40, no current flows through the output pad PADo. Thereafter, when the well potential becomes VDDIO, all of the P-MOS transistors 41, 42, and 43 are turned off to end the charging.

Also, for example, when the potential of the output pad PADo is at a VTT level higher than the internal power supply voltage VDDIO, the P-M0S transistor 41 in the floating well charging circuit 40 is turned off, and instead P Since the MOS transistors 42 and 43 are turned on, electric charge flows from the output pad PADo into the well, and the well potentials of the P-MOS transistors 41, 42, 43, 51, 64, and 65 are pulled up. At this time, the P-MOS transistor 41 remains off because the potential of the output pad PADo is applied to the gate through the resistor 68 and the drain follows the rise of the well potential. Therefore, no current flows through the P-M0S transistor 41 to the power supply voltage VDDIO.

In addition, when the well potential becomes VDDIO, the P-MOS transistor 42 in the floating well charging circuit 40 is turned off, but the P-MOS transistor 43 whose well potential is fed back to the gate remains on. Therefore, the floating well is charged up to the potential of the output pad PADo (= VTT). By operating in this manner, a path through which current flows through the internal power supply voltage VDDIO is not formed, and the well potential can be quickly increased to the external power supply voltage VTT. Thereafter, when the well potential becomes VTT, all of the P-M0S transistors 41, 42, and 43 in the floating well charging circuit 40 are turned off to end the charging.

Also, the transfer gate 50 in FIG. 1 conducts / blocks the connection between the output of the two-input NAND circuit 61 and the gate of the P-MOS transistor 65 based on the potential of the output pad PADo. It serves as a means for doing so. This transfer gate 50 has a P-MOS transistor 51 and an N-MOS transistor 52, as shown in FIG.

The drain of the P-MOS transistor 51 and the source of the N-MOS transistor 52 in the transfer gate 50 are commonly connected to the output of the two-input NAND circuit 61. The source of the P-MOS transistor 51 and the drain of the N-MOS transistor 52 are connected to the source of the P-MOS transistor 64 and the gate of the P-MOS transistor 65. In addition, the gate of the P-MOS transistor 51 is connected to the output pad PADo through the resistor 68, and the back gate is connected to the floating well charging circuit 40 as described above. On the other hand, an internal power supply voltage VDDIO is applied to the gate of the N-MOS transistor 52.

In this configuration, for example, both the input signal a has the H level and the enable signal oe has the H level, that is, the outputs of the two-input NAND circuit 61 and the two-input NOR circuit 63 are both. When at the L level, the node pg (the gate of the P-MOS transistor 65) is brought to the L level through the N-MOS transistor 52 of the transfer gate 50. At this time, the well potentials (backgate potentials) of the P-MOS transistors 51, 64, and 65 are charged to VDDIO by the floating well charging circuit 40.

Further, for example, the input signal a is at the L level and the enable signal oe is at the H level, that is, the outputs of the two-input NAND circuit 61 and the two-input NOR circuit 63 are both at the H level. At that time, the node pg (gate of the P-MOS transistor 65) becomes H level (however, VDDIO level) through the P-MOS transistor 51 of the transfer gate 50. At this time, the well potentials of the P-MOS transistors 51, 64, and 65 are charged to VDDIO by the floating well charging circuit 40.

Further, for example, when the enable signal oe is at L level, that is, when the output of the two-input NOR circuit 63 is at the L level and the output of the two-input NAND circuit 61 is at the H level, the output pad PADo is a negative state (high Z), but if the output PADo is at a VTT level higher than the internal power supply voltage VDDIO, then the node pg (gate of the P-MOS transistor 65) is at the VTT level. Is charged. This is because the bias circuit 30 operates on the basis of the pulse signals oe5 and -oe5 output from the one-short pulse generating circuit 10 when the enable signal oe has transitioned to the L level, whereby the P-MOS transistor ( This is because a bias voltage Vbias is applied to the gate of 64, whereby a current flows from the output pad PADo to the node pg through the resistor 68 and the P-MOS transistor 64.

At this time, since the well potential of the P-MOS transistor 51 in the transfer gate 50 is VTT, the P-MOS transistor 51 is turned off when the potential of the node pg becomes VTT. . The well potential of the P-MOS transistor 64 is also charged to VTT by the floating well charging circuit 40.

Thus, since the well potential becomes VTT and the drain potential becomes VTT (that is, the external power supply voltage VTT applied to the output pad PADo), the source potential, that is, the potential of the node pg becomes VTT. At that point, the P-MOS transistor 51 in the transfer gate 50 is turned off.

In the above case, if the output pad PADo is at the L level or the VDDIO level, the node pg (the gate of the P-MOS transistor 65) passes through the transfer gate 50 or the P-MOS transistor 64. Charged to VDDIO level.

〔action〕

Next, the operation of the tristate output circuit 1 according to the present embodiment will be described. In the following, when the enable signal oe transitions from the H level to the L level, when the external power supply voltage VTT is applied through a pull-up resistor (not shown) to the output pad PADo (this is called 1), and The operation with the case where the output pad PADo becomes an intermediate potential (called 2 in this case) when the enable signal oe is at the L level will be described with an example. However, the intermediate potential is not limited to half of the VDDIO potential, but a P-MOS transistor (eg, 22b in FIG. 1) and an N-MOS transistor (eg, FIG. 1) for monitoring the potential of the output pad PADo. What is necessary is just the electric potential of the range which can turn on 22c) at the same time.

Case 1

First, the operation in the case where the external power supply voltage VTT is applied through the pull-up resistor (not shown) to the output pad PADo by the enable signal oe transitions from the H level to the L level will be described as an example.

In the initial state of this operation, the enable signal oe is at the H level. Here, for example, when the input signal a is at the H level, the output of the two-input NAND circuit 61 is at the L level, and the output of the two-input NOR circuit 63 is at the L level. When the potential of the output pad is at the H (VDDIO) level, the two-input NOR circuit 24 of the OE / PAD potential determination circuit 20 outputs an L level, and the inverter 25 outputs an H level. Therefore, the internal power supply voltage VDDIO output from the bias circuit 30 is applied to the gate of the P-MOS transistor 64.

The well potential of the P-M0S transistor 64 is pulled up to the VDDIO level by the floating well charging circuit 40. Therefore, the P-MOS transistor 64 is turned off after pulling up the source potential, that is, the node pg to the VDDIO level.

Here, when the enable signal oe transitions from the H level to the L level, the output of the two-input NAND circuit 61 becomes H level. As a result, since the H level is applied to the gate of the P-MOS transistor 65 through the transfer gate 50, the output pad PADo becomes in an indefinite state (high Z state). In the description of this operation, the case where the external power supply voltage VTT is applied to the output pad PADo through a pull-up resistor (not shown) is taken as an example. That is, the case where the potential of the output pad PADo becomes VTT will be described.

Further, when the above-described enable signal oe has transitioned from the H level to the L level, the one short pulse generation circuit 10 outputs pulse signals oe5 and -oe5 by performing the operation shown in FIG. . As a result, the OE PAD potential determination circuit 20 temporarily operates to monitor the potential of the output pad PADo. Specifically, since the potential of the output pad PADo is VTT (> VDDIO), the two-input NOR circuit 24 of the OE / PAD potential determination circuit 20 in the period in which the pulse signals oe5 and -oe5 are output. ), The H level is output, and the L level is output from the inverter 25.

In this manner, when the H level is output from the two-input NOR circuit 24 of the OE / PAD potential determination circuit 20 and the L level is output from the inverter 25, the N-MOS transistor 31 is provided in the bias circuit 30. And 32) are turned on. At this time, the N-MOS transistors 33a to 33d are also turned on. As a result, a bias voltage Vbias (= VDDIO-2Vthn) which is twice as low as the threshold voltage Vthn than the internal power supply voltage VDDIO is applied to the node bias.

At this time, the well (back gate) of the P-MOS transistor 64 is charged to the VTT level through the floating well charging circuit 40. For this reason, the P-MOS transistor 64 to which the bias voltage Vbias (= VDDIO-2Vthn) lower than the internal power supply voltage VDDIO is applied to the gate allows the current to pass through as compared to when VDDIO is being applied to the gate. It becomes an easy state. Thus, current flows quickly into the node pg through the resistor 68 and the P-MOS transistor 64. Thereby, the gate potential of the node pg, i.e., the P-MOS transistor 65, is quickly pulled up to the VTT level. As a result, since the gate potential, the back gate potential, and the drain potential (equivalent to the potential of the output pad PADo) of the P-MOS transistor 65 all become VTT, the P-MOS transistor 65 is turned off. As a result, the current path connecting the output pad PADo and the internal power supply voltage VDDIO is interrupted, so that current flows from the output pad PADo through the P-MOS transistor 65 to the internal power supply voltage VDDI0. Incoming is prevented. In other words, an increase in power consumption is prevented.

In addition, since the source potential, the drain potential, and the well potential of the P-MOS transistor 64 both become the VTT level when the potential of the node pg becomes the VTT level, the P-MOS transistor 64 is turned off. do.

After that, when the time corresponding to the predetermined time width of the pulse signals oe5 and -oe5 elapses, that is, when the pulse signals oe5 and -oe5 are not being output, the OE / PAD potential determination circuit 20 Since the L level is output from the two-input NAND circuit 24 of < RTI ID = 0.0 >) and the H level is output from the inverter 25, the internal power supply voltage VDDIO is output from the bias circuit 30. < / RTI > This internal power supply voltage VDDIO is applied to the gate of the P-MOS transistor 64. Therefore, at this time, even if, for example, the potential of the output pad PADo becomes, for example, an intermediate potential, the P-MOS transistor 64 remains off. As a result, current flows from the internal power supply voltage VDDIO applied to the two-input NAND circuit 61 to the output pad PADo through the transfer gate 50, the P-MOS transistor 64, and the resistor 68. Is prevented. In other words, an increase in power consumption is prevented.

Case 2

Next, the operation in the case where the output pad PADo becomes an intermediate potential when the enable signal oe is at the L level will be described as an example.

In this operation, since the output of the two-input NAND circuit 61 is at the H level and the output of the two-input NOR circuit 63 is at the L level, the output pad PADo is in a negative state (high Z state). In this operation description, the case where the potential of the output pad PADo becomes, for example, half of the VDDIO potential (hereinafter, simply referred to as the intermediate potential) is taken as an example.

The intermediate potential applied to the output pad PADo is similarly applied to the OE · PAD potential determination circuit 20 through the N-MOS transistor 21 in the resistor 68 and the OE · PAD potential determination circuit 20. It is applied to the gate of the P-MOS transistor 22b and the gate of the N-MOS transistor 22c which respectively constitute the clock inverter 22 in FIG. As a result, the P-MOS transistor 22b and the N-MOS transistor 22c are turned on at the same time.

However, in the present embodiment, as described above, only when the enable signal oe has transitioned to the L level, the pulse signals oe5 and -oe5 are output from the one short pulse generating circuit 10, and the clock inverter 22 is configured to operate. Therefore, even when the P-MOS transistor 22b and the N-MOS transistor 22c are turned on at the same time by the intermediate potential, the P-MOS transistor 22a is not outputted in the period in which the pulse signals oe5 and -oe5 are not output. And the N-MOS transistor 22d are turned off. Therefore, no through current flows between the internal power supply voltage VDDIO-ground through the clock inverter 22, that is, the P-MOS transistors 22a and 22b and the P-MOS transistors 22c and 22d in this period. As a result, an increase in power consumption is prevented.

The intermediate potential as described above is also applied to the drain of the P-MOS transistor 64 through the resistor 68. However, the present embodiment is configured such that the internal power supply voltage VDDIO output from the bias circuit 30 is applied to the gate of the P-MOS transistor 64 in the period in which the pulse signals oe5 and -oe5 are not output. It is. At this time, the floating well charging circuit 40 is configured to charge the well of the P-MOS transistor 64 to the internal power supply voltage VDDI0. Therefore, even if an intermediate potential is applied to the drain of the P-MOS transistor 64, the P-MOS transistor 64 does not turn on, and as a result, the output is made through the P-MOS transistor 64 and the resistor 68. No DC current flows into the pad (PADo). As a result, an increase in power consumption is prevented.

[Action effect]

As described above, the present embodiment uses the one short pulse generator circuit 10 between the input terminal OE and one input of the two-input NOR circuit 24 that is the input of the OE / PAD potential determination circuit 20. And the potential of the output pad PADo becomes a potential VTT higher than the internal power supply voltage VDDIO in the period during which the pulse signals oe5 and -oe5 are output from the one short pulse generating circuit 10. Since the bias circuit 30 operates to apply a voltage (bias voltage Vbias = VDDIO-2Vthn) lower than the internal power supply voltage VDDIO to the gate of the P-MOS transistor 64, the enable signal oe ) Transitions to the L level, the gate potential of the P-MOS transistor 65 formed between the output pad PADo and the internal power supply voltage VDDIO via the resistor 68 and the P-MOS transistor 64. It can quickly pull up to the external supply voltage (VTT). As a result, it is possible to prevent current from flowing from the output pad PADo to the internal power supply voltage VDDIO side through the P-MOS transistor 65 at the time of pull-up, thereby preventing an increase in power consumption.

In addition, in the present embodiment, the bias circuit 30 operates only during the period in which the pulse signals oe5 and -oe5 are output from the one short pulse generating circuit 10, i.e., the P-MOS transistor 64 is current. The bias voltage Vbias (= VDDIO-2Vthn) is applied to the gate of the P-MOS transistor 64 in the bias circuit 30 to make it easier to flow, and is internal to the gate of the P-MOS transistor 64 outside this period. Since the power supply voltage VDDIO is applied, the pulse signals oe5 and -oe5 are applied even if the potential of the output pad PADo becomes, for example, an intermediate potential after the output pad PADo is in a negative state. In the period of no output, the P-MOS transistor 64 to which the internal power supply voltage VDDIO is applied is not turned on. Therefore, even in the above situation, the current path passing through the P-MOS transistor 64 from the internal power supply voltage VDDIO applied to the two-input NAND circuit 61 to the transfer gate 50 and the output pad PADo is It can be prevented from forming. That is, the current can be prevented from flowing out to the output pad PADo. As a result, increase in power consumption can be prevented.

In addition, the present embodiment uses the clock inverter 22 which operates only during the period in which the OE · PAD potential determination circuit 20 is outputting the pulse signals oe5 and -oe5 from the one short pulse generation circuit 10. Since the potential of the output pad PADo is monitored, a through current does not flow between the internal power supply voltage VDDIO and the ground through the clock inverter 22 even if the output pad PADo becomes an intermediate potential. As a result, an increase in power consumption is prevented.

Further, the present embodiment also shows the N-MOS transistors 66 and 21 for lowering Vt between the output pad PADo and the N-MOS transistor 67 and between the output pad PADo and the gate of the clock inverter 22. The N-MOS transistor 67 which drives the potential of the output pad PADo, even when the potential of the output pad PADo becomes an external power supply voltage VTT higher than the internal power supply voltage VDDIO, because of the configuration in which the? And the clock inverter 22 which monitors the potential of the output pad PADo are not broken.

Example  2

Next, Example 2 of this invention is described in detail using drawing. In addition, in the following description, about the structure similar to Example 1, the same code | symbol is attached | subjected and the detailed description is abbreviate | omitted. In addition, the structure which is not specifically described is the same as that of Example 1.

In this embodiment, another configuration of the tristate output circuit 1 illustrated in Embodiment 1 is taken as an example.

〔Configuration〕

3 is a circuit diagram showing the configuration of the tristate output circuit 2 according to the present embodiment. As shown in FIG. 3, the tristate output circuit 2 includes a bias circuit 30, a floating well charging circuit 40, a transfer gate 50, a two input NAND circuit 61, and an inverter 62, 72, and 73. ) And two-input NOR circuit 63 and P-MOS transistor 64 (second transistor), P-MOS transistor 65 (first transistor) and P-MOS transistor 71 (third transistor) and N-MOS transistor (66; fourth transistor) and N-MOS transistor 67 (fifth transistor) and a resistor 68, and outputs an input signal a input from the input terminal A from the output pad PADo. In addition, in the tristate output circuit 2, similarly to the tristate output circuit 1 according to the first embodiment, a configuration is provided in which the output is allowed or disallowed based on the output enable signal oe.

In the above configuration, the bias circuit 30, the floating well charging circuit 40, the transfer gate 50, the two-input NAND circuit 61, the inverter 62, the two-input NOR circuit 63, and the P-MOS transistor 64 and 65, the N-MOS transistors 66 and 67, and the resistor 68 are the same as those in the tristate output circuit 1 according to the first embodiment. Therefore, detailed description thereof is omitted in this embodiment.

In the tristate output circuit 2 according to the present embodiment, the one-shot pulse generator circuit 10 in the tristate output circuit 1 according to the first embodiment is eliminated, and the OE / PAD potential determination circuit 20 is eliminated. ) Is replaced by two inverters 72 and 73 connected in series. In addition, the tristate output circuit 2 according to the present embodiment has a configuration in which the tristate output circuit 1 according to the first embodiment has a P- gate whose gate is connected to the output pad PADo via a resistor 68. MOS transistor 71.

In this configuration, the bias circuit 30 operates based on the outputs from the inverters 72 and 73. That is, the bias voltage Vbias for controlling the P-M0S transistor 64 is generated based on the signal level of the enable signal oe, and this is applied to the gate of the P-MOS transistor 64.

Specifically, when the enable signal oe is at the H level, that is, the output is enabled, the inverter 72 outputs the L level, and the inverter 73 outputs the H level. The output of the inverter 72 is each of the P-MOS transistors 35a constituting the N-MOS transistors 31 and 32, the P-MOS transistor 34 and the transfer gate 35 in the bias circuit 30. Is connected to the gate. The output of the inverter 73 is connected to the gates of the N-MOS transistors 33e to 33g in the bias circuit 30 and the gates of the N-MOS transistors 35b constituting the transfer gate 35, respectively. do.

Therefore, in the state where the output is enabled, as in the case where the two-input NOR circuit 24 outputs the L level in the first embodiment and the inverter 25 outputs the H level, in the bias circuit 30 Since the N-MOS transistors 31 and 32 are turned off and the P-MOS transistor 34 and the transfer gate 35 are turned on, an internal power supply voltage VDDIO is applied to the node bias. At this time, the N-MOS transistors 33e to 33g in the bias circuit 30 are turned on. For this reason, the N-MOS transistors 33a to 33d are turned off.

On the other hand, when the enable signal oe is at the L level, that is, the output is disabled, the inverter 72 outputs the H level, and the inverter 73 outputs the L level. Therefore, in this state, the P-MOS transistor in the bias circuit 30 is similar to the state in which the two-input NOR circuit 24 outputs the H level and the inverter 25 outputs the L level in the first embodiment. Since the 34 and the transfer gate 35 are turned off and the N-MOS transistors 31 and 32 and the N-MOS transistors 33a to 33d are turned on, the node bias is twice as large as the internal power supply voltage VDDIO. A bias voltage Vbias (= VDDIO-2Vthn) as low as the threshold voltage Vthn is applied.

As described above, in the present embodiment, the bias circuit 30 is continuously operated in the period in which the enable signal oe is at the L level.

In addition, the P-MOS transistor 71 in the tristate output circuit 2 is connected to the gate of the P-MOS transistor 64, in other words, which switches the potential of the node bias based on the potential of the output pad PADo. It serves as a means for switching the applied voltage to either the bias voltage Vbias or the internal power supply voltage VDDIO.

The P-MOS transistor 71 has a drain connected to an internal power supply voltage VDDIO and a source connected to a node bias, that is, a gate of the P-MOS transistor 64. In addition, the gate of the P-MOS transistor 71 is connected to the output pad PADo through the resistor 68 as described above.

In addition, the back gate (floating well) of the P-MOS transistor 71 is connected to the output of the floating well charging circuit 40. That is, the well potential of the P-MOS transistor 71 is charged to the VDDIO level when the potential of the output pad PADo is equal to or less than VDDIO, and the external power supply voltage, for example, when the potential of the output pad PADo is higher than VDDIO. In the case of (VTT), it is charged to the VTT level.

Therefore, the P-MOS transistor 71 applies the internal power supply voltage VDDIO to the node bias in a period in which the output pad PADo is at a voltage level lower than the internal power supply voltage VDDIO, so that the output pad PADo is internal. In a period that is a voltage level above the power supply voltage VDDIO, the signal is turned off.

As described above, that is, based on the output of the bias circuit 30 and the output of the P-MOS transistor 71, in this embodiment, the enable signal oe is at the L level and the output pad PADo is the internal power supply. In the period at which the voltage level is higher than the voltage VDDIO, the potential of the node bias becomes the bias voltage Vbias (= VDDIO-2Vthn) lower than the internal power supply voltage VDDIO, and in other periods, that is, the enable signal ( In the period where oe) is at the H level and / or in the period when the output pad PADo is at a voltage level equal to or lower than the internal power supply voltage VDDIO, the potential of the node bias becomes the internal power supply voltage VDDIO.

〔action〕

Next, the operation of the tristate output circuit 2 according to the present embodiment will be described. In the following, when the enable signal oe transitions from the H level to the L level, when the external power supply voltage VTT is applied through a pull-up resistor (not shown) to the output pad PADo (this is called 1), and The operation in the case where the output pad PADo becomes an intermediate potential when the enable signal oe is at the L level (this case 2) will be described by way of example, respectively.

Case 1

First, the operation in the case where the external power supply voltage VTT is applied through the pull-up resistor (not shown) to the output pad PADo by the enable signal oe transitions from the H level to the L level will be described as an example.

In the initial state of this operation, the inverter 72 outputs the L level, and the inverter 73 outputs the H level. Therefore, the internal power supply voltage VDDIO output from the bias circuit 30 is applied to the gate of the P-MOS transistor 64.

The well potential of the P-MOS transistor 64 is pulled up to the VDDIO level by the floating well charging circuit 40. Therefore, the P-MOS transistor 64 is turned off after pulling up the source potential, that is, the node pg to the VDDIO level.

Here, when the enable signal oe transitions from the H level to the L level, the output of the two-input NAND circuit 61 becomes H level. As a result, since the H level is applied to the gate of the P-MOS transistor 65 through the transfer gate 50, the output pad PADo becomes in an indefinite state (high Z state). In the description of this operation, the case where the external power supply voltage VTT is applied to the output pad PADo through a pull-up resistor (not shown) is taken as an example. That is, the case where the potential of the output pad PADo is set to the VTT level will be described.

Further, as described above, when the enable signal oe transitions from the H level to the L level, the inverter 72 outputs the H level, and the inverter 73 outputs the L level.

As described above, when the H level is output from the inverter 72 and the L level is output from the inverter 73, the bias circuit 30 turns on the N-MOS transistors 31 and 32 to thereby be larger than the internal power supply voltage VDDIO. The bias voltage Vbias (= VDDIO-2Vthn) as low as twice the threshold voltage Vthn is output to the node bias.

In addition, since the external power supply voltage VTT is applied to the gate, the P-MOS transistor 71 is turned off because the floating well (back gate) is charged to the VTT level by the floating well charging circuit 40. Therefore, the potential of the node bias becomes the bias potential Vbias (= VDDIO-2Vthn).

At this time, the well (back gate) of the P-MOS transistor 64 is charged to the VTT level through the floating well charging circuit 40. For this reason, the P-MOS transistor 64 to which the bias voltage Vbias (= VDDIO-2Vthn) lower than VDDIO is applied to the gate is in a state in which current is easier to pass as compared with when VDDIO is applied to the gate. . Thus, current flows rapidly into the node pg through the resistor 68 and the P-MOS transistor 64. As a result, the gate potential of the node pg, that is, the P-M0S transistor 65 is quickly pulled up to the VTT level. As a result, since the gate potential, the back gate potential, and the drain potential (equivalent to the potential of the output pad PADo) of the P-MOS transistor 65 all become VTT, the P-MOS transistor 65 is turned off. As a result, the current path connecting the output pad PADo and the internal power supply voltage VDDIO is interrupted, so that current flows from the output pad PADo through the P-MOS transistor 65 to the internal power supply voltage VDDIO. Incoming is prevented. In other words, an increase in power consumption is prevented.

In addition, when the potential of the node pg becomes the VTT level, since the source potential, the drain potential, and the well potential of the P-MOS transistor 64 both become the VTT level, the P-MOS transistor 64 is turned off. .

After that, for example, when the potential of the output pad PADo becomes an intermediate potential, since the P-MOS transistor 71 is turned on, the node bias, that is, the gate of the P-MOS transistor 64 has an internal power supply voltage. (VDDIO) is applied. Therefore, even if the potential of the output pad PADo becomes the intermediate potential as described above, the P-MOS transistor 64 remains off. As a result, current flows from the internal power supply voltage VDDIO applied to the two-input NAND circuit 61 to the output pad PADo through the transfer gate 50, the P-MOS transistor 64, and the resistor 68. Is prevented. In other words, an increase in power consumption is prevented.

Case 2

Next, the operation in the case where the output pad PADo becomes an intermediate potential when the enable signal oe is at the L level will be described as an example.

In this operation, since the output of the two-input NAND circuit 61 is at the H level and the output of the two-input NOR circuit 63 is at the L level, the output pad PADo is in a negative state (high Z state). In this operation description, the case where the potential of the output pad PADo becomes an intermediate potential at this time is taken as an example.

The intermediate potential applied to the output pad PADo is applied to the gate of the P-MOS transistor 71 through the resistor 68. At this time, since the well potential of the P-MOS transistor 71 is charged to the VDDIO level by the floating well charging circuit 40, the P-MOS transistor 71 is turned on. As a result, an internal power supply voltage VDDIO is applied to the node pg, that is, the gate of the P-MOS transistor 64.

At this time, the well potential of the P-MOS transistor 64 is charged to the VDDIO level by the floating well charging circuit 40. Therefore, even if an intermediate potential is applied to the drain of the P-MOS transistor 64, the P-MOS transistor 64 does not turn on, and as a result, outputs through the P-MOS transistor 64 and the resistor 68. No DC current flows into the pad (PADo). As a result, an increase in power consumption is prevented.

[Action effect]

As described above, the present embodiment has a bias circuit in a case where the potential of the output pad PADo becomes a voltage VTT higher than the internal power supply voltage VDDIO in the period in which the enable signal oe is at the L level. Since the operation of 30 causes the voltage (bias voltage Vbias = VDDIO-2Vthn) lower than the internal power supply voltage VDDIO to be applied to the gate of the P-MOS transistor 64, the phosphorus is similar to that of the first embodiment. The P-MOS transistor 65 formed between the output pad PADo and the internal power supply voltage VDDIO via the resistor 68 and the P-MOS transistor 64 when the enable signal oe transitions to the L level. The gate potential of can be quickly pulled up to the external supply voltage (VTT). As a result, it is possible to prevent current from flowing from the output pad PADo to the internal power supply voltage VDDIO side through the P-MOS transistor 65 at the time of pull-up, thereby preventing an increase in power consumption.

Further, in this embodiment, the bias circuit 30 operates only during a period where the enable signal oe is at the L level and the output pad PADo is at a voltage level higher than the internal power supply voltage VDDIO, i.e., P- The bias voltage Vbias (= VDDIO-2Vthn) for making the MOS transistor 64 easily flow current is output from the bias circuit 30, and other than this period, that is, the enable signal oe is H level. In a period where the period and / or the output pad PADo is at a voltage level equal to or lower than the internal power supply voltage VDDIO, the gate of the P-MOS transistor 64 is output from the bias circuit 30 or the P-MOS transistor 71. The internal power supply voltage VDDIO is applied. Therefore, after the output pad PADo becomes negative, when the potential of the output pad PADo becomes, for example, an intermediate potential, the internal power supply voltage VDDIO is applied to the gate of the P-MOS transistor 64. For this reason, even if the potential of the output pad PADo becomes, for example, an intermediate potential after the output pad PADo is in a negative state, the P-MOS transistor 64 is not turned on. Thus, even in the above situation, the current path passing through the transfer gate 50, the P-MOS transistor 64, and the resistor 68 from the internal power supply voltage VDDIO applied to the two-input NAND circuit 61 is obtained. It can be prevented from forming. That is, the current can be prevented from flowing out to the output pad PADo. As a result, increase in power consumption can be prevented.

In addition, since the present embodiment does not have a configuration in which the potential of the output pad PADo is received at the gate of a Complementary Metal 0xide Semiconductor (C-MOS) such as an inverter, for example, the potential of the output pad PADo is set to an example. For example, even when it is at an intermediate potential, no through current flows between the internal power supply voltage (VDDIO) and the ground. As a result, an increase in power consumption is prevented.

Furthermore, in the present embodiment, since the N-MOS transistor 66 for lowering Vt is formed between the output pad PADo and the N-MOS transistor 67, the potential of the output pad PADo is equal to the internal power supply voltage. Even when the external power supply voltage VTT is higher than VDDIO, the N-MOS transistor 67 which drives the potential of the output pad PADo is not damaged.

In addition, according to the present embodiment, a tristate output circuit having the above effects can be realized with a small number of circuits. For example, the tristate output circuit 2 according to the present embodiment realizes the same effect with a smaller number of circuits than the tristate output circuit 1 according to the first embodiment.

Example  3

Next, Example 3 of this invention is described in detail using drawing. In addition, in the following description, about the structure similar to Example 1 or 2, the same code | symbol is attached | subjected and the detailed description is abbreviate | omitted. In addition, the structure which is not specifically described is the same as that of Example 1 or Example 2.

In the present embodiment, the case where the allowable input circuit 3 which is an input interface (which is also an input / output circuit) is configured using the circuit configuration of the tristate output circuit 2 illustrated in the second embodiment will be described as an example.

〔Configuration〕

4 is a circuit diagram showing the configuration of the allowable input circuit 3 according to the present embodiment. As shown in Fig. 4, the allowable input circuit 3 includes the bias circuit 30, the floating well charging circuit 40, the transfer gate 50, the two input NAND circuit 61, the inverters 72, 73, 82 and 83 and two-input NOR circuit 63 and P-MOS transistor 64 (second transistor), P-MOS transistor 65W (first transistor) and P-MOS transistor 71 and N-MOS transistor 66; An input signal pad input from an input pad PADi (input section) having a fourth transistor), an N-MOS transistor 67 (fifth transistor), and an N-MOS transistor 81 (third transistor) and a resistor 68; Output from the output terminal Y.

In the above configuration, the inverters 72 and 73, the bias circuit 30, the floating well charging circuit 40, and the transfer gate 50 are the same as those in the tristate output circuit 2 according to the second embodiment. Do.

That is, the bias circuit 30 has the N-MOS transistors 31, 32, 33a to 33g, the P-MOS transistor 34 and the transfer gate 35 similarly to the second embodiment, and the inverters 72 and 73. The bias voltage Vbias is applied to the node bias based on the voltage level output from the. However, in this embodiment, the internal power supply voltage VDDIO (predetermined voltage) is connected to the input of the inverter 72 instead of the input terminal OE (see FIG. 1 or FIG. 3). Therefore, the inverter 72 according to the present embodiment always outputs the L level, and the inverter 73 always outputs the H level. As a result, the bias circuit 30 always applies an internal power supply voltage VDDIO to the node bias, that is, the gate of the P-MOS transistor 64.

In addition, the floating well charging circuit 40 has three P-MOS transistors 41 to 43 similarly to the second embodiment, and the back gates of the P-MOS transistors 64, 65W, and 71 are set to the VDDIO level or the input pad. Charge to the external power supply voltage (VTT (> VDDIO)) level applied to (PADi).

In addition, the transfer gate 50 has a P-MOS transistor 51 and an N-MOS transistor 52 similarly to the second embodiment, and is based on the potential of the input pad PADi of the two-input NAND circuit 61. It conducts / blocks between the output and the gate of the P-MOS transistor 65W.

Explain other configurations. In the allowable input circuit 3 according to the present embodiment, as shown in FIG. 4, an input of one of the two-input NAND circuits 61 is used instead of the input terminal A (see FIG. 1 or FIG. 3). The power supply voltage VDDIO is connected. The output of the inverter 82 described later is connected to the other input of the two-input NAND circuit 61. Therefore, the two-input NAND circuit 61 outputs the L level only when the output of the inverter 82 is the H level.

In the allowable input circuit 3 according to the present embodiment, the inverter 62 in the tristate output circuit 1 or 2 is deleted, and the inverter 62 is connected to one input of the two-input NOR circuit 63. Instead of the output (see Fig. 1 or 3), the internal power supply voltage VDDIO is connected. The output of the inverter 82 described later is connected to the other input of the two-input NOR circuit 63 similarly to the two-input NAND circuit 61, but since the internal power supply voltage VDDIO is applied to one of the inputs, The two-input NOR circuit 63 always outputs an L level.

The output of the two-input NAND circuit 61 is connected to the gate of the P-MOS transistor 65W for driving the potential of the input pad PADi via the transfer gate 50, similarly to the first embodiment or the second embodiment. do.

This P-MOS transistor 65W has a configuration corresponding to the P-MOS transistor 65 in the first or second embodiment. However, in the present embodiment, for example, the P-MOS transistor 65W having a shorter gate width and a longer gate length is employed as compared with the P-MOS transistor 65 employed in the first or second embodiment. .

In addition, the gate width being narrow means that the current flowing through the P-M0S transistor is lower than the case in which the gate width is wide (however, the capacity for the same gate potential, hereinafter referred to as driving force) is low. In addition, the longer gate length means that the driving force of the P-M0S transistor is lower than that of the short gate length. That is, in this embodiment, a P-MOS transistor 65W having a relatively low driving force is used.

By using such a P-MOS transistor 65W, a relatively large load can be formed between the internal power supply voltage VDDIO and the input pad PADi, and thus the input pad PADi through the P-MOS transistor 65W. ), The current flowing from the internal power supply voltage VDDIO to the input pad PADi through the P-MOS transistor 65W can be reduced.

In addition, the output of the two-input NOR circuit 63 is connected to the gate of the N-MOS transistor 67 for driving the potential of the input pad PADi, similarly to the first embodiment or the second.

In addition, as shown in FIG. 4, the input pad PADi is connected to the input of the inverter 82 through the N-MOS transistor 81. In other words, an inverter 82 is formed between the input pad PADi and the output terminal Y.

In the N-MOS transistor 81 formed between the input pad PADi and the inverter 82, the internal power supply voltage VDDIO is always applied to the gate. That is, it is always on. This N-MOS transistor 81 is a protection element for preventing the breakage of the N-MOS transistor in particular in the inverter 82 formed later in view of the input pad PADi. That is, it is a circuit element for realizing the function which makes it possible to apply external power supply voltage VTT among the permissible functions by this embodiment.

The inverter 82 is monitoring the potential of the input pad PADi via the resistor 68, but in particular the external power supply voltage VTT whose potential of the output pad PADi is higher than the internal power supply voltage VDDIO (= 3.3V). (= 5V)), when the potential of the input pad PADi is applied to the gate of the N-MOS transistor in the inverter 82 as it is, the N-MOS transistor 67 or the N- described in the first embodiment. Like the MOS transistor 22c, this N-MOS transistor may not withstand the external power supply voltage VTT and may be damaged.

Thus, as shown in FIG. 4, the normally turned on N-MOS transistor 81 is formed between the input pad PADi and the inverter 82. Thus, since the Vt drop occurs in the N-MOS transistor 81, the potential applied to the gate of the N-MOS transistor constituting the inverter 82 is greater than the external voltage VTT applied to the input pad PADi. Lowers.

In this way, by forming the N-MOS transistor 81, it is avoided that the potential difference of the input pad PADi is applied to the gate of the N-MOS transistor constituting the inverter 82 as it is. As a result, the inverter 82 In particular, breakage of the N-MOS transistor is prevented.

The output of the inverter 82 formed at the rear end of the N-MOS transistor 81 is, as described above, the other input of the two-input NAND circuit 61 and the other input of the two-input NOR circuit 63. Are connected to each. Therefore, the two-input NAND circuit 61 outputs the L level only when the data input from the input pad PADi is an H level (for example, data of "1"). However, even when the H level (for example, "1" data) is input to the input pad PADi from the two-input NOR circuit 63, the L level (for example, "0" data) is input. If so, all L levels are output. Therefore, the N-MOS transistor 67 in which the output of the two-input NOR circuit 63 is connected to the gate is always turned off.

Further, the output of the inverter 82, that is, the data input from the input pad PADi is returned to the original data (data that is not inverted) by passing through the inverter 83, and then from the output terminal Y. Is output.

Since other configurations are the same as those in the first embodiment or the second embodiment, detailed descriptions are omitted here.

〔action〕

Next, the operation of the allowable input circuit 3 according to the present embodiment will be described. Hereinafter, when the L level signal (for example, "0" data) is input to the input pad PADi (called "1" in this case), and the H level signal (for example, " 1 ”data) (in this case 2) and when the external power supply voltage (VTT) higher than the internal power supply voltage (VDDIO) is applied to the input pad PADi (this is called 3). The operation will be described with examples, respectively.

Case 1

First, the operation in the case where an L level signal (for example, data of "0") is input to the input pad PADi will be described as an example.

In this operation, since the L level is input to the inverter 82 through the resistor 68 and the N-MOS transistor 81, the inverter 82 outputs the H level. Therefore, the two-input NAND circuit 61 outputs the L level. As a result, the L level is applied to the gate of the P-MOS transistor 65W through the transfer gate 50, so that the P-MOS transistor 65W is turned on. The output of the inverter 83, that is, the L level, is output from the output terminal Y.

Here, the P-MOS transistor 65W according to the present embodiment has a relatively low driving force as described above. Therefore, even if the input pad PADi is in the high Z state, for example, only a small amount of current flows to the P-MOS transistor 65W having a low driving force. For this reason, only a small amount of current flows from the power supply voltage VDDIO to the input pad PADi through the P-MOS transistor 65W, whereby the input pad PADi can be slowly pulled up to the VDDIO level.

Case 2

 Next, an operation in the case where a signal of H (VDDIO) level (for example, "1" data) is input to the input pad PADi will be described as an example.

In this operation, since the H level is input to the inverter 82 through the resistor 68 and the N-MOS transistor 81, the inverter 82 outputs the L level. Therefore, the two-input NAND circuit 61 outputs the H level. Thus, the H level is applied to the gate of the P-MOS transistor 65W through the transfer gate 50, so that the P-MOS transistor 65W is turned off. The output of the inverter 83, that is, the H level, is output from the output terminal Y.

Case 3

Next, an operation in the case where an external power supply voltage VTT higher than the internal power supply voltage VDDIO is applied to the input pad PADi will be described as an example.

In this operation, since the H level is input to the inverter 82 through the resistor 68 and the N-MOS transistor 81, the inverter 82 outputs the L level. Therefore, the two-input NAND circuit 61 outputs the H level. Thus, the H level is applied to the gate of the P-MOS transistor 65W through the transfer gate 50, so that the P-MOS transistor 65W is turned off. In the output terminal Y, the output of the inverter 83, that is, the H level, is output.

Even in such a case, since the P-MOS transistor 65W having a low driving force is formed between the power supply voltage VDDIO and the input pad PADi, only a small amount of current flows in the P-MOS transistor 65W. For example, even if an external power supply voltage VTT higher than the internal power supply voltage VDDIO is applied to the input pad PADi, since the gate and the floating well of the P-MOS transistor 65W are both charged to the VTT level, P The MOS transistor 65W is turned off. For this reason, no current flows from the input pad PADi through the P-MOS transistor 65W to the power supply voltage VDDIO. As a result, since the current flowing from the input pad PADi to the internal power supply voltage VDDIO through the P-MOS transistor 65W can be reduced, an increase in power consumption can be suppressed.

In addition, when the potential of the node pg becomes the VTT level, since the source potential, the drain potential, and the well potential of the P-MOS transistor 64 both become the VTT level, the P-MOS transistor 64 is turned off. .

[Action effect]

As described above, since the present embodiment has a configuration in which a P-MOS transistor 65W having a low driving force is formed between the power supply voltage VDDIO and the input pad PADi, for example, the input pad PADi is in a high Z state. Even if it is, only a small amount of current flows to the P-MOS transistor 65W having a low driving force. For this reason, only a small amount of current flows from the power supply voltage VDDIO to the input pad PADi through the P-MOS transistor 65W, whereby the input pad PADi can be slowly pulled up to the VDDIO level.

In this embodiment, since the P-MOS transistor 65W having a low driving force is formed between the power supply voltage VDDIO and the input pad PADi, only a small amount of current flows through the P-MOS transistor 65W. Do not. For this reason, even if an external power supply voltage VTT higher than the internal power supply voltage VDDIO is applied to the input pad PADi, for example, both the gate and the floating well of the P-MOS transistor 65W are charged to the VTT level. As a result, the P-MOS transistor 65W is turned off. For this reason, no current flows from the input pad PADi through the P-MOS transistor 65W to the power supply voltage VDDIO. As a result, since the current flowing from the input pad PADi to the internal power supply voltage VDDI0 through the P-MOS transistor 65W can be reduced, an increase in power consumption can be suppressed.

In addition, in this embodiment, even after the external power supply voltage VTT is applied to the input pad PADi higher than the internal power supply voltage VDDIO, even if the potential of the output pad PADi becomes an intermediate potential, for example, the node bias That is, since the internal power supply voltage VDDIO is applied to the gate of the P-MOS transistor 64 so that it is turned off, it transfers from the internal power supply voltage VDDIO applied to the two-input NAND circuit 61. No current flows into the input pad PADi through the gate 50, the P-MOS transistor 64, and the resistor 68, so that an increase in power consumption is prevented.

In addition, according to the present embodiment, the allowable input circuit having the above effects can be realized with a small number of circuits.

Example  4

Next, Example 4 of this invention is described in detail using drawing. In addition, in the following description, about the structure similar to any one of Example 1 thru | or 3, the same code | symbol is attached | subjected and the detailed description is abbreviate | omitted. In addition, the structure which is not specifically described is the same as that of any one of Examples 1-3.

In the present embodiment, the tristate output circuit 1 illustrated in the first embodiment and the allowable input circuit 3 illustrated in the third embodiment are used to configure a bidirectional circuit, which is an input / output interface (this is also an input / output circuit) as an example. Listen and explain.

〔Configuration〕

5 is an equivalent circuit diagram showing the configuration of the bidirectional circuit 4 according to the present embodiment. As shown in FIG. 5, the bidirectional circuit 4 has the tristate output circuit 1 according to the first embodiment and the allowable input circuit 3 according to the third embodiment, and the output pad of the tristate output circuit 1. It has a structure in which PADo and an input pad PADi of the allowable input circuit 3 are connected. This connecting portion also functions as an input / output pad (PAD).

The configuration of the tristate output circuit 1 is the same as that of the first embodiment. The configuration of the allowable input circuit 3 is also the same as that of the third embodiment. Therefore, detailed description thereof is omitted here.

〔action〕

In addition, since the operation | movement of the tristate output circuit 1 in the bidirectional circuit 4 by this embodiment is the same as the operation demonstrated in Example 1, description is abbreviate | omitted here. However, the enable signal oe becomes L level, for example, when the permissible input circuit 3 operates. Thus, the operation of the tristate output circuit 1 and the operation of the allowable input circuit 3 can be separated. In addition, since the operation | movement of the allowable input circuit 3 in the bidirectional circuit 4 is the same as the operation demonstrated in Example 3, description is abbreviate | omitted here.

[Action effect]

As described above, according to the present embodiment, by combining the tristate output circuit 1 according to the first embodiment and the allowable input circuit 3 according to the third embodiment, the bidirectional circuit 4 having these effects can be realized. Can be.

Example  5

Next, Example 5 of this invention is described in detail using drawing. In addition, in the following description, about the structure similar to any one of Embodiment 1-4, the same code | symbol is attached | subjected and the detailed description is abbreviate | omitted. In addition, the structure which is not specifically described is the same as that of any one of Examples 1-4.

In the present embodiment, a case where a bidirectional circuit (this is also an input / output circuit), which is an input / output interface, using the tristate output circuit 2 illustrated in the second embodiment and the allowable input circuit 3 illustrated in the third embodiment is used as an example. Listen and explain.

〔Configuration〕

6 is an equivalent circuit diagram showing the configuration of the bidirectional circuit 5 according to the present embodiment. As shown in FIG. 6, the bidirectional circuit 5 has the tristate output circuit 2 according to the second embodiment and the allowable input circuit 3 according to the third embodiment, and the output of the tristate output circuit 2. The pad PADo and the input pad PADi of the allowable input circuit 3 are connected. This connecting portion also functions as an input / output pad (PAD).

The configuration of the tristate output circuit 2 is the same as that of the second embodiment. The configuration of the allowable input circuit 3 is also the same as that of the third embodiment. Therefore, detailed description thereof is omitted here.

〔action〕

In addition, since the operation of the tristate output circuit 2 in the bidirectional circuit 5 according to the present embodiment is the same as the operation described in the second embodiment, the description is omitted here. However, the enable signal oe becomes L level, for example, when the permissible input circuit 3 operates. Thus, the operation of the tristate output circuit 2 and the operation of the allowable input circuit 3 can be separated. In addition, since the operation | movement of the allowable input circuit 3 in the bidirectional circuit 5 is the same as the operation demonstrated in Example 3, description is abbreviate | omitted here.

[Action effect]

As described above, according to the present embodiment, by combining the tristate output circuit 2 according to the second embodiment and the allowable input circuit 3 according to the third embodiment, the bidirectional circuit 5 having these effects can be realized. Can be.

Example  6

Next, Example 6 of this invention is described in detail using drawing. In addition, in the following description, about the structure similar to any one of Embodiment 1-5, the same code | symbol is attached | subjected and the detailed description is abbreviate | omitted. In addition, about the structure which is not specifically described, it is the same as that of Examples 1-5.

The bidirectional circuits 4 to 8 according to any one of the above embodiments 4 to 6 are incorporated in the single-chip semiconductor input / output device 9 as shown in Fig. 7A or 7B. This semiconductor input / output device 9 is, for example, a semiconductor in which a bidirectional circuit 104 composed of a conventional input circuit 101 and an output circuit 103 is incorporated, as shown in Figs. 7 (a) or 7 (b). It can be used in combination with the input / output device 109 or the semiconductor input / output device 110 in which the conventional output circuit 101 is incorporated.

In addition, the said Examples 1-6 are only the examples for implementing this invention, This invention is not limited to these, A various deformation | transformation of these Examples is within the scope of this invention, It is apparent from the above description that various other embodiments are possible within the scope of the invention.

According to the present invention, an input / output circuit and a semiconductor input / output device capable of preventing an increase in power consumption can be realized. That is, based on the present invention, for example, an input / output circuit capable of quickly pulling up the output to an external voltage and preventing a through-current from flowing to the inverter receiving the output even when the output is in a negative state; A semiconductor input / output device can be realized.

Claims (26)

A first transistor for driving an output unit based on a predetermined signal, A second transistor for controlling the potential of the node connected to the gate of the first transistor, A pulse generating circuit for outputting a pulse having a predetermined time width when the signal level of the predetermined signal has transitioned, and And a bias circuit for generating a bias voltage for controlling the second transistor and applying the bias voltage to a gate of the second transistor in a period in which the pulse is output. The method of claim 1, The first and second transistors are p-channel transistors, And the bias circuit outputs the bias voltage having a potential lower than an internal voltage. The method of claim 1, The first and second transistors are p-channel transistors, The bias circuit has two n-channel transistors connected between an internal voltage and a gate of the second transistor, and in a period in which the pulse is output, by the threshold voltages of the two n-channel transistors rather than an internal voltage. Outputting the bias voltage low. The method according to any one of claims 1 to 3, And the bias circuit is configured to apply an internal voltage to the gate of the second transistor in a period where the pulse is not being output. The method according to any one of claims 1 to 3, And a potential determination output circuit for determining a potential of the output section in the period during which the pulse is output, and outputting a voltage for outputting the bias voltage from the bias circuit based on the determination result, And the bias circuit outputs the bias voltage based on the voltage output from the potential determination output circuit. The method according to any one of claims 1 to 3, And a potential determination output circuit for determining a potential of the output section in the period during which the pulse is output, and outputting a voltage for outputting the bias voltage from the bias circuit based on the determination result, And the bias circuit applies an internal voltage to the gate of the second transistor based on the voltage output from the potential determination output circuit. The method of claim 5, And the potential determination output circuit determines a potential of the output unit by using a clock inverter operating only during a period in which the pulse is output. The method of claim 5, The potential determination output circuit has at least three transistors connected in series between an internal voltage and a ground potential, The pulse generating circuit includes: a first inverter formed at an input terminal, an exclusive AND circuit formed at an output terminal, an odd number of second inverters formed in series between an output of the first inverter and one input of the exclusive AND circuit; A third inverter connected to the output of said exclusive AND circuit, At least one of the three transistors is connected to an output of the exclusive AND circuit or to an output of the third inverter, thereby blocking the interruption between an internal voltage and a ground potential in a period when the pulse is not being output. Input and output circuit characterized in. The method of claim 6, And an n-channel transistor formed at an input terminal of said clock inverter. The method according to any one of claims 1 to 7, 9, The pulse generating circuit includes an odd number of second inverters formed in series between a first inverter formed at an input terminal, an exclusive AND circuit formed at an output terminal, and an input of one of the output of the first inverter and the exclusive AND circuit. An input-output circuit characterized by having. The method according to any one of claims 1 to 10, An n-channel third transistor for driving an output unit based on a predetermined signal, and And an n-channel fourth transistor formed between the third transistor and the output unit. The method according to any one of claims 1 to 11, The second transistor is formed on a floating well substrate, And a floating well charging circuit for charging the floating well of the second transistor based on the potential of the output. A first transistor for driving an output unit based on a predetermined signal, A second transistor for controlling the potential of the node connected to the gate of the first transistor, A bias circuit for generating a bias voltage for controlling the second transistor based on the signal level of the predetermined signal, and applying the bias voltage to a gate of the second transistor, and And a third transistor for switching the voltage applied to the gate of the second transistor based on the potential of the output unit. The method of claim 13, The first and second transistors are p-channel transistors, And the bias circuit outputs the bias voltage having a potential lower than an internal voltage. The method of claim 13, The first and second transistors are p-channel transistors, The bias circuit has two n-channel transistors connected between an internal voltage and a gate of the second transistor, and based on the signal level of the predetermined signal, threshold voltages of the two n-channel transistors rather than an internal voltage. Outputting the bias voltage as low as possible. The method according to any one of claims 13 to 15, And the third transistor converts a voltage applied to a gate of the second transistor into an internal voltage when the potential of the output unit is lower than an internal voltage. The method according to any one of claims 13 to 16, An n-channel fourth transistor for driving an output unit based on a predetermined signal, and And an n-channel fifth transistor formed between the fourth transistor and the output unit. The method according to any one of claims 13 to 17, The second transistor is formed on a floating well substrate, And a floating well charging circuit for charging the floating well of the second transistor based on the potential of the output. A first transistor connected to an input of a signal, A second transistor for controlling the potential of the node connected to the gate of the first transistor, and And a bias circuit for generating a bias voltage for controlling the second transistor based on a predetermined voltage, and applying the bias voltage to the gate of the second transistor. The method of claim 19, An inverter formed between the input unit and the output terminal, An exclusive AND circuit, in which an internal voltage is applied to one input, and an output of the inverter is connected to the other input, and And a transfer gate formed between the gate of the first transistor and the exclusive AND circuit, and conducting / blocking a connection between the gate of the first transistor and the exclusive AND circuit based on a potential of the input unit. I / O circuit. The method of claim 20, And an n-channel third transistor formed between the input unit and the inverter. The method according to any one of claims 19 to 21, An n-channel fourth transistor connected to the input unit, and And an n-channel fifth transistor formed between the third transistor and the output unit. The method according to any one of claims 19 to 22, The first transistor has a smaller gate width and a longer gate length than the second transistor. The method according to any one of claims 19 to 23, The second transistor is formed on a floating well substrate, And a floating well charging circuit for charging the floating well of the second transistor based on the potential of the input unit. The input-output circuit according to any one of claims 1 to 18, and An input / output circuit comprising the input / output circuit according to any one of claims 19 to 24. At least one of the said input-output circuit as described in any one of Claims 1-18, and the said input-output circuit as described in any one of Claims 19-24 was formed on the chip. .

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