KR20060058545A - Method for manufacturing of semiconductor device - Google Patents

Method for manufacturing of semiconductor device Download PDF

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Publication number
KR20060058545A
KR20060058545A KR1020040097622A KR20040097622A KR20060058545A KR 20060058545 A KR20060058545 A KR 20060058545A KR 1020040097622 A KR1020040097622 A KR 1020040097622A KR 20040097622 A KR20040097622 A KR 20040097622A KR 20060058545 A KR20060058545 A KR 20060058545A
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South Korea
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nitride film
etch stop
isolation layer
manufacturing
forming
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KR1020040097622A
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Korean (ko)
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차한섭
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매그나칩 반도체 유한회사
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Publication of KR20060058545A publication Critical patent/KR20060058545A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

본 발명에 따른 반도체 소자의 제조 방법은 반도체 기판의 소자 분리막 상부에만 식각 정지 질화막을 형성하여 상기 소자 분리막을 형성하는 갭필 산화막의 손상을 방지하며, 스트레스에 의한 소자 특성의 변화를 억제하고 상기 식각 정지 질화막에 의한 중수소 열처리 공정의 방해를 방지하여 소자의 신뢰성을 향상시키는 기술을 나타낸다. The method of manufacturing a semiconductor device according to the present invention forms an etch stop nitride film only on the device isolation layer of a semiconductor substrate to prevent damage to the gapfill oxide layer forming the device isolation layer, to suppress the change in device characteristics due to stress and to stop the etch stop. A technique for improving the reliability of the device by preventing interference of the deuterium heat treatment process by the nitride film.

Description

반도체 소자의 제조 방법{METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}Method of manufacturing a semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

도 1a 및 도 1b는 종래 기술에 따른 반도체 소자의 제조 방법 및 그 문제점을 도시한 단면도들.1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device and a problem thereof according to the prior art.

도 2a 및 도 2b는 종래 기술에 따른 반도체 소자의 제조 방법 및 그 문제점을 도시한 단면도들.2A and 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device and a problem thereof according to the prior art.

도 3a 내지 도 3e는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도들. 3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

< 도면의 주요 부분에 대한 부호 설명 ><Explanation of Signs of Major Parts of Drawings>

1, 10, 100 : 반도체 기판 2, 20, 110 : 소자 분리막1, 10, 100: semiconductor substrate 2, 20, 110: device isolation film

3, 85, 185 : 층간 절연막 4, 90, 190 : 콘택3, 85, 185: interlayer insulating film 4, 90, 190: contact

30 : 게이트 산화막 40 : 게이트 폴리 30: gate oxide film 40: gate poly

50, 130 : LDD 산화막 60, 140 : LDD 질화막 50, 130: LDD oxide film 60, 140: LDD nitride film

70, 150 : 소스/드레인 영역 80, 170 : 식각 정지 질화막 70, 150: source / drain regions 80, 170: etch stop nitride film

120 : 게이트 전극 160 : 살리사이드막 120 gate electrode 160 salicide film

180 : 감광막 패턴 180: photosensitive film pattern

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 반도체 기판의 소자분리막 상부에만 식각 정지 질화막을 형성하여 상기 소자 분리막을 형성하는 갭필 산화막의 손상을 방지하며, 스트레스에 의한 소자 특성의 변화를 억제하고 상기 식각 정지 질화막에 의한 중수소 열처리 공정의 방해를 방지하여 소자의 신뢰성을 향상시키는 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, to form an etch stop nitride film only on the device isolation film of the semiconductor substrate to prevent damage to the gap fill oxide film forming the device isolation film, to suppress the change in device characteristics due to stress The present invention relates to a method for manufacturing a semiconductor device which prevents interference of a deuterium heat treatment process by an etch stop nitride film and improves device reliability.

도 1a 및 도 1b는 종래 기술에 따른 반도체 소자의 제조 방법 및 그 문제점을 도시한 단면도들이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device and a problem thereof according to the prior art.

도 1a을 참조하면, 소자 분리막(2)이 형성된 반도체 기판(1)의 활성 영역에 콘택(4)을 형성한다. Referring to FIG. 1A, a contact 4 is formed in an active region of a semiconductor substrate 1 on which an isolation layer 2 is formed.

도 1b를 참조하면, 종래 기술에 따라 콘택(4)을 형성하는 과정에서 콘택(4)이 오정렬되면서 산화막으로 형성된 소자 분리막(2)이 과도 식각되어 'A'와 같이 손상되는 문제점이 있다. Referring to FIG. 1B, in the process of forming the contact 4 according to the related art, the contact isolation layer is misaligned and the device isolation layer 2 formed of an oxide film is excessively etched to damage such as 'A'.

최근에는 이러한 소자 분리막의 손상을 방지하기 위해 도 2a와 같이 반도체 기판 상부에 식각 정지 질화막을 형성하고 콘택을 형성하는 방법을 사용한다. Recently, in order to prevent damage to the device isolation layer, a method of forming an etch stop nitride film and forming a contact on the semiconductor substrate as shown in FIG. 2A is used.

도 2a 및 도 2b는 종래 기술에 따른 반도체 소자의 제조 방법 및 그 문제점을 도시한 단면도들이다.2A and 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device and a problem thereof according to the prior art.

도 2a을 참조하면, 반도체 기판(10) 상부에 소자 분리막(20) 및 게이트 전극을 형성한다. 이때, 상기 게이트 전극은 게이트 산화막(30) 및 게이트 폴리(40)로 구성되는 것이 바람직하다. Referring to FIG. 2A, an isolation layer 20 and a gate electrode are formed on the semiconductor substrate 10. In this case, the gate electrode preferably includes a gate oxide layer 30 and a gate poly 40.

게이트 전극 측벽에 LDD 산화막(50) 및 LDD 질화막(60)을 형성하고 식각하여 LDD 스페이서를 형성한 후 이온 주입을 수행하여 소스/드레인 영역(70)을 형성한다. The LDD oxide film 50 and the LDD nitride film 60 are formed on the sidewalls of the gate electrode and etched to form LDD spacers, and then ion implantation is performed to form the source / drain region 70.

다음에 상기 게이트 전극을 포함한 반도체 기판(10) 전면에 식각 정지 질화막(80)을 형성한다. Next, an etch stop nitride film 80 is formed on the entire surface of the semiconductor substrate 10 including the gate electrode.

이때, 식각 정지 질화막(80)은 콘택을 형성하는 단계에서 오정렬이 발생할 경우 소자 분리막(20)을 구성하는 갭필 산화막이 과도 식각되는 것을 방지하기 위하여 형성하는 것이 바람직하다. In this case, the etch stop nitride film 80 may be formed to prevent excessive etching of the gapfill oxide film constituting the device isolation layer 20 when misalignment occurs in the forming of the contact.

도 2b를 참조하면, 반도체 기판(10)의 활성 영역상에 접속되는 콘택(90)을 형성한다. Referring to FIG. 2B, a contact 90 is formed on the active region of the semiconductor substrate 10.

상술한 종래 기술에 따른 반도체 소자의 제조 방법에서, 반도체 기판 상부에 형성된 식각 정지 질화막은 하부의 트랜지스터에 강한 스트레스를 인가하여 캐리어의 이동도를 변경시키기 때문에 소자의 특성이 변하게 되며, 소자의 신뢰성 개선을 위해 H2 열처리 공정 대신 수행되는 중수소 열처리 공정시 상기 중수소 분자가 확산하는 것을 방해하여 신뢰성 개선에 문제점이 있다. In the method of manufacturing a semiconductor device according to the related art, the etch stop nitride film formed on an upper portion of a semiconductor substrate changes the mobility of a carrier by applying a strong stress to a lower transistor, thereby changing characteristics of the device and improving reliability of the device. In order to prevent diffusion of the deuterium molecules in the deuterium heat treatment process performed in place of the H 2 heat treatment process, there is a problem in improving reliability.

상기 문제점을 해결하기 위하여, 반도체 기판의 소자 분리막 상부에만 식각 정지 질화막을 형성하여 갭필 산화막의 손상을 방지하며, 스트레스에 의한 소자 특 성의 변화를 억제하고 상기 식각 정지 질화막에 의해 중수소 열처리 공정이 방해되는 것을 방지하여 반도체 소자의 신뢰성을 향상시키는 반도체 소자의 제조 방법을 제공하는 것을 그 목적으로 한다. In order to solve the above problems, an etch stop nitride film is formed only on the device isolation layer of the semiconductor substrate to prevent damage to the gapfill oxide film, to suppress the change of device characteristics due to stress, and to inhibit the deuterium heat treatment process by the etch stop nitride film. It aims at providing the manufacturing method of the semiconductor element which prevents that and improves the reliability of a semiconductor element.

본 발명에 따른 반도체 소자의 제조 방법은Method for manufacturing a semiconductor device according to the present invention

반도체 기판 상부에 소자 분리막 및 게이트 전극을 형성하는 단계와,Forming an isolation layer and a gate electrode on the semiconductor substrate;

상기 게이트 전극 측벽에 LDD 스페이서를 형성하고 이온 주입을 수행하여 소스/드레인 영역을 형성하는 단계와,Forming an LDD spacer on the sidewall of the gate electrode and performing ion implantation to form a source / drain region;

상기 소자 분리막 및 게이트 전극을 포함하는 반도체 기판 전면에 식각 정지 질화막을 형성하는 단계와,Forming an etch stop nitride film on an entire surface of the semiconductor substrate including the device isolation layer and the gate electrode;

상기 소자 분리막 상부에 감광막 패턴을 형성하는 단계와,Forming a photoresist pattern on the device isolation layer;

상기 감광막 패턴을 마스크로 상기 식각 정지 질화막을 제거하여 상기 소자 분리막 상부에만 상기 식각 정지 질화막을 남기는 단계와,Removing the etch stop nitride film using the photoresist pattern as a mask to leave the etch stop nitride film only on the device isolation layer;

상기 소스/드레인 영역에 접속되는 콘택을 형성하는 단계Forming a contact connected to the source / drain region

를 포함하는 것을 특징으로 한다. Characterized in that it comprises a.

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다. Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

도 3a 내지 도 3e는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도들이다. 3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

도 3a를 참조하면, 반도체 기판(100) 상부에 소자 분리막(110) 및 게이트 전 극(120)을 형성하고, 게이트 전극(120) 측벽에 LDD 산화막(130) 및 LDD 질화막(140)으로 구성된 LDD 스페이서(130, 140)를 형성한다. Referring to FIG. 3A, a device isolation layer 110 and a gate electrode 120 are formed on a semiconductor substrate 100, and an LDD including an LDD oxide film 130 and an LDD nitride film 140 on a sidewall of the gate electrode 120. Spacers 130 and 140 are formed.

다음에 상기 LDD 스페이서(130, 140)를 마스크로 이온 주입을 수행하여 소스/드레인 영역(150) 및 살리사이드막(160)을 형성한다. 여기서, 게이트 전극(120)은 게이트 산화막, 게이트 폴리 및 살리사이드막의 적층 구조로 구성되는 것이 바람직하다. Next, ion implantation is performed using the LDD spacers 130 and 140 as a mask to form the source / drain region 150 and the salicide layer 160. Here, the gate electrode 120 preferably has a stacked structure of a gate oxide film, a gate poly and a salicide film.

도 3b를 참조하면, 소자 분리막(110) 및 게이트 전극(120)을 포함하는 반도체 기판(100) 전면에 식각 정지 질화막(170)을 형성한다. 여기서, 식각 정지 질화막(170)은 100 내지 300Å의 두께로 형성하는 것이 바람직하다. Referring to FIG. 3B, an etch stop nitride film 170 is formed on the entire surface of the semiconductor substrate 100 including the device isolation layer 110 and the gate electrode 120. Here, the etch stop nitride film 170 is preferably formed to a thickness of 100 to 300 kPa.

도 3c를 참조하면, 소자 분리막(110) 상부에만 감광막 패턴(180)을 형성한다. Referring to FIG. 3C, the photoresist pattern 180 is formed only on the device isolation layer 110.

도 3d를 참조하면, 감광막 패턴(180)을 마스크로 식각 정지 질화막(170)을 제거하여 소자 분리막(110) 상부에만 식각 정지 질화막(170)을 남긴다. Referring to FIG. 3D, the etch stop nitride film 170 is removed using the photoresist pattern 180 as a mask to leave the etch stop nitride film 170 only on the device isolation layer 110.

도 3e를 참조하면, 반도체 기판(100)의 활성영역상의 소스/드레인 영역(150)에 접속되는 콘택(190)을 형성한다. Referring to FIG. 3E, a contact 190 is formed to be connected to the source / drain region 150 on the active region of the semiconductor substrate 100.

본 발명에 따른 반도체 소자의 제조 방법은 반도체 기판의 소자 분리막 상부에만 식각 정지 질화막을 형성하여 소자 분리막을 형성하는 갭필 산화막의 손상을 방지하며, 스트레스에 의한 소자 특성의 변화를 억제하고 상기 식각 정지 질화막에 의해 발생하던 중수소 열처리 공정의 방해를 방지하여 소자의 신뢰성을 향상시키는 효과가 있다. The method of manufacturing a semiconductor device according to the present invention forms an etch stop nitride film only on an element isolation film of a semiconductor substrate to prevent damage to the gap fill oxide film forming the device isolation film, to suppress a change in device characteristics due to stress, and to suppress the etch stop nitride film. There is an effect of preventing the interference of the deuterium heat treatment process generated by the to improve the reliability of the device.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.






In addition, the preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are claimed in the following claims It should be seen as belonging to a range.






Claims (4)

반도체 기판 상부에 소자 분리막 및 게이트 전극을 형성하는 단계;Forming a device isolation layer and a gate electrode on the semiconductor substrate; 상기 게이트 전극 측벽에 LDD 스페이서를 형성하고 이온 주입을 수행하여 소스/드레인 영역을 형성하는 단계;Forming an LDD spacer on sidewalls of the gate electrode and performing ion implantation to form a source / drain region; 상기 소자 분리막 및 게이트 전극을 포함하는 반도체 기판 전면에 식각 정지 질화막을 형성하는 단계;Forming an etch stop nitride film on an entire surface of the semiconductor substrate including the device isolation layer and the gate electrode; 상기 소자 분리막 상부에 감광막 패턴을 형성하는 단계;Forming a photoresist pattern on the device isolation layer; 상기 감광막 패턴을 마스크로 상기 식각 정지 질화막을 제거하여 상기 소자 분리막 상부에만 상기 식각 정지 질화막을 남기는 단계; 및Removing the etch stop nitride film using the photoresist pattern as a mask to leave the etch stop nitride film only on the device isolation layer; And 상기 소스/드레인 영역에 접속되는 콘택을 형성하는 단계;Forming a contact connected to the source / drain region; 를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법. Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서, The method of claim 1, 상기 식각 정지 질화막은 100 내지 300Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. The etch stop nitride film is a semiconductor device manufacturing method, characterized in that formed in a thickness of 100 to 300 내지. 제 1 항에 있어서, The method of claim 1, 상기 게이트 전극은 게이트 산화막, 게이트 폴리 및 살리사이드막의 적층 구조로 구성되는 것을 특징으로 하는 반도체 소자의 제조 방법. The gate electrode is a semiconductor device manufacturing method, characterized in that consisting of a laminated structure of a gate oxide film, a gate poly and a salicide film. 제 1 항에 있어서, The method of claim 1, 상기 LDD 스페이서는 산화막 및 질화막으로 형성되는 것을 특징으로 하는 반도체 소자의 제조 방법. And the LDD spacer is formed of an oxide film and a nitride film.
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Publication number Priority date Publication date Assignee Title
KR100909027B1 (en) * 2006-10-12 2009-07-22 후지쯔 마이크로일렉트로닉스 가부시키가이샤 Semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100909027B1 (en) * 2006-10-12 2009-07-22 후지쯔 마이크로일렉트로닉스 가부시키가이샤 Semiconductor device and manufacturing method thereof

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