KR20060058421A - Liquid crystal display device and driving method for the same - Google Patents

Abstract

A liquid crystal display device and a driving method thereof are provided. The liquid crystal display includes a plurality of thin film transistors having a plurality of gate lines, a plurality of data lines insulated from and intersecting the plurality of gate lines, a gate electrode connected to the gate line, and a source electrode connected to the data line, and a thin film transistor. A liquid crystal panel comprising a first substrate having a pixel electrode connected to the drain electrode, a second substrate having a common electrode facing the pixel electrode, and a gate-on voltage and a thin film transistor for turning on the thin film transistor. A driving voltage generator for providing first and second gate-off voltages having different levels for turning off the gate signal, a gate-on voltage applied from the driving voltage generator, and sequentially supplied to the plurality of gate lines; When the first gate off voltage is supplied at a predetermined timing to turn off, A gate driver for supplying a second gate off voltage instead of a first gate off voltage at intervals, and a data driver for applying image voltages to a plurality of data lines as the gate on voltages are sequentially output, and outputting image data; .

Liquid crystal display, leakage current, gate-off voltage, thin film transistor

Description

Liquid crystal display device and driving method for the same

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of pixels constituting the liquid crystal display according to the exemplary embodiment of the present invention.

3 is a waveform diagram illustrating a current between a source drain and a gate voltage of a thin film transistor.

4 is a waveform diagram illustrating a state in which a leakage current is generated according to a change in a gate-off voltage, and a pixel voltage is separated by a predetermined level.

(Explanation of symbols for the main parts of the drawing)

100: liquid crystal panel 200: gate driver

300: data driver 400: driving voltage generator

500: timing controller 600: gray voltage generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (LCD) and a driving method thereof, and more particularly, to a liquid crystal display and a driving method thereof that minimize afterimages.

In general, liquid crystal displays inject a liquid crystal material between a color filter substrate on which a common electrode and a color filter are formed, and a thin film transistor substrate on which a thin film transistor and a pixel electrode are formed. By applying different potentials to the electric field to form an electric field to change the arrangement of the liquid crystal molecules, and through this to control the light transmittance is an apparatus that represents the image.

When the gray voltage of the same polarity is continuously applied to the pixel electrode of the liquid crystal display device, ionic impurities in the liquid crystal material are precipitated due to the characteristics of the liquid crystal, thereby causing electrical and chemical changes in the pixel electrode and the common electrode, resulting in a decrease in luminance or afterimage. Will remain. On the other hand, the afterimage phenomenon occurs when the image displayed on the liquid crystal panel maintains the same state for a predetermined time and then changes to another image, and the previous image does not completely disappear.

In order to prevent this, a driving method that periodically inverts the polarity of the gray voltage applied to the pixel electrode is used. As a period, frame inversion, line inversion, and dot inversion are used. Are distinguished.

Even when the inversion driving is performed, the + and-applied to the liquid crystal may not be ideally applied to each liquid crystal every frame, thereby remaining the residual DC voltage in the liquid crystal.                         

When the residual DC voltage acts on the liquid crystal molecules, a driving method for removing the residual DC is required because the residual DC voltage acts as a cause of generating an afterimage left in the liquid crystal panel.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a liquid crystal display and a method of driving the same, which minimize surface persistence due to residual DC voltage caused by asymmetric inversion driving of liquid crystals.

Technical problems to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, a liquid crystal display device includes a plurality of gate lines, a plurality of data lines insulated from and intersecting the plurality of gate lines, a gate electrode connected to the gate line, and the A plurality of thin film transistors having a source electrode connected to a data line, a first substrate having a pixel electrode connected to a drain electrode of the thin film transistor, and a second electrode having a common electrode facing the pixel electrode. A liquid crystal panel including a substrate, a driving voltage generator configured to provide a gate on voltage for turning on the thin film transistor and first and second gate off voltages having different levels for turning off the thin film transistor; The gate-on voltage is applied from the voltage generator and sequentially applied to the plurality of gate lines. A gate driver configured to supply the first gate-off voltage at a predetermined timing of turning off the thin film transistor, and supply the second gate-off voltage instead of the first gate-off voltage every several frame periods; And a data driver for outputting image data by applying a gray scale voltage to the plurality of data lines as the gate-on voltage is sequentially output.

In this case, it is preferable that the gate driver supplies the second gate-off voltage to the gate line in a pulse form at intervals of 5 to 15 frames.

On the other hand, the second gate off voltage is preferably a voltage level that operates to generate a leakage current in the thin film transistor.

Here, the first gate off voltage may be a voltage level between -8V and -6V, and the second gate off voltage may be greater than or less than the first gate off voltage level.

In addition, the driving method of the liquid crystal display according to an embodiment of the present invention for achieving the above technical problem, has a gate electrode connected to the gate line, a source electrode connected to the data line and a drain electrode connected to the pixel electrode. Providing a gate on voltage for turning on the plurality of thin film transistors and first and second gate off voltages having different levels for turning off the thin film transistors, and sequentially supplying gate on voltages to the plurality of gate lines. And supplying the first gate-off voltage at a predetermined timing of turning off the thin film transistor, and supplying the second gate-off voltage instead of the first gate-off voltage at intervals of several frames. As the signals are sequentially output, grayscales are applied to the plurality of data lines. By applying comprises the step of outputting the image data.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described.

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal panel 100, a gate driver 200, a data driver 300, a driving voltage generator 400, and a timing controller 500. ), And the gray voltage generator 600.

In the liquid crystal panel 100, a plurality of data lines D1 to Dm and a plurality of gate lines G0 to Gn intersect each other, and pixels are arranged in respective regions where one gate line and one data line cross each other. A first substrate formed in a shape and a second substrate on which a common electrode facing the pixel electrode are formed are included. Each pixel includes a TFT which is a switching element having a source electrode connected to the data line and a gate electrode connected to the data electrode gate line connected to the pixel electrode. The equivalent circuit of the pixel is specifically illustrated in FIG. 2.

As shown in FIG. 2, the gate electrode g, the source electrode s, and the drain electrode d of the TFT 10 in each pixel are connected to the gate line, the data line, and the pixel electrode P, respectively. A liquid crystal material is formed between the pixel electrode P and the common electrode Com, which is equivalently represented as a liquid crystal capacitor Cp, and a storage capacitor Cst is formed between the pixel electrode and the common electrode.

In FIG. 2, when the gate on signal is applied to the gate line and the TFT 10 is turned on, the data voltage Vd supplied to the data line is applied to the pixel electrode through the TFT 10. Then, an electric field corresponding to the difference between the pixel voltage Vp and the common voltage Vcom applied to the pixel electrode is applied to the liquid crystal (equivalently represented by the liquid crystal capacitor Cp in FIG. 1) to the intensity of the electric field. Allow light to transmit at the corresponding transmittance. At this time, the storage capacitor Cst is used auxiliary to maintain the pixel voltage Vp applied to the pixel electrode for one frame.

On the other hand, the timing controller 500 distinguishes R (red), G (green), and B (blue) data signals, a vertical synchronization signal (Vsync), which is a frame discrimination signal, and a row discrimination from a graphic controller (not shown) outside the LCD module. The digital synchronization signal Hsync and the main clock signal MCLK, which are signals, are provided to output a digital signal for driving the gate driver 200 and the data driver 300.

The timing signal output from the timing controller 500 to the gate driver 200 includes a vertical start signal Vstart for instructing the gate on voltage to be applied to the gate line, and the gate on voltage. There is a gate select signal CPV for sequentially applying to each gate line and a gate on enable signal OE that enables the output of the gate driver 200.

The timing signal output from the timing controller 500 to the data driver 300 includes the digital data signals R (0: N), G (0: N), and B (0: N) that are passed from the graphics controller. The horizontal synchronizing start signal STH for inputting to the driver 300, the load signal LOAD for commanding to apply the analog data signal converted in the data driver 300 to the panel, and the data driver 300. There is a horizontal clock signal HCLK for data shift.

The data driver 300 is also called a source driver and serves to lower the voltage value transmitted to each pixel in the liquid crystal panel 100 by one line. More specifically, the data driver 300 stores digital data from the timing controller 500 in a shift register in the data driver, and when the signal comes to command the data to the liquid crystal panel 100 (LOAD signal), respectively. It selects a voltage corresponding to the data of the to transfer the voltage into the liquid crystal panel 100.

The gate driver 200 may also be referred to as a scan driver, and serves to open a path for data from the data driver 300 to be transferred to the pixel. Each pixel of the liquid crystal panel 100 is turned on or off by a thin film transistor (TFT) serving as a switch, and the on / off of the TFT is performed by applying a constant voltage (Von, Voff) to the gate.

The gate driver 200 receives the gate selection signal CPV and the gate on enable signal 0E output from the timing controller 500 and gates the gate-on voltage Von synchronized with the two signals CPV and OE. Apply sequentially to the line. In addition, the gate-off voltage Voff is also applied in accordance with the timing for turning off the thin film transistor TFT. In detail, the gate off voltage Voff may be applied to a section where the gate on enable signal OE becomes a high level.

The gray voltage generator 600 generates a gray voltage equally divided according to the number of bits of the RGB data provided from the graphic controller and provides the gray voltage to the data driver 300. The data driver 300 is driven by a signal output from the timing controller 500 to apply a data voltage to all data lines in accordance with the driving of the gate driver 200.

On the other hand, the gate-on voltage Von for turning on the gate of the thin film transistor TFT and the gate-off voltage Voff for turning off the gate are generated by the driving voltage generator 400. The driving voltage generator 400 generates not only the Von and Voff voltages but also a common voltage Vcom which is a reference for the data voltage difference in the TFT, and Vcom is provided as a common electrode of each pixel. Particularly, in the exemplary embodiment of the present invention, first and second gate off voltages Voff1 and Voff2 having different levels are generated as the gate off voltage Voff, and the gate driver 200 generates the first and second gate off voltages Voff1 and Voff2 at regular intervals. By applying the second gate off voltage Voff2, the residual DC voltage causing the afterimage is removed.

Next, the first and second gate-off voltages are described in more detail with reference to FIG. 3, and then the liquid crystal display according to the exemplary embodiment of the present invention operates to remove the residual DC voltage. The driving method will be described.

3 is a waveform diagram illustrating a current between a source drain and a gate voltage of a thin film transistor.

As shown in FIG. 3, in the VI waveform diagram of the thin film transistor TFT, the voltage at which the minimum value of the inter-source drain current Ids appears is set to the first gate-off voltage Voff1, and the inter-source drain current Ids. The driving voltage is applied to the liquid crystal display device to operate the thin film transistor TFT by setting the gate-on voltage Von to a voltage at which the maximum value of.

In this case, the gate on voltage Von level for driving the liquid crystal display according to the exemplary embodiment of the present invention is generally determined within a range of 20V to 25V, and the first gate off voltage Voff1 level is -6V to-. It is determined within the 8V range.

On the other hand, assuming that the gate-off voltage (Voff) for turning off the thin film transistor normally is from -6V to -8V, the gate-off voltage (Voff) is set to a level greater than -6V, less than -8V, Figure 3 As shown in the waveform diagram of FIG. 2, leakage currents (Leakage currents) in which the source-drain current (Ids) of the thin film transistor are increased, that is, drop the pixel voltage (Vp), are generated.                     

When the gate-off voltage Voff is changed using this principle, a leakage current between source and drain of the TFT may be generated to remove the above-described residual DC component.

Next, a driving method of a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 4.

4 is a waveform diagram illustrating a state in which a leakage current is generated according to a change in a gate-off voltage, and a pixel voltage is separated by a predetermined level.

According to the driving method of the liquid crystal display according to the exemplary embodiment of the present invention, the above-described timing controller 500 may control the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the main clock signal CLK. Accordingly, a digital signal for driving the gate driver 200 and the data driver 300 is generated.

The driving voltage generator 400 may include a gate on voltage Von for turning on the thin film transistor TFT formed on the liquid crystal panel 100 and a different level for turning off the thin film transistor TFT. The first and second gate off voltages Voff1 and Voff2 are generated.

Here, the first gate off voltage Voff1 is a voltage level for normally turning off the thin film transistor TFT, and the second gate off voltage Voff2 is operated to generate a leakage current in the thin film transistor TFT. Is the voltage level.

Specifically, the first gate-off voltage Voff1 is a gate voltage level (for example, a voltage level between -8V and -6V) indicating a minimum value of the source-drain current in the TFT VI waveform diagram of FIG. 3. It is preferable to be set. In addition, the second gate off voltage Voff2 is set to be greater than or less than the level of the first gate off voltage Voff1 to generate a leakage current in the thin film transistor TFT so that the drain terminal of the thin film transistor TFT is formed. Preferably, the voltage level is operable to lower the pixel voltage Vp level applied to the pixel voltage Vp.

The gate driver 200 receives a gate select signal CPV and a gate on enable signal 0E output from the timing controller 500, and a gate on voltage Von synchronized with the two signals CPV and OE. Are sequentially applied to the plurality of gate lines G0 to Gn to sequentially turn on the plurality of thin film transistors TFTs connected to the respective gate lines. The first gate off voltage Voff1 is supplied at a predetermined timing of turning off the thin film transistor TFT. In detail, the first gate off voltage Voff1 may be applied to a section where the gate on enable signal OE becomes a high level.

Accordingly, as shown in FIG. 4, the data voltage Vdata applied to the plurality of data lines D1 to Dm is the pixel voltage Vp on the pixel electrode connected to the drain terminal of the thin film transistor TFT. Appears to be applied. On the other hand, even while the gate driving voltage falls from the gate-on voltage Von to the gate-off voltage Voff level, the pixel voltage Vp is applied until the next gate-on voltage Von is applied by the above-described holding capacitor Cst. Stays on.

In this case, when the second gate off voltage Voff2 is applied at the timing when the gate off voltage Voff is applied, a leakage current is generated in the thin film transistor, so that the pixel voltage Vp level is as shown in part A of FIG. 4. Can be reduced. Here, reference numeral Vk denotes a kickback voltage. In addition, the second gate off voltage Voff2 may be applied for one frame time 1f = 1/60 sec. In an embodiment of the present invention, one frame time has been described as an example of 1/60 sec, but the frame time may be variously modified within a range of 1/40 to 1/120 sec.

Meanwhile, the second gate off voltage Voff2 may be applied in a pulse form to the plurality of gate lines G0 to Gn instead of the first gate off voltage Voff1 at intervals of several frame times.

Given that the above-described residual DC voltage is a voltage remaining over several frame times due to the asymmetry of the liquid crystal inversion driving, the second DC voltage is generally accumulated in a period of 5 to 15 frame times when it is accumulated to affect the afterimage. It is preferable to apply the gate-off voltage Voff2.

As the gate-on voltage Von is sequentially output, the data driver 300 outputs image data by applying gray voltages to the data lines D1 to Dm.

Therefore, according to one embodiment of the present invention, the residual DC voltage component of the liquid crystal can be removed by providing the gate-off voltage set at a level for generating leakage current to the thin film transistor every several frame periods.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments and can be variously modified and implemented by those skilled in the art without departing from the technical scope of the present invention.

As described above, according to the present invention, an afterimage of the liquid crystal display device due to the residual DC voltage due to the asymmetric inversion driving of the liquid crystal display device can be minimized.

Claims (8)

A plurality of thin film transistors having a plurality of gate lines, a plurality of data lines insulated from and intersecting the plurality of gate lines, a gate electrode connected to the gate line and a source electrode connected to the data line, and a drain of the thin film transistor A liquid crystal panel comprising a first substrate having a pixel electrode connected to the electrode and a second substrate having a common electrode opposed to the pixel electrode; A driving voltage generator configured to provide a gate on voltage for turning on the thin film transistor and first and second gate off voltages having different levels for turning off the thin film transistor; The gate-on voltage is applied from the driving voltage generator and sequentially supplied to the plurality of gate lines, the first gate-off voltage is supplied at a predetermined timing of turning off the thin film transistor, and a few frame periods are provided. A gate driver configured to supply the second gate off voltage instead of the first gate off voltage; And And a data driver configured to apply image voltages to the plurality of data lines and output image data as the gate-on voltages are sequentially output. In claim 1, And the gate driver supplies the second gate off voltage to the gate line in a pulse form at intervals of 5 to 15 frames. In claim 1, And the second gate off voltage is a voltage level operative to generate a leakage current in the thin film transistor. In claim 3, The first gate off voltage is a voltage level between -8V and -6V, and the second gate off voltage is greater than or less than the first gate off voltage level. A gate on voltage for turning on the plurality of thin film transistors having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode, and having a different level for turning off the thin film transistor. Providing a first and a second gate off voltage; The gate-on voltage is sequentially supplied to a plurality of the gate lines, the first gate-off voltage is supplied at a predetermined timing of turning off the thin film transistor, and the second gate instead of the first gate-off voltage is provided every several frame periods. Supplying a gate off voltage; And And outputting image data by applying a gray scale voltage to a plurality of the data lines as the gate on signals are sequentially output. In claim 5, In the step of supplying the gate off voltage, A method of driving a liquid crystal display device, wherein the second gate-off voltage is supplied to the plurality of gate lines in a pulse form at intervals of 5 to 15 frame times. In claim 5, And the second gate off voltage is a voltage level operative to generate a leakage current in the thin film transistor. In claim 7, The first gate off voltage is a voltage level between -8V and -6V, and the second gate off voltage is greater than or less than the first gate off voltage level.

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