KR20060047024A - Display device and driving method thereof - Google Patents

Abstract

A display device according to an aspect of the present invention includes a plurality of pixels arranged in a matrix form, each pixel including first and second subpixels, and a plurality of pixels connected to the first subpixel and transferring a first gate signal. A plurality of second gate lines connected to a first gate line, the second subpixel, and transferring the second gate signal, intersecting the first and second gate lines, and connected to the first and second subpixels; A plurality of data lines are provided to transfer data voltages, and the magnitudes of the data voltages applied to the first and second subpixels of each pixel are different from each other and are obtained from one image information.

Visibility, Pixel Division, Double Gamma, Gray Voltage

Description

Display device and driving method thereof {DISPLAY DEVICE AND DRIVING METHOD THEREOF}

1A to 1C are block diagrams of a liquid crystal display according to an exemplary embodiment of the present invention.

2A and 2B are equivalent circuit diagrams of one pixel of the liquid crystal display according to the exemplary embodiment of the present invention.

3 is an equivalent circuit diagram of one subpixel of a liquid crystal display according to an exemplary embodiment of the present invention;

4A to 4C are block diagrams illustrating various examples of a gray voltage generator and a data driver according to an exemplary embodiment of the present invention.

5 is a block diagram of a reference voltage changing circuit and a voltage generation resistor string according to an embodiment of the present invention;

6 is a layout view of a lower panel according to an exemplary embodiment of the present invention.

7 is a layout view of an upper panel according to an exemplary embodiment of the present invention.

FIG. 8 is a layout view of a liquid crystal panel assembly including the upper panel of FIG. 7.

9 and 10 are cross-sectional views of the liquid crystal panel assembly of FIG. 8 taken along lines VII-VII ′ and VIII-VIII ′, respectively.

11 is a layout view of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.                 

12A is a graph illustrating a gamma curve of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 12B is a graph illustrating grayscale voltages relative to input grayscales of the liquid crystal display according to the exemplary embodiment.

13A to 13C illustrate signal waveforms of a liquid crystal display according to an exemplary embodiment of the present invention with time.

The present invention relates to a display device and a driving method thereof.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which field generating electrodes such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light to display an image.

Among them, the vertical alignment mode liquid crystal display in which the long axis of the liquid crystal molecules are arranged perpendicular to the upper and lower display panels without an electric field is applied, and thus a high contrast ratio and a wide reference viewing angle can be easily realized. Here, the reference viewing angle refers to a viewing angle having a contrast ratio of 1:10 or a luminance inversion limit angle between gray levels.

Means for implementing a wide viewing angle in a vertical alignment mode liquid crystal display include a method of forming a cutout in the field generating electrode and a method of forming a protrusion on the field generating electrode. Since the inclination and the projection can determine the direction in which the liquid crystal molecules are tilted, the reference viewing angle can be widened by using these to disperse the oblique directions of the liquid crystal molecules in various directions.

However, the liquid crystal display of the vertical alignment type has a problem in that the side visibility is inferior to the front visibility. For example, in the case of a patterned vertically aligned (PVA) type liquid crystal display device having an incision, the image becomes brighter toward the side, and in a severe case, the luminance difference between the high grays disappears and the picture may appear clumped.

In order to solve this problem, one pixel is divided into two subpixels, two subpixels are capacitively coupled, and one subpixel is directly applied with voltage, and the other subpixel causes voltage drop due to capacitive coupling. A method of changing the transmittances by changing the voltages of the two subpixels has been proposed.

However, this method does not have a problem in that the transmittances of the two subpixels cannot be accurately adjusted to a desired level, and in particular, since the light transmittance is different according to the color, this cannot be done despite the fact that the voltage combination for each color must be different. In addition, there is a problem in that the opening ratio decreases due to the addition of a conductor for capacitive coupling, and the transmittance decreases due to the voltage drop caused by the capacitive coupling.

The technical problem to be achieved by the present invention is to solve this problem.

A display device according to an aspect of the present invention includes a plurality of pixels arranged in a matrix form, each pixel including first and second subpixels, and a plurality of pixels connected to the first subpixel and transferring a first gate signal. A plurality of second gate lines connected to a first gate line, the second subpixel, and transferring the second gate signal, intersecting the first and second gate lines, and connected to the first and second subpixels; A plurality of data lines are provided to transfer data voltages, and the magnitudes of the data voltages applied to the first and second subpixels of each pixel are different from each other and are obtained from one image information.

Different sets of first and second gray voltages may be generated, and gray voltages corresponding to the image information may be respectively selected from the first and second gray voltage voltage sets and applied to the first and second subpixels, respectively. .

Alternatively, the image information is processed to generate a first image signal and a second image signal, and each data voltage corresponding to the first image signal and the second image signal is selected from one gray level voltage set to generate the first image signal and the second image signal. And a second subpixel, respectively.

The first subpixel and the second subpixel of each pixel may be capacitively coupled.

A liquid crystal display according to an exemplary embodiment of the present invention includes a plurality of pixels arranged in a matrix form, each pixel including a first and a second subpixel, and connected to the first subpixel and transferring a first gate-on voltage. A plurality of first gate lines, a plurality of second gate lines connected to the second subpixel and transferring a second gate-on voltage, intersecting the first and second gate lines, and the first and second subpixels. A plurality of data lines connected to and transferring a data voltage, a gray voltage generator circuit for generating first and second gray voltage voltage sets, and a selection circuit for alternately selecting and outputting the first and second gray voltage voltage sets, the selection A data driver which selects a gray voltage corresponding to image data from a set of gray voltages from a circuit and applies the gray voltage to the data line as the data voltage; and the first and second gates And a gate driver configured to sequentially apply the first and second gate-on voltages to a line.

The selection circuit may comprise an analog switch.

The selection circuit may be integrated with the data driver.

An application time of the first gate on voltage and an application time of the second gate on voltage may overlap at least partially. In this case, the application time of the first gate on voltage may be the same or may be short.

The voltage level of the second gray voltage set is smaller than the voltage of the first gray voltage set, when the first gray voltage set is selected, the first gate-on voltage is applied, and when the second gray voltage set is selected, A second gate on voltage may be applied.

According to another exemplary embodiment, a display device includes a plurality of pixels arranged in a matrix form, each pixel including a first subpixel and a second subpixel, and connected to the first subpixel to transfer a first gate-on voltage. A plurality of first gate lines, a plurality of second gate lines connected to the second subpixel and transferring a second gate-on voltage, and intersecting the first and second gate lines, respectively, to the first and second subpixels. A plurality of data lines connected and transferring a data voltage, a reference voltage generation circuit for generating a plurality of reference voltages whose values change periodically, a gray voltage generation circuit for generating a plurality of gray voltages based on the reference voltage, and Data driving for selecting a gray voltage corresponding to the image data from the gray voltage set from the gray voltage generation circuit and applying it to the data line as the data voltage. And a gate driver configured to sequentially apply the first and second gate signals to the first and second gate lines.

A liquid crystal display according to another exemplary embodiment of the present invention may include first and second gate lines extending parallel to each other and separated from each other, a data line crossing the first and second gate lines, and the first gate line and the data. A first thin film transistor connected to a line, a second thin film transistor connected to the second gate line and the data line, and a first thin film transistor connected to the first and second thin film transistors and having inclined hypotenuses facing each other. And first and second display electrodes.

According to another exemplary embodiment of the present invention, a liquid crystal display device includes first and second gate lines extending in a first direction and separated from each other, a data line extending in a second direction, and connected to the first gate line and the data line. A first thin film transistor, a second thin film transistor connected to the second gate line and the data line, and a first thin film transistor connected to the first and second thin film transistors, respectively, and including first and second display electrodes. The second direction length of the second display electrode is longer than the first display electrode, and the first display electrode is positioned in the second direction length of the second display electrode.                     

According to another exemplary embodiment of the present invention, a liquid crystal display device includes first and second gate lines extending in a first direction and separated from each other, a data line extending in a second direction, and connected to the first gate line and the data line. A first thin film transistor, a second thin film transistor connected to the second gate line and the data line, and a first thin film transistor connected to the first and second thin film transistors, respectively, and including first and second display electrodes. Each of the first and second display electrodes has a substantially symmetrical shape with respect to one straight line extending in the first direction.

The liquid crystal display may further include a third display electrode facing the first and second electrodes.

At least one of the first or second display electrodes may have a cutout, and the third display electrode may have a cutout or a protrusion. The cutouts or protrusions may be alternately arranged, and the gap between the first display electrode and the second display electrode and the cutouts of the third display electrode may be alternately arranged.

The first gate line may overlap the first and second display electrodes, and the second gate line may overlap the second display electrode and may not overlap the first display electrode.

The liquid crystal display may further include a storage electrode line overlapping the first and second display electrodes.

Each of the first and second thin film transistors may include a gate electrode connected to the first or second gate line, a source electrode connected to the data line, and a drain electrode connected to the first or second display electrode. The storage electrode line may overlap the drain electrode.

The liquid crystal display may further include a coupling electrode connected to the second display electrode and overlapping the first display electrode.

The voltage of the first display electrode may be different from the voltage of the second display electrode, and the difference between the voltage of the first display electrode and the predetermined voltage may be smaller than the difference between the voltage of the second display electrode and the predetermined voltage.

The liquid crystal display may further include an electrode which overlaps the data line and is disposed in the same layer as the pixel electrode.

A method of driving a liquid crystal display according to an exemplary embodiment of the present invention may include receiving image data, converting the input image data into two or more data voltages, and applying the converted data voltage to a corresponding subpixel. It may include the step.

The converting step may include generating two or more gray voltage sets, and selecting a gray voltage corresponding to the input image data from each of the two or more gray voltage sets as a data voltage.

The converting may include converting the input image data into two or more output image data, selecting a gray voltage corresponding to the two or more output image data from one gray voltage set, and using the data voltage as a data voltage. .

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

1A to 1C are block diagrams of a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 2A and 2B are equivalent circuit diagrams of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. An equivalent circuit diagram of one subpixel of a liquid crystal display according to an exemplary embodiment of the present invention.

1A to 1C, a liquid crystal display according to an exemplary embodiment may include a liquid crystal panel assembly 300 and a pair or one gate driver 400a, 400b, and 400 connected thereto. And a data driver 500, a gray voltage generator 800 connected to the data driver 500, and a signal controller 600 for controlling them.

The liquid crystal panel assembly 300 includes a plurality of display signal lines and a plurality of pixels PX connected to the display signal lines and arranged in a substantially matrix form when viewed in an equivalent circuit. In contrast, in the structure shown in FIG. 3, the liquid crystal panel assembly 300 includes a lower and upper panel 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The display signal line is provided in the lower panel 100, and includes a plurality of gate lines G _1a -G _nb transmitting the gate signals (also called “scan signals”) and data lines D ₁ -D transferring the data signals. _m ). The gate lines G _1a -G _nb extend approximately in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

2A and 2B show an equivalent circuit of a display signal line and a pixel. In addition to the gate line indicated by reference numerals GLa and GLb and the data line indicated by reference numeral DL, the display signal lines are substantially parallel to the gate lines G ₁ -G _2b . The extended sustain electrode line SL is included.

Referring to FIG. 2A, each pixel PX includes a pair of subpixels PXa and PXb, and each of the subpixels PXa and PXb has a corresponding gate line GLa and GLb and a data line DL. Switching elements Qa and Qb connected thereto and liquid crystal capacitors C _LC a and C _LC b connected thereto, and storage capacitors connected to switching elements Qa and Qb and sustain electrode lines SL. (storage capacitor) (C _ST a, C _ST b). The storage capacitors C _ST a and C _ST b can be omitted if necessary, and in this case, the storage electrode lines SL are also not necessary.

Referring to FIG. 2B, each pixel PX includes a pair of subpixels PXa and PXb and coupling capacitors Ccp connected therebetween, and each subpixel PXa and PXb has a corresponding gate line. Switching elements Qa and Qb connected to the GLa and GLb and the data line DL, and liquid crystal capacitors C _LC a and C _LC b connected thereto. One of the two subpixels PXa and PXb includes a storage capacitor C _ST a connected to the switching element Qa and the storage electrode line SL.

Referring to FIG. 3, the switching elements Q of each of the subpixels PXa and PXb are formed of a thin film transistor or the like provided on the lower panel 100, and each of the control terminals connected to the gate line GL; A three-terminal device having an input terminal connected to the data line DL and an output terminal connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST .

The liquid crystal capacitor C _LC has two terminals of the subpixel electrode PE of the lower panel 100 and the common electrode CE of the upper panel 200, and the liquid crystal layer 3 between the two electrodes PE and CE. Functions as a dielectric. The subpixel electrode PE is connected to the switching element Q, and the common electrode CE is formed on the entire surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 3, the common electrode CE may be provided in the lower panel 100. In this case, at least one of the two electrodes PE and CE may be formed in a linear or bar shape.

The storage capacitor C _ST , which serves as an auxiliary part of the liquid crystal capacitor C _LC , is formed by overlapping the storage electrode line SL and the pixel electrode PE provided in the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the SL. However, the storage capacitor C _ST may be formed by the subpixel electrode PE overlapping the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel uniquely displays one of the primary colors (spatial division) or each pixel alternately displays three primary colors over time (time division) so that the spatial and temporal combinations of these three primary colors can be achieved. To recognize the desired color. Examples of primary colors include red, green and blue. 3 illustrates an example of spatial division, in which each pixel includes a color filter CF representing one of primary colors in an area of the upper panel 200. Unlike FIG. 3, the color filter CF may be formed above or below the subpixel electrode PE of the lower panel 100.

1A to 1C, the gate drivers 400a, 400b, and 400 are connected to the gate lines G _1a -G _nb to form a combination of a gate on voltage Von and a gate off voltage Voff from the outside. The formed gate signal is applied to the gate lines G _1a -G _nb . In FIG. 1A, a pair of gate drivers 400a and 400b are positioned at left and right sides of the liquid crystal panel assembly 300, respectively, and are connected to odd-numbered and even-numbered gate lines G _1a -G _nb , respectively. FIGS. 1B and 1C. One gate driver 400 illustrated in FIG. 1 is positioned on one side of the liquid crystal panel assembly 300 and is connected to all of the gate lines G _1a -G _nb . In FIG. 1C, two gate drivers 400 are driven in the gate driver 400. Circuits 401 and 402 are built in, and are connected to odd and even gate lines G _1a -G _nb , respectively.

The gray voltage generator 800 generates two gray voltage sets (or reference gray voltage sets) related to the transmittance of the pixel. Two sets of gray voltages may be independently provided to two subpixels constituting one pixel, and each set of gray voltages includes a positive value and a negative value with respect to the common voltage Vcom. However, instead of two (reference) gradation voltage sets, only one (reference) gradation voltage set may be generated.

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 to select one of two gray voltage sets from the gray voltage generator 800 and to belong to the selected gray voltage set. One gray voltage is applied to the pixel as a data voltage. However, when the gray voltage generator 800 does not provide all the voltages for all grays, but only the reference gray voltages, the data driver 500 divides the reference gray voltages to generate gray voltages for all grays. Select the data voltage among these.

Various examples of the gray voltage generator 800 and the data driver 500 will be described in detail with reference to FIGS. 4A to 4C.

In addition to the gray voltage generator 800 and the data driver 500 including two voltage generation resistor lines GStr1 and GStr2, the liquid crystal display illustrated in FIG. 4A may be connected between the gray voltage generator 800 and the data driver 500, and according to the selection signal SE. It further includes an analog switch (SW) 850 for selecting one of two sets of gray voltages from the voltage generator 800 as a separate part.

The liquid crystal display shown in FIG. 4B has a structure in which the analog switch 850 shown in FIG. 4A is integrated into the data driver 500.

In the liquid crystal display shown in FIG. 4C, only the reference voltage changing circuit (VCC) 860 is used instead of the gray voltage generator 800 to generate a predetermined number of reference voltages whose sizes vary according to the selection signal SE. A plurality of gamma voltage sets different from each other according to the reference voltage supplied from the reference voltage change circuit (VVC) 860 may be provided by providing a voltage generation resistor string (GStr) 560 capable of generating a gray scale voltage in the driver 500. To create it.

An example of the reference voltage changing circuit and the voltage generation resistor column shown in FIG. 4C is shown in FIG. 5.

Referring to FIG. 5, the voltage generation resistor string 560 includes a plurality of resistors R201-R211 connected in series, and is connected to a central resistor R206 and both of them, and five resistors R201 respectively. -R205 and R207-R211 may be divided into first and second resistor sets. One end of the first resistor set R201-R205 and the second resistor set R207-R211 is connected to a low voltage such as a ground voltage and a power supply voltage AVDD, respectively.

The reference voltage change circuit 860 includes NPN and PNP bipolar transistors connected to both ends of the center resistor R206, the first resistor set R201-R205, and the second resistor set R207-R211, respectively. Q1, Q2, Q3) and a pair of resistors (R1, R2) and diodes (D1, D2) connected in series. The PNP transistor Q4, which receives the low voltage to the base through the resistors R5 and R7, is connected between the diode D3 between the high voltage input terminal to which the power supply voltage AVDD is input and the transistor Q3. The NPN transistor Q2 is connected to the input signal of the selection signal SE through the resistor R3, and the PNP transistor Q3 is connected to the high voltage input terminal through the resistors R4 and R6. The capacitor C2 is connected between the bases of the transistors Q1 and Q3, and the capacitor C1 is connected between the transistors Q2 and Q4 with the resistors R3 and R5 interposed therebetween. The capacitor C3 is connected between them.                     

Since the transistor Q3 is always turned on in the reference voltage change circuit 860, the power supply voltage AVDD is applied to one end thereof. When the select signal SE is a low value, the transistor Q4 is turned off to disconnect the high voltage, and the transistor Q2 is turned on to form a path to the low voltage. Accordingly, a low voltage is applied to the contacts N1 and N2. On the contrary, when the selection signal SE is a high value, the transistor Q2 is turned off to disconnect the low voltage, and the transistor Q4 is turned on to make a path to the high voltage. Accordingly, a high voltage determined by the resistors R1 and R6 is applied to the contacts N1 and N2.

The gate driver 400a or 400b or the data driver 500 may be directly mounted on the liquid crystal panel assembly 300 in the form of a plurality of driving integrated circuit chips, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP). Alternatively, the gate driver 400 or the data driver 500 may be integrated in the liquid crystal panel assembly 300 together with the display signal lines G _1a -G _nn and D ₁ -D _m and the thin film transistor switching element Q. It may be.

The signal controller 600 controls operations of the gate driver 400 and the data driver 500.

Next, examples of the liquid crystal panel assembly described above will be described in detail with reference to FIGS. 6 to 11.                     

6 is a layout view of a lower panel according to an exemplary embodiment of the present invention, FIG. 7 is a layout view of an upper panel according to an exemplary embodiment of the present invention, and FIG. 8 includes a lower panel of FIG. 6 and an upper panel of FIG. 7. 9 and 10 are cross-sectional views of the liquid crystal panel assembly of FIG. 8 taken along lines VII-VII 'and VIII-VIII', respectively, and FIG. 11 is a cross-sectional view of another embodiment of the present invention. It is a layout view of the liquid crystal panel assembly. 6 to 10 are examples of the liquid crystal panel assembly of the liquid crystal display device shown in FIG. 2A, and FIG. 11 is an example of the liquid crystal panel assembly of the liquid crystal display device shown in FIG. 2B.

Hereinafter, the liquid crystal panel assembly illustrated in FIGS. 6 to 10 will be mainly described, but the liquid crystal panel assembly illustrated in FIG. 11 will be described separately only in other parts.

6 to 11, the liquid crystal display device 400 according to the present exemplary embodiment includes a lower panel 100, an upper panel 200 facing each other, and a liquid crystal layer 3 interposed therebetween. .

First, the lower panel 100 will be described in detail with reference to FIGS. 6, 8 through 10, and 11.

A plurality of pairs of first and second gate lines 121a and 121b and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 made of transparent glass or the like. In the case of FIG. 11, a plurality of coupling electrodes 126 is also formed over the substrate 110.                     

The gate lines 121a and 121b mainly extend in the horizontal direction, are physically and electrically separated from each other, and transmit gate signals. The first and second gate lines 121a and 121b are disposed at an upper side and a lower side, respectively, and the plurality of first and second gate electrodes 124a and 124b protruding from the lower side and the upper side of the other layer or an external driving circuit are disposed. It includes end portions 129a and 129b that are large in area for connection and are disposed on the left and right sides, respectively. However, these ends 129a and 129b may both be disposed to the left or to the right.

The storage electrode line 131 extends mainly in the horizontal direction and is closer to the first gate line 121a than the second gate line 121b. Each storage electrode line 131 includes a plurality of pairs of first and second storage electrodes 137a and 137b extending up and down. The first storage electrode 137a has a longer length and a width than the second storage electrode 137b. Is narrow. In contrast, the storage electrode line 131 illustrated in FIG. 11 includes only one storage electrode 137 substantially corresponding to the first storage electrode 137a. However, the shape and arrangement of the storage electrode lines 131 including the storage electrodes 137a, 137b, and 137 may be modified in various forms.

The coupling electrode 126 of FIG. 11 is adjacent and extends in parallel with the sustain electrode 137 and has a protrusion extending downward for connection with another layer.

The gate line 121 and the storage electrode line 131 may be formed of aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, and copper-based metals such as copper (Cu) and copper alloys. , Molybdenum-based metals such as molybdenum (Mo) and molybdenum alloy, chromium (Cr), titanium (Ti), tantalum (Ta) and the like is preferably made. However, the gate line 121 and the storage electrode line 131 may have a multilayer structure including two conductive layers (not shown) having different physical properties. One of the conductive films may be formed of a low resistivity metal such as an aluminum-based metal, a silver-based metal, or a copper-based metal so as to reduce signal delay or voltage drop between the gate line 121 and the storage electrode line 131. Is done. In contrast, the other conductive film is made of a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, titanium, tantalum, and the like. A good example of such a combination is a chromium bottom film and an aluminum top film, and an aluminum bottom film and a molybdenum top film. However, the gate line 121 and the storage electrode line 131 may be made of various metals and conductors.

In addition, side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is about 30-80 °.

A gate insulating layer 140 made of silicon nitride (SiN _x ) is formed on the gate lines 121a and 121b and the storage electrode line 131.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon, polycrystalline silicon, or the like are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction, from which a plurality of first and second projections 154a and 154b extend toward the first and second gate electrodes 124a and 124b, respectively. In addition, the linear semiconductor 151 increases in width near a point where the linear semiconductor 151 meets the gate lines 121a and 121b and the storage electrode line 131, thereby covering a large area of the gate lines 121a and 121b.

A plurality of linear and island ohmic contacts 161 and 165a made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed on the semiconductor 151. have. The linear contact member 161 has a plurality of protrusions 163a, and the protrusions 163a and the island contact members 165a are paired and positioned on the protrusions 154a of the semiconductor 151. Although not shown, the protrusion of the linear contact member 161 and the island contact member are paired with each other on the second protrusion 154b of the semiconductor 151.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165a are also inclined with respect to the surface of the substrate 110 and have an inclination angle of 30-80 °.

A plurality of data lines 171 and a plurality of pairs of first and second drain electrodes 175a and 175b are formed on the ohmic contacts 161 and 165a and the gate insulating layer 140, respectively. have.

The data line 171 mainly extends in the vertical direction and crosses the gate line 121 and the storage electrode line 131 and transmits a data voltage. Each data line 171 is connected to a plurality of first and second source electrodes 173a and 173b extending toward the first and second drain electrodes 175a and 175b, respectively, from another layer or an external device. It includes an end portion 179 extending in width.

The first and second drain electrodes 175a and 175b start from the rod-shaped ends positioned over the first and second protrusions 154a and 154b of the semiconductor 151, respectively, and the first and second sustain electrodes 137a and 137b. ) Has wide areas 177a and 177b which overlap with each other. However, the second drain electrode 175b of FIG. 11 does not extend long but extends shortly, and the first drain electrode 175a overlaps the sustain electrode 137 and the coupling electrode 126. Each of the source electrodes 173a and 173b is bent to surround the rod-shaped ends of the drain electrodes 175a and 175b. The first and second gate electrodes 124a and 124b, the first and second source electrodes 173a and 173b, and the first and second drain electrodes 175a and 175b are first and second protrusions of the semiconductor 151. The first and second thin film transistors TFTs Qa / Qb are formed together with the second and second source electrodes 154a and 154b, and the channels of the thin film transistors Qa and Qb are formed of the first and second source electrodes. 173a / 173b and protrusions 154a / 154b between the drain electrodes 175a / 175b.

The data line 171 and the drain electrodes 175a and 175b are preferably made of a refractory metal such as chromium, molybdenum-based metal, tantalum, and titanium, and include a lower film (not shown) such as a refractory metal and a low resistance thereon. It may have a multilayer structure consisting of a material upper layer (not shown). Examples of the multilayer film structure include a triple film of molybdenum film, aluminum film, and molybdenum film in addition to the above-described double film of chromium lower film and aluminum upper film or aluminum lower film and molybdenum upper film.

The data line 171 and the drain electrodes 175a and 175b are also inclined at an angle of about 30 to 80 degrees, similarly to the gate line 121 and the storage electrode line 131.

The ohmic contacts 161 and 165a exist only between the semiconductor 151 below and the data lines 171 and drain electrodes 175a and 175b thereon, and serve to lower the contact resistance. The linear semiconductor 151 has portions exposed between the source electrodes 173a and 173b and the drain electrodes 175a and 175b, and are not covered by the data line 171 and the drain electrodes 175a and 175b. Although the width of the linear semiconductor 151 is smaller than the width of the data line 171, as described above, the width of the linear semiconductor 151 increases in a portion where the linear semiconductor 151 meets the gate lines 121a and 121b and the storage electrode line 131 so as to soften the profile of the surface so that the data line To prevent disconnection.

A passivation layer 180 is formed on the data line 171, the drain electrodes 175a and 175b, and the exposed portion of the semiconductor 151. The passivation layer 180 is formed of an inorganic material made of silicon nitride or silicon oxide, an organic material having excellent planarization characteristics, photosensitivity, or a-Si: C: O formed by plasma enhanced chemical vapor deposition (PECVD), It consists of low dielectric constant insulating materials, such as a-Si: O: F. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer in order to protect the exposed portion of the semiconductor 151 while maintaining the excellent characteristics of the organic layer.

The passivation layer 180 includes a plurality of contact holes 182, 185a, and 185b exposing end portions 179 of the data line 171 and the extended portions 177a and 177b of the drain electrodes 175a and 175b, respectively. A plurality of contact holes 181a and 181b exposing end portions 129a and 129b of the gate lines 121a and 121b are formed in the passivation layer 180 and the gate insulating layer 140. In the case of FIG. 11, a plurality of contact holes 186 are formed in the passivation layer 180 and the gate insulating layer 140 to expose end portions 129a and 129b of the coupling electrode 126.

On the passivation layer 180, a plurality of pixel electrodes 190 including the first and second subpixel electrodes 190a and 190b, a plurality of shielding electrodes 88, and a plurality of contact assistants, respectively. ) 81a, 81b, 82 are formed. The pixel electrode 190 and the contact auxiliary members 81a, 81b, and 82 are made of a transparent conductor such as ITO or IZO or a reflective conductor such as aluminum.

The first and second subpixel electrodes 190a and 190b are physically and electrically connected to the first and second drain electrodes 175a and 175b through the contact holes 185a and 185b to form the first and second drain electrodes ( Data voltage is applied from 175a / 175b). In FIG. 11, the second subpixel electrode 190b is connected to the coupling electrode 126 through the contact hole 186, and the first subpixel electrode 190a overlaps the coupling electrode 126.

The subpixel electrodes 190a and 190b to which the data voltage is applied generate an electric field together with the common electrode 270 to determine the arrangement of liquid crystal molecules of the liquid crystal layer 3 between the two electrodes 190 and 270.

In addition, as described above, each of the subpixel electrodes 190a and 190b and the common electrode 270 form liquid crystal capacitors C _LC a and C _LC b to maintain the applied voltage even after the thin film transistors Qa and Qb are turned off. And the storage capacitors C _ST a and C _ST b connected in parallel with the liquid crystal capacitors C _LC a and C _LC b to enhance the voltage holding capability. The first and second subpixel electrodes 190a and 190b are connected to each other. And overlapping drain electrodes 175a and 175b and first and second sustain electrodes 137a and 137b connected thereto.

Each pixel electrode 190 is chamfered at the left corner, and the chamfered hypotenuse forms an angle of about 45 degrees with respect to the gate lines 121a and 121b.

The pair of first and second subpixel electrodes 190a and 190b constituting one pixel electrode 190 are engaged with each other with a gap 94 therebetween, and an outer boundary thereof is substantially rectangular. The first subpixel electrode 190a is a rotated equilateral trapezoid, the left side of which is located near the second storage electrode 137b, the right side of the opposite side thereof, and an upper hypotenuse which is approximately 45 ° with the gate lines 121a and 121b. And lower hypotenuse. The second subpixel electrode 190b includes a pair of trapezoids facing the hypotenuse of the first subpixel electrode 190a and a vertical portion facing the left side of the first subpixel electrode 190a. Accordingly, the gap 94 between the first subpixel electrode 190a and the second subpixel electrode 190b has a substantially uniform width and has upper and lower diagonal portions (45 °) that form about 45 ° with the gate lines 121a and 121b. 91, 93 and longitudinal sections 92 having a substantially uniform width.

The first subpixel electrode 190a has a cutout 95 extending along the storage electrode line 131, and is bisected into an upper half and a lower half by the cutout 95. The cutout 95 has an inlet at the right side of the first subpixel electrode 190a, and the inlet of the cutout 95 is formed with the upper diagonal 91 and the lower diagonal 93 of the gap 94, respectively. It has a pair of hypotenuses that are substantially parallel. The gap 94 and the cutout 95 are substantially inversion symmetry with respect to the storage electrode line 131.

In this case, the number of divided portions or the number of cutout portions varies depending on the size of the pixel, the ratio of the length of the horizontal side to the vertical side of the pixel electrode 190, and the type or characteristics of the liquid crystal layer 3. Hereinafter, for convenience of explanation, the gap 94 is also expressed as a cutout.

In addition, the first subpixel electrode 190a overlaps the first gate line 121a and the second subpixel electrode 190b overlaps both the first and second gate lines 121a and 121b and the first gate. The line 121a passes near the center of the upper half of the pixel electrode 190.

The shielding electrode 88 extends along the data line 171 and completely covers the data line 171. A common voltage is applied to the shielding electrode 88. The common electrode is connected to the storage electrode line 131 through a contact hole (not shown) of the passivation layer 180 and the gate insulating layer 140, or the common voltage is applied to the thin film transistor array panel. The display device may be connected to a short point (not shown) transferred from the 100 to the common electrode display panel 200. At this time, it is preferable to minimize the distance between the shielding electrode 88 and the pixel electrode 190 so that the aperture ratio decreases to a minimum.

As such, when the shielding electrode 88 to which the common voltage is applied is disposed on the data line 171, the shielding electrode 88 is disposed between the data line 171 and the pixel electrode 190, and the data line 171 and the common electrode ( By blocking the electric field formed between the 270, the voltage distortion of the pixel electrode 190 and the signal delay of the data voltage transmitted by the data line 171 are reduced.

Also, in order to prevent a short circuit between the pixel electrode 190 and the shielding electrode 88, a distance is required between them so that the pixel electrode 190 is further away from the data line 171, thereby reducing the parasitic capacitance therebetween. Furthermore, since the permittivity of the liquid crystal layer 3 is higher than that of the passivation layer 180, the parasitic capacitance between the data line 171 and the shielding electrode 88 is absent when the shielding electrode 88 is absent. It is smaller than the parasitic capacitance between 171 and the common electrode 270.

In addition, since the pixel electrode 190 and the shielding electrode 88 are made of the same layer, the distance between them is kept constant and thus the parasitic capacitance between them is constant. Although the parasitic capacitance between the pixel electrode 190 and the data line 171 may still vary depending on the exposure area divided during the split exposure process, the parasitic capacitance between the pixel electrode 190 and the data line 171 is relatively low. The overall parasitic capacity is almost constant. Therefore, stitch defects can be minimized.

The contact auxiliary members 81a, 81b, and 82 may contact the end portions 129a and 129b of the gate lines 121a and 121b and the end portions 179 of the data lines 171 through the contact holes 181a, 181b and 182. Each is connected. The contact auxiliary members 81a, 81b, and 82 complement adhesiveness between the end portions 129a and 129b of the gate lines 121a and 121b and the respective end portions 179 of the data line 171 and the external device, and It protects you.

When the gate drivers 400a and 400b or the data driver 500 illustrated in FIG. 1 are integrated on the assembly 300, the gate lines 121a and 121b or the data line 171 may be extended to be directly connected to them. In this case, the contact auxiliary members 81a, 81b, and 82 may be used to connect the gate lines 121a and 121b or the data lines 171 and the driving units 400a, 400b, and 500, and the like.

On the pixel electrode 190, the contact auxiliary members 81a, 81b, 82, and the passivation layer 180, an alignment layer 11 capable of aligning the liquid crystal layer is coated.

Next, the upper panel 200 will be described with reference to FIGS. 7 to 10.

A light blocking member 220 called a black matrix for preventing light leakage is formed on an insulating substrate 210 made of transparent glass or the like. The light blocking member 220 has a plurality of openings facing the pixel electrode 190 and having substantially the same shape as the pixel electrode 190. Alternatively, the light blocking member 220 may include a portion corresponding to the data line 171 and a portion corresponding to the thin film transistor. However, the light blocking member 220 may have various shapes to block light leakage near the pixel electrode 190 and the thin film transistors Qa and Qb.

A plurality of color filters 230 is also formed on the substrate 210. The color filter 230 may be mostly located in an area surrounded by the light blocking member 230, and may extend in the vertical direction along the pixel electrode 190. The color filter 230 may display one of primary colors such as red, green, and blue.

An overcoat 250 is formed on the color filter 230 and the light blocking member 230 to prevent the color filter 230 from being exposed and to provide a flat surface.

The common electrode 270 formed of a transparent conductor such as ITO or IZO is formed on the overcoat 250.

The common electrode 270 has a plurality of cutouts 271, 273, and 275.

One set of cutouts 271, 273, and 275 includes an upper cutout 271, a center cutout 272, and a lower cutout 273 facing the pixel electrode 190. Each of the cutouts 271, 273, and 275 is disposed between adjacent cutouts 94 and 95 of the pixel electrode 190 or between the cutout 94 and the hypotenuse of the pixel electrode 190. Further, each cutout 271, 273, 275 defines at least one diagonal line 271o, 273o, 275o1, 275o2 extending in parallel with the upper diagonal line 91 or the lower diagonal line 93 of the gap 94. It is substantially inverted symmetry with respect to the storage electrode line 131.

Each of the upper and lower incisions 271 and 273 is a pixel from each end of the oblique portions 271o and 273o extending from the left side of the pixel electrode 190 toward the upper or lower side, and the diagonal portions 271o and 273o. It includes a horizontal portion (271t, 273t) and the vertical portion (271 l , 273 l ) extending along the side of the electrode 190 and overlapping the side and forming an obtuse angle with the oblique portions (271o, 273o).

The center cutout 275 includes a pair of oblique portions 275o1 and 275o2, and oblique portions 275o1 and 275o2 extending from the center of the left side of the pixel electrode 190 to the right side of the pixel electrode 190 at an angle. Each of the ends of the pixel electrode 190 includes a vertical portion 275 l 1 and 275 l 2 which extends while overlapping the right side and forms an obtuse angle with the oblique portions 275 o 1 and 275 o 2.

The number of cutouts 271, 273, and 275 may vary depending on design factors, and the light blocking member 220 overlaps the cutouts 271, 273, and 275 so that the light leakage near the cutouts 271, 273, and 275 may occur. Can be blocked.

An alignment layer 21 is disposed on the common electrode 270 to align the liquid crystal molecules.

Orthogonal polarizing plates 12 and 22 are provided on the outer surfaces of the display panels 100 and 200, and the transmission axes of the two polarizing plates 12 and 22 are orthogonal, and one transmission axis (or absorption axis) is parallel to the horizontal direction. In the case of a reflective liquid crystal display, one of the two polarizing plates 12 and 22 may be omitted.

The liquid crystal layer 3 has negative dielectric anisotropy and the liquid crystal molecules are aligned such that their major axes are substantially perpendicular to the surfaces of the two display panels 100 and 200 when there is no electric field.

When a common voltage is applied to the common electrode 270 and a data voltage is applied to the pixel electrode 190, an electric field substantially perpendicular to the surfaces of the display panels 100 and 200 is generated. The cutouts 94, 95, 271, 273, 275 of the electrodes 190, 270 distort this electric field to create a horizontal component perpendicular to the sides of the cutouts 94, 95, 271, 273, 275. . Accordingly, the electric field indicates a direction inclined with respect to the direction perpendicular to the surfaces of the display panels 100 and 200. In response to the electric field, the liquid crystal molecules change their long axis to be perpendicular to the direction of the electric field. In this case, the electric field near the sides of the cutouts 94, 95, 271, 273, and 275 and the pixel electrode 190 is a liquid crystal. The liquid crystal molecules rotate in a direction in which the movement distance is short on a plane formed by the long axis direction of the liquid crystal molecules and the electric field because they are formed at an angle without being parallel to the long axis direction of the molecules. Accordingly, one set of cutouts 94, 95, 271, 273, and 275 and the side of the pixel electrode 190 may be arranged in a plurality of different directions in which liquid crystal molecules are inclined to a portion of the liquid crystal layer 3 positioned on the pixel electrode 190. Divide into domains, thereby expanding the reference viewing angle.                     

At least one cutout 94, 95, 271, 273, 275 may be replaced with a protrusion or depression, and the shape and arrangement of the cutouts 94, 95, 271, 273, 275 may be modified.

The display operation of such a liquid crystal display device will now be described in detail.

The signal controller 600 is configured to control the input image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical synchronization signal Vsync and a horizontal synchronization signal ( Hsync, main clock MCLK, and data enable signal DE are provided. Based on the input image signals R, G and B of the signal controller 600 and the input control signals, the image signals R, G and B are properly processed according to the operating conditions of the liquid crystal panel assembly 300, and the gate control signal After generating the CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to

The gate control signal CONT1 includes a scan start signal STV indicating the start of scanning and at least one clock signal controlling the output time of the gate-on voltage Von. The gate control signal CONT1 may also include an output enable signal OE that defines the duration of the gate-on voltage Von. The clock signal may be used as the selection signal SE shown in FIGS. 4A to 4C and FIG. 5.

The data control signal CONT2 is a horizontal synchronization start signal STH for transmitting data to a group of pixels PX and a load signal LOAD for applying a corresponding data voltage to the data lines D ₁ -D _m . And a data clock signal HCLK. The data control signal CONT2 may also include an inversion signal RVS that inverts the polarity of the data voltage relative to the common voltage Vcom (hereinafter referred to as the polarity of the data voltage by reducing the polarity of the data voltage relative to the common voltage). have.

In response to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the image data DAT for the batch of subpixels PX, and receives the image data DAT from the gray voltage generator 800. By selecting one of the two sets of gray voltages and selecting a gray voltage corresponding to each of the image data DAT from among the selected gray voltage sets, the image data DAT is converted into the corresponding data voltage, and the corresponding data line ( D ₁ -D _m ).

On the contrary, as shown in FIG. 4A, the external selection circuit 850 provided separately from the data driver 500 selects one of two sets of gray voltages and transfers them to the data driver 500, or generates gray voltages as shown in FIG. 4C. The unit 800 may provide a reference voltage whose value changes, and the data driver 500 may divide the voltage to generate a gray voltage by itself.

The gate driver 400 applies the gate-on voltage Von to the gate lines G _1a -G _nb in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G _1a -G _nb . Turns on the switching elements Qa and Qb connected thereto, so that the data voltages applied to the data lines D ₁ -D _m are applied to the corresponding subpixels PX through the turned-on switching elements Qa and Qb. .

The difference between the data voltage applied to the subpixels PXa and PXb and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor CLC, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

The two sets of gray voltages described above show different gamma curves Ta and Tb as shown in FIG. 12A and one pixel PX because they are applied to two subpixels PXa and PXb of one pixel PX. The gamma curve of becomes the curve T which synthesize | combined these. When determining two sets of gray voltages, the composite gamma curve (T) is close to the reference gamma curve at the front, i.e., the composite gamma curve (T) at the front is the And the synthetic gamma curve T on the side closest to the reference gamma curve on the front. For example, making the lower gamma curve lower at lower gradations can improve visibility.

The data driver 500 and the gate driver 400 perform the same operation in units of 1/2 horizontal periods (or "1/2 H") (one period of the horizontal sync signal Hsync and the gate clock CPV). Repeat. In this manner, the gate-on voltages Von are sequentially applied to all the gate lines G1 -G2n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarities of the data voltages flowing through one data line change according to the characteristics of the inversion signal RVS within one frame (eg, row inversion and dot inversion), or polarities of data voltages flowing through adjacent data lines at the same time. Can be different (eg, column inversion, dot inversion).

However, since the liquid crystal display has twice the gate lines as compared to the conventional liquid crystal display, when the data voltage is applied by the conventional method, the voltage charging time may be short and the pixel may not reach the target voltage due to polarity inversion. Even more so. Therefore, the time for applying the gate-on voltage Von to two adjacent gate lines may be partially overlapped. This may be achieved by employing the gate driver illustrated in FIGS. 1A and 1C.

Various data voltage application types will now be described in detail with reference to FIGS. 13A to 13B.

13A to 13C illustrate signal waveforms of a liquid crystal display according to an exemplary embodiment of the present invention according to time, wherein Vga is a gate signal applied to a first gate line, and Vgb is a gate signal applied to a second gate line. , Vd is a data voltage flowing through one data line.

In the case of the point inversion, since the polarities of the adjacent pixels are opposite, applying the data voltage of the adjacent pixels does not help to reduce the charging time. Therefore, as shown in FIG. 13A, it is preferable that the charging times of adjacent pixels do not overlap and the charging times of two subpixels of one pixel are overlapped. Then, since the charging time of the sub-pixel charged later will be reduced, the gradation voltage applied to the sub-pixel charged later than the magnitude (GVa) of the set of gradation voltages applied to the sub-pixel initially charged as shown in FIGS. 12B and 13A. It is desirable to increase the size (Vgb) of the set.

However, in the case of column inversion, since the polarity of the pixels adjacent to each other up and down is the same, the precharge may be performed by applying the data voltages of the adjacent pixels. Therefore, as shown in FIG. 13B, the charging times of all the subpixels can be overlapped for a predetermined time or more.

FIG. 13C illustrates a case in which the gate-on voltage Von may be applied to one gate line at a time as in the gate driver of FIG. 1B.

On the other hand, unlike the foregoing description, only one pair of gray voltages may be generated, two sets of image data corresponding to the input image data may be generated, and the corresponding gray voltage may be found and applied as a data voltage.

To this end, a lookup table containing output image data corresponding to input image data may be used.

For example, the signal controller 600 includes two row memories and a lookup table, converts the input image data into two image data according to the lookup table, stores them in each row memory, and then outputs the image data stored in the two memories. This is followed by the output to the data driver 500.

In this case, the data transmission speed from the signal controller 600 to the data driver 500 should be twice as fast as the previous example.

Alternatively, the data driver 500 includes two row memories and a lookup table, converts the image data received from the signal controller 600 into two image data according to the lookup table, and stores the image data in each row memory. The gradation voltage corresponding to the image data stored in the circuit is found and applied to the data line.

In this case, the data transmission speed from the signal controller 600 to the data driver 500 does not change.

By precisely adjusting the voltages of the two subpixels to the desired level, the visibility is improved, the aperture ratio is increased, and the transmittance is improved.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (31)

A plurality of pixels arranged in a matrix and including first and second subpixels, A plurality of first gate lines connected to the first subpixel and transferring a first gate signal, A plurality of second gate lines connected to the second subpixel and transferring a second gate signal; A plurality of data lines intersecting the first and second gate lines, connected to the first and second subpixels, and transferring data voltages; Including; The magnitudes of the data voltages applied to the first and second subpixels of each pixel are different from each other and are obtained from one image information. Display device. In claim 1, A display device for generating a different set of first and second gray voltages and selecting a gray voltage corresponding to the image information from the first and second gray voltage sets, respectively, and applying them to the first and second subpixels, respectively. . In claim 1, The image information is processed to generate a first image signal and a second image signal, each data voltage corresponding to the first image signal and the second image signal is selected from one gray level voltage set, and the first and second image signals are generated. Display devices applied to sub-pixels respectively. In claim 1, The first subpixel and the second subpixel of each pixel are capacitively coupled. A plurality of pixels arranged in a matrix and including first and second subpixels, A plurality of first gate lines connected to the first subpixel and transferring a first gate on voltage; A plurality of second gate lines connected to the second subpixel and transferring a second gate on voltage; A plurality of data lines crossing the first and second gate lines and connected to the first and second subpixels and transferring data voltages; A gray voltage generator circuit for generating a first and second gray voltage sets; A selection circuit for alternately selecting and outputting the first and second gray voltage sets; A data driver which selects a gray voltage corresponding to the image data from the set of gray voltages from the selection circuit and applies it to the data line as the data voltage; and A gate driver configured to sequentially apply the first and second gate-on voltages to the first and second gate lines Display device comprising a. In claim 5, And the selection circuit comprises an analog switch. In claim 5, And the selection circuit is integrated with the data driver. In claim 5, And an application time of the first gate on voltage and at least a portion of the application time of the second gate on voltage. In claim 8, The display time of applying the first gate on voltage and the applying time of the second gate on voltage are the same. In claim 8, The display time of the first gate on voltage is shorter than the time of applying the second gate on voltage. In claim 5, The voltage level of the second gray voltage set is smaller than the voltage of the first gray voltage set, when the first gray voltage set is selected, the first gate-on voltage is applied, and when the second gray voltage set is selected, A display device to which a second gate on voltage is applied. A plurality of pixels arranged in a matrix and including first and second subpixels, A plurality of first gate lines connected to the first subpixel and transferring a first gate on voltage; A plurality of second gate lines connected to the second subpixel and transferring a second gate on voltage; A plurality of data lines crossing the first and second gate lines and connected to the first and second subpixels and transferring data voltages; A reference voltage generation circuit for generating a plurality of reference voltages whose values change periodically, A gray voltage generator for generating a plurality of gray voltages based on the reference voltage; A data driver which selects a gray voltage corresponding to the image data from the gray voltage set from the gray voltage generator and applies it to the data line as the data voltage; and A gate driver configured to sequentially apply the first and second gate signals to the first and second gate lines Display device comprising a. First and second gate lines extending parallel to each other and separated from each other, A data line crossing the first and second gate lines; A first thin film transistor connected to the first gate line and the data line, A second thin film transistor connected to the second gate line and the data line, and First and second display electrodes connected to the first and second thin film transistors, respectively, and have inclined hypotenuses facing each other. Liquid crystal display comprising a. First and second gate lines extending in a first direction and separated from each other, A data line extending in a second direction, A first thin film transistor connected to the first gate line and the data line, A second thin film transistor connected to the second gate line and the data line, and First and second display electrodes connected to the first and second thin film transistors, respectively; Including; The second direction length of the second display electrode is longer than the first display electrode, and the first display electrode is positioned within the second direction length of the second display electrode. Liquid crystal display. First and second gate lines extending in a first direction and separated from each other, A data line extending in a second direction, A first thin film transistor connected to the first gate line and the data line, A second thin film transistor connected to the second gate line and the data line, and First and second display electrodes connected to the first and second thin film transistors, respectively; Including; The first and second display electrodes each have a substantially symmetrical shape with respect to one straight line extending in the first direction. Liquid crystal display. The method according to any one of claims 13 to 15, And a third display electrode facing the first and second electrodes. The method of claim 16, And at least one of the first and second display electrodes has a cutout. The method of claim 17, The third display electrode has a cutout or protrusion. The method of claim 16, At least one of the first and second display electrodes and the third display electrode have cutouts arranged alternately. The method of claim 19, The gap between the first display electrode and the second display electrode and the cutouts of the third display electrode are alternately arranged. The method according to any one of claims 13 to 15, The first gate line overlaps the first and second display electrodes. The method of claim 21, And the second gate line overlaps the second display electrode and does not overlap the first display electrode. The method according to any one of claims 13 to 15, And a storage electrode line overlapping the first and second display electrodes. The method of claim 23, Each of the first and second thin film transistors may include a gate electrode connected to the first or second gate line, a source electrode connected to the data line, and a drain electrode connected to the first or second display electrode. , The storage electrode line overlaps the drain electrode. Liquid crystal display. The method of claim 24, And a coupling electrode connected to the second display electrode and overlapping the first display electrode. The method according to any one of claims 13 to 15, The voltage of the first display electrode is different from the voltage of the second display electrode. The method of claim 26, The difference between the voltage of the first display electrode and the predetermined voltage is smaller than the difference between the voltage of the second display electrode and the predetermined voltage. The method according to any one of claims 13 to 15, And a shielding electrode overlapping the data line and positioned on the same layer as the pixel electrode. Receiving image data, Converting the input image data into two or more data voltages, and Applying the converted data voltage to a corresponding subpixel Method of driving a liquid crystal display comprising a. The method of claim 29, The conversion step, Generating two or more sets of gray voltages, and Selecting a gray voltage corresponding to the input image data from each of the two or more gray voltage sets and using the data voltage as a data voltage; Method of driving a liquid crystal display comprising a. The method of claim 29, The conversion step, Converting the input image data into two or more output image data, and Selecting a gray voltage corresponding to the two or more output image data from one gray voltage set and using the data voltage as a data voltage; Method of driving a liquid crystal display comprising a.

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