CN1773601A - Display device and driving method - Google Patents

Abstract

A display device according to an embodiment of the present invention includes: a pixel including a first subpixel and a second subpixel; a first signal line connected to the first subpixel and transmitting a first signal; a second signal line connected to the second subpixel and transmitting a second signal; a third signal line intersecting the first and the second signal lines, connected to at least one of the first and the second subpixels, and transmitting a third signal; and a fourth signal line intersecting the first and the second signal lines and transmitting a fourth signal, wherein the first subpixel and the second subpixel are supplied with data voltages having different magnitude, and the data voltages applied to the first and the second subpixels are originated from a single image information.

Description

Display device and driving method thereof

Technical field

The present invention relates to display device and driving method thereof, especially, relate to LCD.

Background technology

Normally, LCD (LCD) comprises the counter plate with pixel electrode and common electrode and is folded in therebetween the liquid crystal with each diversity of dielectric (LC) layer.Pixel electrode is arranged in matrix, and is connected with on-off element such as thin film transistor (TFT) (TFT).Pixel electrode is supplied to data voltage line by line by TFT.Common electrode is formed at the whole surface of panel, and is supplied to the common-battery pressure.Pixel electrode and common electrode and the LC layer that is folded in therebetween form the LC capacitor from the circuit angle, and LC capacitor and on-off element are the primary elements that forms pixel.

By to electrode application voltage, LCD produces electric field in the LC layer, and the optical transmission rate that incides on the LC layer with change by the intensity of controlling this electric field obtains required image.

In LCD, the LCD of vertical orientated (VA) pattern (it is orientated the LC molecule, thereby the longitudinal axis of LC molecule is not having under the situation of electric field perpendicular to panel) is owing to the benchmark visual angle of its higher contrast ratio and broad gets most of the attention.

The wide visual angle of the LCD of VA pattern can be realized by the projection that the field produces the cut of electrode and produces electrode.Because cut and projection can determine the vergence direction of LC molecule, therefore by using cut and projection, vergence direction can be distributed to several directions, thereby has enlarged the visual angle.

Yet the LCD of VA pattern compares with positive visuality has relatively poor side visibility.For example, the side gamma curve is different from the front gamma curve.

In order to improve side visibility, pixel is divided into can two sub-pixels connected to one another.One of them sub-pixel directly is supplied to voltage, and another sub-pixel experiences pressure drop by the electric capacity connection, thereby two sub-pixels have different voltage to cause different transmissivities.

Yet conventional method can not be controlled the transmissivity of two sub-pixels.Especially, depend on that owing to transmissivity the color of light changes, preferably, the voltage of different colours is different, and this is impossible.In addition, owing to the extra conductor that is used for the electric capacity connection has reduced the aperture ratio, and the pressure drop that causes owing to the electric capacity connection has reduced transmissivity.

Simultaneously, each frame of polarity of the data voltage of pressing with respect to common-battery all, the row or column of each predetermined quantity is all anti-phase, perhaps are used to avoid each pixel of defective to include because the defective that the unidirectional electric field of long-time application causes.In inversion scheme, the row of data voltage are anti-phase, it is in the polarity of each predetermined quantity oppisite phase data line of pixel column, with the data voltage polarity that keeps being applied in the given time on the data line, to reduce the signal delay in the data line and to reduce power attenuation.

Yet, be listed as anti-phase vertical flicker and the image quality that vertically disturbs, thereby reduced LCD of causing.

Summary of the invention

Fundamental purpose of the present invention is to avoid the defective that exists in the above-mentioned prior art, and a kind of display device and driving method thereof are provided.

Display device according to the embodiment of the invention comprises: pixel comprises first sub-pixel and second sub-pixel; First signal wire is connected to described first sub-pixel and transmits first signal; The secondary signal line is connected to described second sub-pixel and transmits secondary signal; The 3rd signal wire intersects with described first and second signal wires, and is connected in described first and second sub-pixels at least one, and transmits the 3rd signal; And the 4th signal wire, intersect with described first and second signal wires, and transmit the 4th signal, wherein, described first sub-pixel and described second sub-pixel are supplied to the data voltages with different sizes, and the data voltage that is fed into described first and second sub-pixels results from single image information.

First sub-pixel comprises first on-off element that is connected on described first signal wire, with first liquid crystal capacitor that is connected on described first on-off element, and second sub-pixel comprise and be connected to the second switch element on the described secondary signal line and be connected to second liquid crystal capacitor on the described second switch element.

First liquid crystal capacitor comprises first pixel electrode that is connected on first on-off element, and second liquid crystal capacitor comprises second pixel electrode that is connected on the second switch element.

The first and second pixel electrode each intervals make the gap that is the oblique angle with first to the 4th signal wire.

In first and second sub-pixels at least one has makes the cut that is the oblique angle with described first to the 4th signal wire.

First and second sub-pixels also comprise the common electrode with cut, and this cut makes and is the oblique angle with described first to the 4th signal wire.

First on-off element is connected to the first and the 3rd signal wire, and the second switch element is connected to the second and the 3rd signal wire.

First on-off element is connected according to described first signal and is transmitted described the 3rd signal, and the second switch element is connected according to described secondary signal and transmit described the 3rd signal.

First on-off element is connected according to described the 3rd signal and is transmitted described first signal, and the second switch element is connected according to described the 3rd signal and transmit described secondary signal.

First sub-pixel is connected to the described first and the 3rd signal wire, and second sub-pixel is connected to the described second and the 4th signal wire.

First sub-pixel also comprises first holding capacitor that is connected on described first on-off element, and second sub-pixel also comprises second holding capacitor that is connected on the described second switch element.

Generation has first and second gray scale voltage group that differ from one another, and first pixel electrode is supplied to the voltage that is selected from described first gray scale voltage group, and second pixel electrode is supplied to the voltage that is selected from second gray scale voltage group.

Image information is processed producing first and second picture signals, and first and second pixel electrodes are supplied to corresponding to the voltage in the single gray scale voltage group of being selected from of described first and second picture signals.

The electric capacity ground coupling each other of first sub-pixel and second sub-pixel.

LCD according to the embodiment of the invention comprises: pixel comprises first sub-pixel and second sub-pixel; Gate line is connected to described first and second sub-pixels and transmits signal; First data line intersects with described gate line, and it is connected to described first sub-pixel, and transmits first data voltage; And second data line, intersecting with described gate line, it is connected to described second sub-pixel, and transmits described second data voltage.

First data voltage is different from described second data voltage, and first and second data voltages result from single image information.

The polarity of first data voltage is opposite with the polarity of described second data voltage.

It is constant that the polarity of first data voltage keeps in the given time.

Display device according to another embodiment of the present invention comprises: a plurality of pixels, be arranged as matrix, and each described pixel comprises first sub-pixel and second sub-pixel; A plurality of first grid polar curves are connected to described first sub-pixel, and the energising of transmission first grid is pressed; A plurality of second grid lines are connected to described second sub-pixel, and the energising of transmission second grid is pressed; A plurality of data lines intersect with described first and second gate lines, are connected to described first and second sub-pixels, and the transmission data voltage; Grey scale signal produces circuit, produces the first grey scale signal group and the second grey scale signal group; Select circuit, alternate selection and output first and second sets of signals; Data driver produces data voltage corresponding to view data based on the described first and second grey scale signal groups, and described data voltage is supplied to described data line; And gate drivers, described first and second grids energising is pressed supply to described first and second gate lines in turn.

Grey scale signal comprises analog gray voltages.

Select circuit to comprise analog switch, or the simulation Port Multiplier.This selection circuit is integrated into described data driver.Grey scale signal produces circuit and comprises that a plurality of aanalogvoltages produce circuit, and each described aanalogvoltage produces circuit and comprises a succession of resistor.

Grey scale signal comprises the digital gray scale data.

This display device also comprises the digital simulation electric pressure converter, and the digital gray scale data in its described grey scale signal group that will choose by described selection circuit are changed, to produce a plurality of grayscale voltages.

Select circuit to comprise a plurality of Port Multipliers that are connected on the described grey scale signal generation circuit.

The application that application that the first grid energising is pressed and second grid energising are pressed overlaps each other on part at least.

The duration that the first grid energising is pressed is equal to or less than the duration that the second grid energising is pressed.

LCD according to another embodiment of the present invention comprises: a plurality of pixels, be arranged as matrix, and each described pixel comprises first sub-pixel and second sub-pixel; A plurality of first grid polar curves are connected to described first sub-pixel, and the energising of transmission first grid is pressed; A plurality of second grid lines are connected to described second sub-pixel, and the energising of transmission second grid is pressed; A plurality of data lines intersect with described first and second gate lines, are connected to described first and second sub-pixels, and the transmission data voltage; Reference voltage generating circuit produces the reference voltage of a plurality of big or small periodically-varieds; Grayscale voltage produces circuit, produces a plurality of grayscale voltages based on described reference voltage; Data driver from the data voltage of described gray-scale voltage selection corresponding to view data, and is applied to described data line with described data voltage; And gate drivers, described first and second grids energising is pressed be applied to described first and second gate lines in turn.

According to the LCD of an embodiment more of the present invention, comprising: first and second gate lines extend parallel to each other basically and are isolated from each other; Data line intersects with described first and second gate lines; The first film transistor is connected to described first grid polar curve and described second data line; Second thin film transistor (TFT) is connected to described second grid line and described second data line; First show electrode is connected to described the first film transistor; And second show electrode, be connected to described second thin film transistor (TFT), wherein, described first and second show electrodes have the hypotenuse that faces with each other.

LCD according to still another embodiment of the invention comprises: first and second gate lines, extend and be isolated from each other at first direction; Data line intersects with described first and second gate lines; The first film transistor is connected to described first grid polar curve and described second data line; Second thin film transistor (TFT) is connected to described second grid line and described second data line; First show electrode is connected to described the first film transistor; And second show electrode, be connected to described second thin film transistor (TFT), wherein, described first show electrode is longer than described second show electrode in second direction, and described first show electrode is arranged in the second direction length of described second show electrode.

LCD according to another embodiment of the present invention comprises: first and second gate lines, extend and be isolated from each other at first direction; Data line intersects with described first and second gate lines; The first film transistor is connected to described first grid polar curve and described second data line; Second thin film transistor (TFT) is connected to described second grid line and described second data line; First show electrode is connected to described the first film transistor; And second show electrode, be connected to described second thin film transistor (TFT), wherein, each described first and second show electrode is basically with respect to the straight line symmetry of extending at described first direction.

This LCD also comprises the 3rd show electrode of facing with described first and second show electrodes.

In first and second show electrodes at least one has cut.

The 3rd show electrode has cut or projection.

In first and second show electrodes at least one and described the 3rd show electrode have the cut that is arranged alternately.

The cut of gap between first and second show electrodes and described the 3rd show electrode is arranged alternately.

This LCD also comprises and the overlapping storage electrode line of described first and second show electrodes.

Each described first and second thin film transistor (TFT) all have be connected to described first or the second grid line on gate electrode, be connected to the source electrode on the described data line and be connected to drain electrode on described first or second show electrode.

The voltage of first show electrode is different from the voltage of described second show electrode.

The voltage of described first show electrode that scheduled voltage deducts is less than the voltage of described second show electrode that is deducted by described predetermined voltage.

This LCD also comprise with described data line overlapping and be arranged at guard electrode as the described first and second display pixel electrodes.

Thin-film transistor display panel according to the embodiment of the invention comprises: gate line is formed at described substrate; First and second data lines intersect with described gate line insulation and with described gate line; The first film transistor is connected to described gate line and described first drain electrode and comprises first drain electrode; Second thin film transistor (TFT) is connected to described gate line and described second drain electrode and comprises second drain electrode; Passivation layer is formed at described gate line, described first and second data lines and described first and second thin film transistor (TFT)s, and has first contact hole that exposes described first data line and second contact hole that exposes described second data line; And pixel electrode, comprise by described first contact hole being connected to first pixel electrode on described first drain electrode, and be connected to second pixel electrode on described second drain electrode by described second contact hole.

This thin-film transistor display panel also comprise with first and second pixel electrodes insulation and with described gate line and described first and second data lines at least one overlapping guard electrode.

Pixel electrode and described guard electrode are arranged on the described passivation layer.

This thin-film transistor display panel also comprises storage electrode line, comprises with described first and second drain electrodes overlapping to form the storage electrode of memory capacitance.

Guard electrode and described storage electrode are supplied to single voltage.

Guard electrode covers described first and second data lines fully.

The zone of first pixel electrode is different from the zone of described second pixel electrode.

According to the driving method of the LCD of the embodiment of the invention, LCD wherein comprises a plurality of pixels, and each pixel comprises a plurality of sub-pixels, and described method comprises: receive input image data; Described view data is converted at least two data voltages; And at least two data voltages are applied to described sub-pixel.

Conversion wherein comprises: produce at least two group grayscale voltages; And from described two group grayscale voltages, select grayscale voltage corresponding to described input image data at least to produce data voltage.

Conversion wherein comprises: described input image data is converted at least two output image datas; And from described one group of grayscale voltage, select grayscale voltage corresponding to described at least two output image datas to produce data voltage.

Driving method according to the LCD of the embodiment of the invention, described LCD comprises a plurality of pixels that are arranged in matrix, each described pixel comprises first and second sub-pixels, and described method comprises: first data voltage that will have first polarity is applied to described first sub-pixel; And second data voltage that will have with described first opposite polarity second polarity is applied to described second sub-pixel.

First and second data voltages produce from the single image data.

Described first sub-pixel of neighbor has opposite polarity in the row, and described second sub-pixel of neighbor has opposite polarity in the row.

Described first sub-pixel of neighbor has identical polarity in the row, and described second sub-pixel of neighbor has identical polarity in the row.

Each data voltage is supplied at least two sub-pixels simultaneously.

A kind of driving method of LCD, described LCD comprises a plurality of pixels, and each described pixel comprises first sub-pixel and second sub-pixel, and described method comprises: transmit image data; Export first group of grayscale voltage; Described view data is converted to first data voltage that is selected from described first group of grayscale voltage; Described first data voltage is applied to described first sub-pixel; By using Port Multiplier to substitute first group of grayscale voltage with second group of grayscale voltage, output varies in size in described second group of grayscale voltage of described first group of grayscale voltage; Described view data is converted to second data voltage that is selected from described second group of grayscale voltage; And described second data voltage is applied to described second sub-pixel.

This method also comprises: produce first and second groups of grayscale voltages; Wherein, the output of first group of grayscale voltage comprises: select described first group of grayscale voltage by using Port Multiplier, and wherein, the output of second group of grayscale voltage comprises: select described second group of grayscale voltage by using Port Multiplier.

Returning method also comprises: store first and second groups of digital gray scale data; Wherein, the output of first group of grayscale voltage comprises: select described first group of digital gray scale data by using Port Multiplier; And described first group of digital gray scale digital simulation be converted to described first group of grayscale voltage, and wherein, the output of second group of grayscale voltage comprises: select second group of digital gray scale data by using Port Multiplier; And described second group of digital gray scale digital simulation be converted to described second group of grayscale voltage.

Description of drawings

By below in conjunction with the detailed description of accompanying drawing to the embodiment of the invention, the present invention will become apparent, wherein:

Fig. 1 is the block diagram according to the LCD of the embodiment of the invention;

Fig. 2 is the equivalent circuit diagram according to the pixel of the LCD of the embodiment of the invention;

Fig. 3 A, 3B and 3C are the block diagrams according to the LCD of the embodiment of the invention;

Fig. 4 A and 4B are the equivalent circuit diagrams according to the pixel of the LCD of the embodiment of the invention;

Fig. 5 A, 5B and 5C show the example of grayscale voltage generator and the data driver of the LCD shown in Fig. 3 A-4B;

Fig. 6 changes the have a resistance block diagram of device string of circuit and voltage according to the reference voltage of the embodiment of the invention;

Fig. 7 A is the gamma curve figure according to the LCD of the embodiment of the invention;

Fig. 7 B shows the figure of conduct according to the grayscale voltage of the function of the input gray level of the LCD of the embodiment of the invention;

Fig. 8 A, 8B and 8C show the signal waveform according to the LCD of the embodiment of the invention;

Fig. 9 is the block diagram of LCD according to another embodiment of the present invention;

Figure 10 is the block diagram according to the grayscale voltage generator of the embodiment of the invention;

Figure 11 is the block diagram of grayscale voltage generator according to another embodiment of the present invention;

Figure 12 shows the waveform of the various signals of the LCD shown in Fig. 9-11;

Figure 13 is the block diagram of LCD according to another embodiment of the present invention;

Figure 14 shows the waveform of the various signals among the LCD shown in Figure 13;

Figure 15 is the block diagram of LCD according to another embodiment of the present invention;

Figure 16 is the equivalent circuit diagram of the pixel of LCD according to another embodiment of the present invention;

Figure 17 A schematically shows according to the pixel arrangement of the embodiment of the invention and the polarity of data voltage;

Figure 17 B shows the polarity of the sub-pixel shown in Figure 17 A;

Figure 18 shows the waveform of the various signals of the LCD shown in Figure 17 A;

Figure 19 is the schematic layout pattern of the lower panel (tft array panel) according to the embodiment of the invention;

Figure 20 is the schematic layout pattern of the top panel (common electrode panel) according to the embodiment of the invention;

Figure 21 is the schematic layout pattern that comprises the LC panel assembly of tft array panel shown in Figure 19 and common electrode panel shown in Figure 20;

Figure 22 and 23 is respectively a LC panel assembly shown in Figure 21 sectional view along XXII-XXII and XXIII-XXIII intercepting;

Figure 24 is the schematic layout pattern of tft array panel according to another embodiment of the present invention;

Figure 25 is the block diagram of LCD according to another embodiment of the present invention;

Figure 26 is the equivalent circuit diagram of the pixel of LCD according to another embodiment of the present invention;

Figure 27 is the schematic layout pattern of the lower panel (tft array panel) according to the embodiment of the invention;

Figure 28 is the schematic layout pattern of the top panel (common electrode panel) according to the embodiment of the invention;

Figure 29 is the schematic layout pattern that comprises the LC panel assembly of tft array panel shown in Figure 27 and common electrode panel shown in Figure 28;

Figure 30 A and 30B are LC panel assembly shown in Figure 29 sectional views along line XXXA-XXXA and XXXB-XXXB intercepting;

Figure 31 is the schematic layout pattern of tft array panel according to another embodiment of the present invention;

Figure 32 A is the sectional view that tft array panel shown in Figure 31 intercepts along line XXXIIA-XXXIIA;

Figure 32 B is the sectional view that tft array panel shown in Figure 31 intercepts along line XXXIIB-XXXIIB; And

Figure 33 shows according to the row of the embodiment of the invention polarity of the pixel electrode in anti-phase.

Embodiment

Hereinafter with reference to accompanying drawing the present invention is described in detail, wherein, accompanying drawing shows according to a preferred embodiment of the invention.Yet the present invention can have multiple different way of realization and be not limited to embodiment described herein.

In the accompanying drawing, for clarity sake, enlarged the thickness in layer, film and zone.Identical reference numerals is all pointed to components identical.Be appreciated that when the element such as layer, film, zone and substrate " is positioned at " on another element, be meant that it is located immediately on another element, perhaps exists interference element therebetween.On the contrary, in the time of on element " is located immediately at " another element, being meant does not have interference element therebetween.

Below with reference to the LCD of Fig. 1 and 2 detailed description according to the embodiment of the invention.

Fig. 1 is the block diagram according to the LCD of the embodiment of the invention; Fig. 2 is the equivalent circuit diagram according to the pixel of the LCD of the embodiment of the invention.

With reference to Fig. 1, comprise LC panel assembly 300, be connected to gate drivers 400 and the data driver 500 on the panel assembly 300, the signal controller 600 that is connected to the grayscale voltage generator 800 on the data driver 500 and controls above-mentioned each element according to the LCD of the embodiment of the invention.

With reference to Fig. 1, panel assembly 300 comprises a plurality of signal wire (not shown) and a plurality of pixel PX that is connected thereto and is arranged in matrix basically.In ad hoc structure shown in Figure 2, panel assembly 300 comprises lower panel 100, top panel 200 and is folded in therebetween LC layer 3.

Signal wire comprises the gate line (not shown) of a plurality of transmission signals (being also referred to as " sweep signal "), and the data line (not shown) of a plurality of transmission of data signals.Extend on the direction that gate line is expert at basically, and parallel to each other basically, and data line extends in the direction of row basically, and parallel to each other basically.

With reference to Fig. 2, each pixel PX comprises a pair of sub-pixel PXa and PXb.Each sub-pixel PXa/PXb comprises liquid crystal (LC) capacitor Clca/Clcb and is connected to on-off element Qa/Qb on gate line, data line and the LC capacitor Clca/Clcb.

The on-off element Qa/Qb that comprises thin film transistor (TFT) (TFT) is arranged on the lower panel 100, and has three terminals: be connected to control terminal on the gate line, be connected to the input terminal on the data line and be connected to lead-out terminal on the LC capacitor Clca/Clcb.

LC capacitor Clca/Clcb comprises pixel electrode PEa/PEb and the common electrode CE on the top panel 200 of being arranged on as two terminals.LC layer 3 is arranged between electrode PEa/PEb and the CE, plays the dielectric effect of LC capacitor Clca/Clcb.A pair of pixel electrode PEa and PEb are isolated from each other and form pixel electrode PE.Common electrode CE is supplied to the whole surface that common-battery is pressed Vcom and covered top panel 200.In another embodiment, common electrode CE also can be arranged on lower panel 100, and the shape of at least one had bar among electrode PE and the CE or band.

For display color, each pixel PX represents a kind of (also promptly, separated by spaces) in the primary colors separately, and perhaps each pixel PX represents primary colors (also promptly, time-division) in turn, thereby the space of primary colors or time sum are identified as required color.The example of one group of primary colors comprises red, green and blue.Fig. 2 shows the example of separated by spaces, and wherein, each pixel PX is included in the face of representing wherein a kind of color filter CF of primary colors in the zone of the top panel 200 of pixel electrode 190.Selectively, color filter CF be arranged on pixel electrode PEa on the lower panel 100 or the PEb or under.

One or more polarizer (not shown) are connected in panel 100 and 200 at least one.

Referring again to Fig. 1, grayscale voltage generator 800 produces the relevant grayscale voltage of transmission a plurality of and pixel PX.Yet grayscale voltage generator 800 also can only produce the grayscale voltage (being also referred to as the benchmark grayscale voltage) to determined number, but not produces all grayscale voltages.

Gate drivers 400 is connected on the gate line of panel assembly 300, and synthesizes with press Von and grid pass voltage Voff from the grid energising of external device (ED), is used for the signal Vg of gate line with generation.

Data driver 500 is connected to the data line of panel assembly 300, and provides data voltage Vd to data line, and wherein this data voltage is selected from the grayscale voltage of being supplied with by grayscale voltage generator 800.Yet when grayscale voltage generator 800 produced the benchmark grayscale voltage, by distinguish benchmark grayscale voltage and selected data voltage Vd from the grayscale voltage that produces, data driver 500 also can produce the grayscale voltage that is used for all gray scales.

Signal controller control gate driver 400 and data-driven etc.

Carry in encapsulation (TCP) type at band, each driver element 400,500,600,700 and 800 can comprise that at least one is installed in LC panel assembly 300 or flexible print circuit (FPC) is gone up integrated circuit (IC) chip, and it is connected on the panel assembly 300.Selectively, at least one processing unit 400,500,600,700 and 800 can be integrated on the panel assembly 300 with signal wire and on-off element Qa and Qb.Selectively, all processing units 400,500,600,700 and 800 can be integrated on the single IC chip, but at least one processing unit 400,500,600,700 and 800 or processing unit 400,500,600,700 and 800 at least one at least one circuit component can be arranged on the outside of single IC chip.

Now with reference to Fig. 3 A, 3B, 3C, 4A and 4B detailed description LCD according to the embodiment of the invention.

Fig. 3 A, 3B and 3C are the block diagrams according to the LCD of the embodiment of the invention; Fig. 4 A and 4B are the equivalent circuit diagrams according to the pixel of the LCD of the embodiment of the invention.

With reference to Fig. 3 A-3C, according to an embodiment of the invention LCD comprise LC panel assembly 300, (to) gate drivers 400a, 400b, 410,420, data driver 500, grayscale voltage generator 800, and signal controller 600.

Panel assembly 300 comprises a plurality of signal wires and is connected thereto and is arranged in basically a plurality of pixel PX of matrix.

Signal wire is arranged at lower panel 100 (with reference to Fig. 2), and comprises many to gate line and a plurality of data line.

Fig. 4 A and Fig. 4 B show signal wire and pixel PX equivalent circuit diagram.Display signal line comprise gate lines G La, down gate lines G Lb, data line DL and with the storage electrode line SL of gate lines G La and the substantially parallel extension of GLb.

Each pixel PX shown in Fig. 4 A comprises a pair of sub-pixel Pxa and PXb, each sub-pixel PXa/PXb comprises the on-off element Qa/Qb at least one that is connected among gate lines G La/GLb and the data line DL, be connected to liquid crystal (LC) the capacitor Clca/Clcb on the on-off element Qa/Qb, and be connected to the holding capacitor Csta/Cstb between on-off element Qa/Qb and the storage electrode line SL.Holding capacitor Csta, Cstb can omit as required, and in this case, storage electrode line SL also can omit.

Each pixel PX shown in Fig. 4 B comprises a pair of sub-pixel Pxa, PXb, and is connected in the coupling condenser Ccp between sub-pixel Pxa and the PXb.Each sub-pixel PXa/PXb comprises the on-off element Qa/Qb at least one that is connected among gate lines G La and GLb and the data line DL, and is connected to liquid crystal (LC) the capacitor Clca/Clcb on the on-off element Qa/Qb.A sub-pixel Pxa comprises the holding capacitor Csta that is connected between on-off element Qa and the storage electrode line SL.

Holding capacitor Csta/Cstb is the auxiliary capacitor that is used for LC capacitor Clca/Clcb.Holding capacitor Csta/Cstb comprises pixel electrode PEa/PEb and independent signal wire, and it is arranged on the lower panel 100, and is overlapping by insulator and pixel electrode PEa/PEb, and is supplied to the predetermined voltage such as voltage supplied Vcom.Selectively, the adjacent gate polar curve that holding capacitor Csta/Cstb comprises pixel electrode PEa/PEb and is called previous gate line, its insulator and pixel electrode PEa/PEb are overlapping.

Referring again to Fig. 3 A to Fig. 3 C, gate drivers 400a, 400,410,420 is connected with gate lines G 1a-Gnb, and synthesizes the signal that is applied to gate lines G 1a-Gnb with generation with press Von and grid pass voltage Voff from the grid energising of external device (ED).Among Fig. 3 A, a pair of gate drivers 400a, 400b lay respectively at panel assembly 300 about, and be connected to odd and even number gate lines G 1a-Gnb.Each gate drivers 410,420 shown in Fig. 3 B and Fig. 3 C is positioned at a side of panel assembly 300, and is connected in all gate lines G 1a-Gnb.Gate drivers 420 shown in Fig. 3 C comprises two driving circuits 421,422, will be connected with odd and even number gate lines G 1a-Gnb respectively.

Grayscale voltage generator 800 produces two group (benchmark) grayscale voltages relevant with the transmission of pixel.Two groups of grayscale voltages supply to two sub-pixel Pxa, PXb individually.Each is organized grayscale voltage and comprises that relative common-battery pressure Vcom has the grayscale voltage of positive polarity and the grayscale voltage that relative common-battery presses Vcom to have negative polarity.Yet grayscale voltage generator 800 also can only produce one group of (benchmark) grayscale voltage.

Example referring now to grayscale voltage generator and data driver among the LCD shown in Fig. 5 A, 5B and the 5C further explanatory drawings 3A-4B.

LCD example shown in Fig. 5 A comprises data driver 500, grayscale voltage generator 800 and as the analog switch (SW) 850 of individual component.Grayscale voltage generator 800 comprises two voltages have a resistance device string GStr1, GStr2.Analog switch 850 is connected between grayscale voltage generator 800 and the data driver 500, and response selects signal SE to select from one group in two groups of grayscale voltages of grayscale voltage generator 800.

LCD example shown in Fig. 5 B is attached to data driver 500 with the analog switch 850 shown in Fig. 5 A.The common data driver unit of reference number 510 expressions.

LCD example shown in Fig. 5 C comprises that the reference voltage that substitutes grayscale voltage generator 800 changes circuit (VCC) 860.Reference voltage changes circuit 860 and produces the reference voltage that depends on selection signal SE and change its big or small some.Data driver 500 comprises the voltage that the produces grayscale voltage device string (GStr) 560 that has a resistance, and produces not on the same group gamma electric voltage according to changed reference voltage that circuit 860 supplies with by reference voltage.

Fig. 6 shows the reference voltage shown in Fig. 5 C and changes the have a resistance example of device string of circuit and voltage.

With reference to Fig. 6, the voltage device string 560 that has a resistance comprises the resistor R 201-R211 of a plurality of polyphones, central resistor R 206 and be connected five resistors of first and second groups of central resistor R 206 both sides.First group of resistor R 201-R205 has the end of the low-voltage of being connected to, and second group of resistor R 207-R211 has the end that is connected to service voltage AVDD.

Reference voltage changes circuit 860 and comprises NPN and PNP bipolarity (bipolar) transistor Q1, Q2, Q3, a pair of resistor R 1 and diode D1, and another is to resistor R 2 and diode D2.NPN and PNP bipolar transistor Q1, Q2, Q3 be connected to central resistor R 206, first group of resistor R 201-R205, and second group of resistor R 207-R211 between.This is connected between transistor Q1, Q2, the Q3 resistor and diode R1, D1 and R2, D2.PNP transistor Q4 is connected between the high voltage input terminal and transistor Q3 of supplying with service voltage (supply voltage) AVDD, and transistor Q4 has the base stage of supplying with low-voltage by resistor R 5, R7, and is connected to transistor Q3 by diode D3.NPN transistor Q2 is connected to by resistor R 3 and selects signal SE input end, and PNP transistor Q3 is connected to the high voltage input end by resistor R 4, R6.Capacitor C2 is connected between the base stage of transistor Q1, Q3, and capacitor C1 is connected between transistor Q2 and the Q4 by resistor R 3, R5, and capacitor C3 is connected between resistor R 4, the R6.

Change in the circuit 860 at this reference voltage, transistor Q3 is in on-state all the time, with transmission service voltage AVDD.If selecting signal SE is low value, then transistor Q4 is closed, and is connected with high-tension to cut off, and connects transistor Q2, to form the path that arrives low-voltage.Therefore, contact N1, N2 are supplied to low-voltage.

On the contrary, be high value if select signal SE, then transistor Q2 closes, cutting off and being connected of low-voltage, and connection transistor Q4, with the high-tension path of formation arrival.Therefore, be supplied to the high voltage that determines by resistor R 1, R6 etc. at contact N1, N2.

To describe the operation of above-mentioned LCD below in detail.

The input control signal that signal controller 600 is supplied to received image signal R, G, B and is used to control its demonstration from the external graphics controller (not shown).Received image signal R, G, B contain the monochrome information of each pixel PX, and this brightness has predetermined value, for example, have 1024 (=2 ¹⁰), 256 (=2 ⁸), or 64 (=2 ⁶) individual gray scale.Input control signal comprises vertical synchronizing signal Vsync, horizontal-drive signal Hsync, major clock MCLK and data enable signal DE etc.

Based on input control signal and received image signal R, G, B, after producing picture signal R, G that grid control signal CONT1 and data controlling signal CONT2 and processing be suitable for the operation of panel assembly 300, B, signal controller 600 is transferred to gate drivers 400a, 400b, 410,420 with grid control signal CONT1, and picture signal DAT and the data controlling signal CONT2 that handles is transferred to data driver 500.The processing of picture signal R, G, B comprises according to the pixel arrangement of panel assembly shown in Figure 3 300 arrange view data R, G, B again.

Grid control signal CONT1 comprises the scanning commencing signal STV that indication begins to scan, and is used to control at least one clock signal that the output time of Von is pressed in the grid energising.Grid control signal CONT1 can also comprise and is used to limit the output enable signal OE that the duration of Von is pressed in the grid energising.Clock signal can be used as the selection signal SE shown in Fig. 5 A-5C and Fig. 6 and uses.

Data controlling signal CONT2 comprises that notice begins the horizontal synchronization commencing signal STH of data transmission to one group of sub-pixel Pxa, PXb, and indication is supplied with the load signal LOAD of data voltage and data clock signal HCLK to data line D1-Dm.Data controlling signal CONT2 can comprise inversion signal RVS, is used for the polarity (with respect to voltage supplied Vcom) of oppisite phase data voltage.

Response is from the data controlling signal CONT2 of signal controller 600, data driver 500 receives the view data DAT that is used for a group of sub-pixel Pxa, PXb from signal controller 600, and receives by one group in two groups of grayscale voltages of grayscale voltage generator 800 supplies.Data driver 500 will be selected from the view data DAT converting analogue data voltage in the grayscale voltage of being supplied with by grayscale voltage generator 800, and data voltage is supplied to D1-Dm.

Therewith differently, shown in Fig. 5 A, separately circuit 850 is selected in the outside that is provided with, but not data driver 500 is selected and transmitted in two groups of grayscale voltages one group to data driver 500.In another embodiment shown in Fig. 5 C, grayscale voltage generator 800 provides the reference voltage of size variation, and it carries out dividing potential drop by data driver 500, to form grayscale voltage.

Gate drivers 400a, 400b, 410,420 responses press Von to put on gate lines G 1a-Gnb the grid energising from the grid control signal CONT1 of signal controller 600, therefore, connect the on-off element Qa, the Qb that are connected thereto.The data voltage that puts on data line D1-Dm is applied to sub-pixel Pxa, PXb by on-off element Qa, the Qb that connects.

Data voltage and common-battery press the difference between the Vcom to be expressed as the voltage at LC capacitor Clca, Clcb two ends, and it is also referred to as pixel voltage.LC molecule among LC capacitor Clca, the Clcb changes according to the pixel voltage size and carries out orientation, and the orientation of molecule has determined the deflection by the light of LC layer 3.This deflection is converted to optical transmission with the deflection of light, thereby pixel PX shows the brightness by picture signal DAT representative.

Shown in Fig. 7 A, two groups of above-mentioned grayscale voltages show two kinds of gamma curve Ta, Tb that differ from one another.Because two groups of two sub-pixel Pxa, PXb that are supplied to pixel PX, therefore, the resultant curve T of two gamma curve has promptly formed the gamma curve of pixel PX.Preferably determine two groups of grayscale voltages, thus the benchmark gamma curve of synthetic gamma curve T during near top view.For example, the synthetic gamma curve during top view during with top view optimal benchmark gamma curve consistent, and the synthetic gamma curve T of side and front benchmark gamma curve are the most approaching.GS1 and GSf mean minimum input gray level and the highest input gray level respectively among Fig. 7 A.For example, the gamma curve that is positioned at downside will further reduce to improve visuality.

Repeat said process, all gate lines G with 1/2 horizontal cycle (it is represented with " 1/2H ", and equals the half period of horizontal-drive signal Hsync or data enable signal DE) _1a-G _NbIn a frame, be supplied to the grid energising in turn and press Von, therefore data voltage is applied to all pixels.

When after a frame end, beginning next frame, be applied to the anti-phase control signal RVS Be Controlled on the data driver 500, thereby the polarity of data voltage is by anti-phase (it is also referred to as " frame is anti-phase ").Also the anti-phase control signal RVS of may command makes that the polarity of image transmitted data-signal is anti-phase (for example on a frame intercycle ground in the data line, row is anti-phase and point is anti-phase), perhaps at an encapsulation (packet, the polarity of the viewdata signal bag) is by anti-phase (for example, row are anti-phase anti-phase with point).

Yet because the gate line of this LCD is the twice of common LCD gate line, therefore, the duration of charging of above-mentioned LCD may be too short for pixel PX reaches its object brightness, and anti-phasely also may reduce the duration of charging.

Can increase the duration of charging by grid energising pressure is applied to partly overlapping adjacent two gate lines, and this can realize by using the gate drivers shown in Fig. 3 A and the 3B.

Describe the several types of application data voltage in detail below with reference to Fig. 8 A, 8B, 8C.

Fig. 8 A, 8B, 8C show the signal waveform according to the LCD of the embodiment of the invention.Label Vga is meant the signal that puts on the upper gate line, and label Vgb is meant the signal that puts on the bottom gate line, and label Vd is meant the data voltage that is carried by data line.

In the anti-phase situation of point, because the polarity of neighbor is opposite, so providing yet of the data voltage of neighbor can not improved the duration of charging significantly.Therefore shown in Fig. 8 A, preferably, the duration of charging that is used for neighbor overlaps each other, and the duration of charging of the adjacent subpixels of a pixel overlaps each other.In addition, preferably, the size of one group of grayscale voltage of charging sub-pixel is greater than the size that is applied to one group of grayscale voltage on the sub-pixel that at first charges, shown in Fig. 8 A and Fig. 8 B after being applied to.

In the anti-phase situation of row, because the polarity of two adjacent pixels is identical in the row, sub-pixel can be used the data voltage precharge of neighbor, and therefore, shown in Fig. 8 B, the duration of charging of all adjacent subpixels is overlapping in the given time.

Fig. 8 C showed at the gate drivers shown in Figure 1B in the identical time, only was applied to the logical voltage condition of a grid on the gate line.

Describe LCD according to another embodiment of the present invention in detail below with reference to Fig. 9,10 and 11.

Fig. 9 is the block diagram of LCD according to another embodiment of the present invention; Figure 10 is the block diagram according to the grayscale voltage generator of the embodiment of the invention; Figure 11 is the block diagram of grayscale voltage generator according to another embodiment of the present invention.

The structure of LCD shown in LCD shown in Fig. 9 and Fig. 3 B much at one.That is, LCD comprises LC panel assembly 300, gate drivers 430, data driver 500, grayscale voltage generator 900 and signal controller 600.

Signal controller 600 according to present embodiment produces and exports the selection signal SE that is used to control grayscale voltage generator 900.

According to the grayscale voltage generator 900 of present embodiment or produce two groups of independent analog gray voltages, and response selects signal SE alternately to export two groups of grayscale voltages, perhaps selects in two groups of digital gray scale data of opsition dependent storage one group and produce one group of analog gray voltages based on the digital gray scale data of selecting.The latter's situation can find out that two groups of analog gray voltages corresponding to two groups of digital gray scale voltages are arranged alternately.Two groups of grayscale voltages supply to two sub-pixels that form pixel respectively.Each organizes the grayscale voltage that grayscale voltage comprises that relative common-battery presses Vcom to have positive polarity and negative polarity.As mentioned above, grayscale voltage generator 900 only produces the benchmark grayscale voltage of giving determined number, but not all grayscale voltages.

Grayscale voltage generator 900 shown in Figure 10 comprises register cell 910, data selection unit 920 and converting unit 930.

Register cell 910 comprises a pair of digital register 911,912, and storage is had one to one corresponding not gradation data γ on the same group _1a-γ _Xa, γ _1b-γ _Xb

Data selection unit 920 comprises a plurality of Port Multipliers (MUX), and it is connected to digital register 911,912.Each Port Multiplier (MUX) receives a pair of voltage (r _1ar _1b, r _2ar _2b..., r _Xar _Xb) select signal SE to export the voltage (r of one of them reception as input and response from digital register 911,912 _1ar _1b, r _2ar _2b..., r _Xar _Xb).

Converting unit 930 comprises a plurality of digital-analog convertors (DAC), and it is connected respectively to Port Multiplier (MUX).Each digital-analog convertor (DAC) will be converted to aanalogvoltage (r by Port Multiplier (MUX) supplied digital data ₁, r ₂..., r _X) and export aanalogvoltage (r ₁, r ₂..., r _X).

Grayscale voltage generator 900 shown in Figure 11 comprises voltage generator 940 and simulation Port Multiplier AMUX 950.

Voltage generator 940 comprises a pair of resistor string 941 and 942.Each resistor string 941 and 942 produces one group of grayscale voltage, and two groups of grayscale voltages have different sizes.

Simulation Port Multiplier 950 is according to selecting signal SE to select and export two groups of grayscale voltages one group from voltage generator 940.

Operation below with reference to the LCD shown in Figure 12 further explanatory drawings 9-11.

Figure 12 shows the oscillogram of the various signals of the LCD shown in Fig. 9-11.

As previously mentioned, signal controller 600 is handled picture signal R, G, B based on input control signal and received image signal R, G, B.Signal controller 600 produces grid control signal CONT1, data controlling signal CONT2, reaches and select signal SE.Signal controller 600 is transferred to gate drivers 430 with grid control signal CONT1, data controlling signal CONT2 and treated picture signal DAT are transferred to data driver 500, and signal controller 600 will select signal SE to be transferred to grayscale voltage generator 900.

Grid control signal CONT1 comprises scanning commencing signal STV and at least one clock signal, and may further include output enable signal OE, is used to limit the duration that Von is pressed in the grid energising.Data controlling signal CONT2 comprises horizontal synchronization commencing signal STH, and load signal LOAD, and data clock signal HCLK also may further include inversion signal RVS, are used for the polarity of oppisite phase data voltage.

Selecting signal SE is exactly that indication is selected a kind of indicator signal of signal from two groups of grayscale voltages that grayscale voltage generator 900 produces, and has and the identical cycles such as horizontal synchronization commencing signal STH, load signal TP.

The cycle of the clock signal in grid control signal CONT1 may be the twice of horizontal synchronization commencing signal STH, and in this case, clock signal can be used as selects signal SE.

The pulse of the horizontal synchronization commencing signal STH of data driver 500 response signal controllers 600 receives and to be used for one group of pixel PX, for example with the image information di of the pixel of the synchronous i pixel column of data clock signal HCLK.During receiving view data di, data driver 500 is applied to data line D1-Dm with the data voltage of former pixel column.After receiving view data di, grayscale voltage generator 900 is by one group of (benchmark) grayscale voltage selecting signal SE decision, data driver 500 is converted to the analog data voltage that is selected from grayscale voltage with image information di, and this data voltage is applied to data line D1-Dm.

As mentioned above, data driver 500 can produce the grayscale voltage that is carried out dividing potential drop by the benchmark grayscale voltage.

Gate drivers 400 response grid control signal CONT1 press Von to be applied to gate lines G 1a-Gnb the grid energising, for example, are connected to the gate line of top sub-pixel PXa at the i pixel column, thereby connect the on-off element Qa that is connected thereto.The data voltage that is applied on the data line D1-Dm is applied to sub-pixel PXa by the on-off element Qa that connects.

Then, signal controller 600 changes the value of selecting signal SE, makes grayscale voltage generator 900 produce and export other group (benchmark) grayscale voltage to data driver 500.Then, data driver 500 is reselected the grayscale voltage of corresponding each view data di from new grayscale voltage, it is imposed on respective data lines D1-Dm as data voltage.

Gate drivers 430 response grid control signal CONT1 press Von to be applied to gate lines G 1a-Gnb the grid energising, for example, are connected to the gate line of lower sub pixel PXb in the i pixel column, thereby connect the on-off element Qb that is connected thereto.The data voltage that is applied to data line D1-Dm is applied to sub-pixel PXb by the on-off element Qb that connects.

Describe LCD according to another embodiment of the present invention in detail below with reference to Figure 13 and Figure 14.

Figure 13 is the block diagram of LCD according to another embodiment of the present invention; Figure 14 shows the waveform of the various signals among the LCD shown in Figure 13.

LCD as shown in figure 13 almost has identical structure with LCD shown in Figure 9.That is, the LCD according to present embodiment comprises LC panel assembly 300, gate drivers 440, data driver 500, grayscale voltage generator 900, reaches signal controller 600.

Yet, signal controller 600 according to present embodiment no longer produces selection signal SE, and grayscale voltage generator 800 produces one group (benchmark) grayscale voltage relevant with the pixel transmission rate with data driver 500, and produces data voltage based on this (benchmark) grayscale voltage.

On the contrary, signal controller 600 is converted to a pair of output image signal DATa, DATb with received image signal R, G, B.Here, the conversion of picture signal is by being undertaken by the step of experiment decision, and is stored in the question blank (not shown) and by the operation of signal controller 600 and undertaken.

The horizontal synchronization commencing signal STH of data driver 500 response signal controllers 600 and data clock signal HCLK receive one group of sub-pixel Pxa, PXb, for example view data of the top sub-pixel Pxa of i pixel column synchronously.Receive during the view data dia, data driver 500 is applied to data line D1-Dm with the data voltage of former pixel column lower sub pixel PXb.After receiving view data dia, according to the pulse of the load signal TP of signal controller 600, grayscale voltage generator 900 is converted to the analog data voltage that is selected from the grayscale voltage with view data dia, and this data voltage is applied to data line D1-Dm.

Gate drivers 400 response grid control signal CONT1 press Von to be applied to gate lines G 1a-Gnb the grid energising, and for example therefore the upper gate line Gia of i pixel column connects the on-off element Qa that is connected thereto.The data voltage that is applied to data line D1-Dm is applied to sub-pixel PXa by the on-off element Qa that connects.Among Figure 14, label gia, gib represent to be applied to the top of i pixel column and the signal on bottom gate lines G ia, the Gib respectively.

In addition, after the transmission of the view data dia of the upside sub-pixel Pxa that finishes the i pixel column, signal controller 600 with the view data dib of the downside sub-pixel PXb of i pixel column together with the new burst transmissions of horizontal-drive signal STH to data driver 500.Then, signal controller 600 provides pulse to load signal TP, thereby makes data driver 500 select the grayscale voltage of corresponding each view data dib again in grayscale voltage, and selected grayscale voltage is applied to data line D1-Dm as data voltage.

Gate drivers 400 response grid control signal CONT1 press Von to be applied to next gate lines G 1a-Gnb the grid energising, for example, are applied to the bottom gate lines G ib of i pixel column, thereby connect the on-off element Qb that is connected thereto.The data voltage that is applied to data line D1-Dm is applied to sub-pixel PXb by the on-off element Qb that connects.

As mentioned above, view data is converted to a pair of output image data, will make a pair of sub-pixel Pxa, PXb have the transmissivity that differs from one another.Therefore, shown in Fig. 7 A, two sub-pixel Pxa, PXb present gamma curve Ta, the Tb that differs from one another, pixel PX gamma curve be exactly from the synthetic curve T of gamma curve Ta, Tb.

Describe LCD according to another embodiment of the present invention in detail below with reference to Figure 15,16,17A, 17B and 18.

Figure 15 is the block diagram of LCD according to another embodiment of the present invention; Figure 16 is the equivalent circuit diagram of the pixel of LCD according to another embodiment of the present invention; Figure 17 A schematically shows according to the pixel arrangement of the embodiment of the invention and the polarity of data voltage; Figure 17 B shows the polarity of the sub-pixel shown in Figure 17 A; Figure 18 shows the waveform of the various signals of the LCD shown in Figure 17 A.

The structure of LCD shown in LCD shown in Figure 15-18 and Fig. 3 A much at one.That is, LCD comprises LC panel assembly 300, a pair of gate drivers 440a and 440b, data driver 500, grayscale voltage generator 800 and signal controller 600.

As shown in figure 15, LC panel assembly 300 comprises many to gate lines G 1a-Gnb, a plurality of data line D0-Dm, and a plurality of pixels.The quantity of data line D0-Dm is more than the LCD shown in Fig. 3 A.

Shown in Figure 16 and Figure 17 A, each pixel PX comprises two sub-pixel Pxa, PXb.PXa (below be called first sub-pixel) comprises the on-off element Qa that is connected with upper gate line and left data line, the LC capacitor Clca that is connected with on-off element Qa, and the holding capacitor Csta that is connected with on-off element Qa.Form the pixel electrode 190a shape triangular in shape of LC capacitor Clca.

Another sub-pixel PXb (below be called second sub-pixel) comprises the on-off element Qb that is connected with bottom gate line and right side data line, the LC capacitor Clcb that is connected with on-off element Qb, and the holding capacitor Cstb that is connected with on-off element Qb, form the pixel electrode 190b of LC capacitor Clcb and the pixel electrode 190b interval predetermined gap of the first sub-pixel Pxa, and pixel electrode 190a and 190b form rectangle basically.

Anti-phase type is anti-phase for row, shown in Figure 17 A, is listed as and anti-phasely will makes that among each pixel PX, the polarity of the first sub-pixel Pxa and the second sub-pixel PXb is opposite.Have identical polarity along the first sub-pixel Pxa among two adjacent pixel PX of column direction, the second sub-pixel PXb that follows among two adjacent pixel PX of direction has opposite polarity.

As shown in figure 18, because the problem of the duration of charging deficiency that gate line number increase twice causes, overlapping apply the time of signal ga, gb to two adjacent gate lines in order to replenish can carry out precharge.With reference to the annexation shown in Figure 17 A, the first sub-pixel Pxa carries out precharge with the data voltage of the second sub-pixel PXb of the left pixel PX of upside pixel column, and the second sub-pixel PXb carries out precharge with the data voltage of the first sub-pixel Pxa of right pixel PX.Anti-phase the comparing of point with the polarity of the data voltage that transmits in the oppisite phase data line is listed as the anti-phase precharge of carrying out easily.Among Figure 18, label Vd represents to put on the data voltage of tentation data line, and label Vpa represents the voltage of first sub-pixel, and label Vpb represents the voltage of second sub-pixel.

When the sub-pixel of pixel is connected to different data lines, and data driver 500 carries out aforesaid row when anti-phase, considers that the obvious anti-phase type of sub-pixel is anti-phase for point.Therefore LCD has the advantage that row are anti-phase and point is anti-phase concurrently.

In addition, because each pixel is of similar shape, therefore can increase picture quality.

Describe the example of aforesaid LC panel assembly in detail below with reference to Figure 19,20,21,22,23 and 24.

Figure 19 is the schematic layout pattern of the lower panel (tft array panel) according to the embodiment of the invention; Figure 20 is the schematic layout pattern of the top panel (common electrode panel) according to the embodiment of the invention; Figure 21 is the schematic layout pattern that comprises the LC panel assembly of tft array panel shown in Figure 19 and common electrode panel shown in Figure 20; Figure 22 and 23 is respectively a LC panel assembly shown in Figure 21 sectional view along XXII-XXII and XXIII-XXIII intercepting; Figure 24 is the schematic layout pattern of tft array panel according to another embodiment of the present invention.

Figure 19-23 shows the example of the LC panel assembly of the LCD shown in Fig. 4 A, and Figure 24 is the example of the LC panel assembly of the LCD shown in Fig. 4 B.Following description mainly concentrates on the panel assembly shown in Figure 19 and 23, and the different characteristic that the panel shown in Figure 24 is set up also will be described.

Shown in Figure 19-23, comprise tft array panel 100, and the common electrode panel 200 faced of tft array panel 100 and be folded in liquid crystal layer 3 between panel 100 and 200 according to the LC panel assembly of present embodiment.

At first with reference to Figure 19, Figure 21-23, and Figure 24 describe tft array panel 100 in detail.

Many such as forming on the dielectric base 110 of transparent glass or plastics etc. to first and second gate line 121a and 121b and a plurality of storage electrode line 131.In Figure 24, also be formed with a plurality of connection electrode 126 in the substrate 110.

Gate line 121a, 121b transmit signal, will be basically in horizontal expansion, and physics and electrical separation each other.The a pair of first and second gate line 121a, 121b lay respectively at relative upside and downside, and comprise respectively a plurality of grid 124a, the 124b that protrudes to downside and upside.Each gate line 121a, 121b also comprise end 129a, the 129b with big zone, contacting with another layer or external drive circuit, and are arranged on the left and right sides of substrate 110.Yet the position of both ends 129a, 129b also can be the left side or the right side of substrate 110.The gate driver circuit (not shown) that is used to produce signal can be installed on flexible print circuit (FPC) film (not shown), and it can be connected in the substrate 110, or is directly installed in the substrate 110, or is integrated in the substrate 110. Gate line 121a and 121b are extensible to be connected on the driving circuit that can be integrated in the substrate 110.

Storage electrode line 131 is supplied to the predetermined voltage of pressing Vcom such as common-battery, and each storage electrode line 131 includes the branch line that almost extends in parallel with gate line 121a, 121b and many to first and second storage electrode 137a, 137b.Each storage electrode line 131 is between first grid polar curve 121a and second grid line 121b, and it is than the more close first grid polar curve of second grid line 121b 121a.

The first storage electrode 137a is longer and narrower than the second storage electrode 137b.Yet storage electrode line 131 shown in Figure 24 includes only a storage electrode 137 corresponding to the first storage electrode 137a.Storage electrode line 131 can have various shape and arrange.

Capacitance electrode 126 as shown in figure 24 is adjacent with storage electrode 137, and is parallel to storage electrode 137 substantially parallel extensions.Capacitance electrode 126 comprises the projection of downward protrusion, is used for contacting with another layer.

Gate line 121 and storage electrode line 131 preferably by such as aluminiferous metals such as aluminum or aluminum alloy, such as silver or silver alloy etc. contain silver metal, such as copper-containing metals such as copper or aldary, such as molybdenum or molybdenum alloy etc. contain molybdenum, chromium, tantalum, and titanium etc. make.Yet it can have the sandwich construction that comprises two conductive film (not shown), and these two conductive films have different physical characteristicss.The low resistivity metal that in two films one preferably contains the AI metal by comprising, contain the Ag metal and contain the Cu metal is made, and another film is preferably by having the metal that has good physics, chemistry and a contact characteristics with other materials such as indium tin oxide target (ITO) and indium zinc oxide (IZO) and make such as containing Mo metal, Cr, Ta or Ti etc.Two films be that lower floor is the Cr film in conjunction with preferred exemplary, and the upper strata is AI (alloy) film, and lower floor is AI (alloy) film and the upper strata is Mo (alloy) film.Yet gate line 121a and 121b and storage electrode line 131 also can be made by various other material and conductors.

The side of gate line 121a and 121b and storage electrode line 131 is with respect to the surface tilt of substrate, and its pitch angle is about 30 ° to 80 °.

On gate line 121a, 121b and storage electrode line 131, form the gate insulator of making by silicon nitride (SiNx) or monox (SiOx) etc. 140.

On gate insulator 140, form a plurality of semiconductor tapes 151 that form by amorphous silicon hydride (abbreviating " a-Si " as) or polysilicon etc.Each semiconductor tape 151 is basically at longitudinal extension, and comprises respectively a plurality of first and second projection 154a, 154b towards the first and second grid 124a, 124b branch.Semiconductor tape 151 is basically at longitudinal extension, and broadens during near gate line 121a, 121b and storage electrode line 131, thus the big zone of semiconductor tape 151 covering gate polar curve 121a and 121b and storage electrode line 131.

On semiconductor 151, form a plurality of Ohmic contact bands and island 161,165.Ohmic contact band and island 161,165a are preferably made by the n+ hydrogenation a-Si such as the heavy doping n type impurity of phosphorus, or are made by silicide.Each Ohmic contact band 161 comprises a plurality of projection 163a, and this projection 163a and Ohmic contact island 165a are positioned on the projection 154a of semiconductor tape 151 in pairs.

Although not shown, the many of semiconductor tape 151 are arranged in pairs on the second projection 154b of semiconductor tape 151 projection (not shown) and semiconductor island (not shown).

The side of semiconductor tape 151 and Ohmic contact part 161,165a is with respect to the surface tilt of substrate 110, and its pitch angle is preferably 30 ° to 80 °.

Form a plurality of data lines 171 and many on Ohmic contact part 161,165a and the gate insulator 140 to first and second drain electrode 175a, 175b.

Data line 171 transmission of data signals, and basically at longitudinal extension, with gate line 121a with 121b and storage is connected 135a and 135b intersects.Each data line 171 comprises a plurality of first and second source electrode 173a, the 173b that gives prominence to towards first and second gate electrode 124a, 124b respectively, and is bent into the letter C type.Each data line 171 also comprises the end 179 with big zone, is used to contact another layer or external drive circuit.The data drive circuit (not shown) that is used to produce data-signal is installed on FPC film (not shown), and it can be connected in the substrate 110, or is directly installed in the substrate 110, or is integrated in the substrate 110.Data line 171 is extensible directly to be connected with this data drive circuit that is integrated in the substrate 110.

First and second drain electrode 175a, 175b separate with data line 171, and the relative first and second source electrode 173a of first and second gate electrode 124a, 124b, 173b are provided with relatively.Among first and second drain electrode 175a, the 175b each includes wide end 177a or 177b and narrow end. Wide end 177a or 177b and first and second storage electrode 137a, 137b are overlapping, and narrow end is positioned on first and second projection 154a or the 154b, and part is by the first or second source electrode 173a and 173b defendance.

Yet the second drain electrode 175b shown in Figure 24 is not shorter relatively, and the first drain electrode 175a and storage electrode 137 and connection electrode 126 are overlapping.

Gate electrode 124a/124b, source electrode 173a/173b and drain electrode 175a/175b form TFT Qa and Qb with semiconductor island 154a/154b, it has the passage that is formed on the semiconductor island 154a/154b, and this semiconductor island is arranged between source electrode 173a/173b and the drain electrode 175a/175b.

Preferably, data line 171 and drain electrode 175a, 175b are made by refractory metals such as Cr, Mo, Ta, Ti or its alloys, yet it also can have the sandwich construction that comprises infusibility metal level (not shown) and low resistance device conductive layer (not shown).Sandwich construction be exemplified as double-decker, comprise Cr/Mo (alloy) film of lower floor and AI (alloy) film on upper strata, and three-decker, comprise Mo (alloy) film of lower floor, the AI in middle layer (alloy) film, and the Mo on upper strata (alloy) film.Yet data line 171 and gate electrode 175a, 175b can be made by in addition multiple metal or conductor.

Preferably, data line 171 and drain electrode 175a, 175b have the edge contour of inclination, and the scope at its inclination angle is 30 ° to 80 °.

Semiconductor island 152,154a and the 154b that Ohmic contact part 162,163a and 165a only place lower floor with and the conductor 171 on top, 175a, 175b between, and reduced contact resistivity therebetween.Although in most of zone, semiconductor tape 151 is narrower than data line 171, as mentioned above, broadens with the width of the approaching semiconductor tape 151 of gate line 121a, 121b and storage electrode line 131, and make surface profile level and smooth, thereby prevent the disconnection of data line 171.Semiconductor tape 151 comprises some not by the exposed portions serve of data line 171 and drain electrode 175a, 175b covering, for example, and the part between source electrode 173 and drain electrode 175a, 175b.

On the exposed portions serve of data line 171 and drain electrode 175a, 175b and semiconductor 151, form passivation layer 180.Passivation layer 180 is preferably made by inorganic or organic insulator, and has an even surface.The example of inorganic insulator comprises silicon nitride and monox.Preferably, organic insulation substrate has photonasty, and its specific inductive capacity is about below 4.0.But passivation layer 180 can comprise the following film of inorganic insulator and the upper film of organic insulator, thereby can have good organic insulation feature, prevents that simultaneously the exposed parts of semiconductor island 152,154a and 154b from being damaged by organic insulator.

Form on the passivation layer 180 and expose the end 179 of data line 171 and a plurality of contact holes 182,187a, the 187b of drain electrode 175a, 175b respectively, be formed with a plurality of contact hole 181a, the 181b of the end 129a, the 129b that expose gate line 121a, 121b on passivation layer 180 and the gate insulator 140.Among Figure 24, also form a plurality of contact holes 186 of the end of exposing connection electrode 126 on passivation layer 180 and the gate insulator 140.

Form a plurality of pixel electrodes 190 that comprise first and second pixel electrode 190a, 190b respectively on the passivation layer 180, a plurality of protection (shielding) electrode 88, and a plurality of contact auxiliary member 81a, 81b, 82.It is preferably made by transparent conductors such as ITO or IZO or such as reflectivity conductors such as Ag, AI, Cr and its alloys.

The first/the second pixel electrode 190a/190b is by the contact hole 185a/185b and the first/the second drain electrode 175a/175b physics and the electric connection, thereby reception is from the data voltage of the first/the second drain electrode 175a/175b.Among Figure 24, the second pixel electrode 190b is connected with connection electrode 126 by contact hole 186, and the first pixel electrode 190a and connection electrode 126 are overlapping.

Pixel electrode 190a, the 190b of supply data voltage forms electric field with the common electrode 270 of supply voltage supplied, and it determines the arrangement of the liquid crystal molecule (not shown) of the liquid crystal layer 3 between two electrodes 190,270.Pixel electrode 190a/190b and common electrode 270 form LC capacitor Clca/Clcb, and it still keeps the voltage of supply after TFT closes.And in order to strengthen the voltage hold facility, holding capacitor Csta, Cstb are by with first and second pixel electrode 190a, 190b and have the drain electrode 175a of the first and second storage electrode 137a, 137b etc. and 175b is overlapping forms.

Each pixel electrode 190 is notched in the corner, left side, and the relative gate line 121 of the hypotenuse of the corner cut of pixel electrode 190 is miter angle.

Each pixel electrode 190 comprises a pair of first and second pixel electrode 190a, 190b, the gap 194 that its each interval is set, and have the shape of rectangle.The antiparallelogram of the first pixel electrode 190a for rotating, and have the limit, left side that is provided with near the second storage electrode 137b, the right edge that limit, relative left side is provided with, and relative gate line 121a, 121b are the upside hypotenuse and the downside hypotenuse of 45.The second pixel electrode 190b comprises a pair of trapezoidal portion of the hypotenuse of facing the first pixel electrode 190a and faces the longitudinal part on limit, first pixel electrode 190a left side.

Therefore, gap 94 between the first pixel electrode 190a and the second pixel electrode 190b has uniform width basically, and comprises the longitudinal part 92 that is the top of 45 and bottom oblique line portion 91,93 and has even width basically with gate line 121a, 121b.

The first pixel electrode 190a has the cut 95 of extending along storage electrode line 131, and is divided into the first half and Lower Half according to this cut 95.The inlet of cut 95 is formed on the right edge of the first pixel electrode 190a, and the inlet of cut 95 has respectively a pair of hypotenuse substantially parallel with the top oblique line portion 91 in gap 94 and bottom oblique line portion 93.Gap 94 forms anti-phase symmetry with cut 95 relative storage electrode lines 131.

At this moment, the quantity of separating part or the quantity of cut is according to design factor, for example, and the size of pixel electrode 190, the ratio of the horizontal edge of pixel electrode 190 and longitudinal edge, the feature of liquid crystal layer 3 and kind etc.

Below, for convenience of explanation, gap 94 is expressed as cut.

In addition, the first pixel electrode 190a and first grid polar curve 121a are overlapping, and the second pixel electrode 190b and first and second gate line 121a, 121b are overlapping.First grid polar curve 121a is through near the first half center of pixel electrode 190.

Guard electrode 88 is extended along data line 171, and complete cover data line 171.Guard electrode 88 is supplied to common-battery and presses, and its contact hole by passivation layer 180 and gate insulator 140 is supplied to, and perhaps can be transferred to the short dot (not shown) of common electrode panel 200 and is supplied to from common-battery being pressed from tft array panel 100.At this moment, preferably, minimize the distance between guard electrode 88 and the pixel electrode 190, aspect ratio is reduced.

Guard electrode 88 can stop between data line 171 and the pixel electrode 190, and the electromagnetic interference (EMI) between data line 171 and the common electrode 270, the signal delay of the data voltage that carries with the voltage distortion that reduces pixel electrode 190 and by data line 171.

In addition, because pixel electrode 190 need separate to prevent short circuit therebetween with guard electrode 88, therefore, the distance between pixel electrode 190 and the data line 171 increases, thereby reduces the stray capacitance between them.And the permittivity of LC layer 3 is higher than the permittivity of passivation layer 180, and the data line 171 of the stray capacitance between data line 171 and the guard electrode 88 when not having guard electrode 88 compared with the stray capacitance between the common electrode 270 and reduced.

In addition, pixel electrode 190 is with guard electrode 88 because by forming with one deck, so the spacing between them can keep equably, and therefore, the stray capacitance between them also remains unchanged.

Contact auxiliary member 81a, 81b, 82 are connected with end 129a, the 129b of gate line 121a, 121b and the end 179 of data line 171 respectively by contact hole 181a, 181b, 182.Cementability between contact auxiliary member 81a, 81b, 82 protection end 129a, 129b and raising end 129a, 129b and end 179 and the external device (ED).

When gate drivers or data driver are integrated on the panel assembly 300, gate line 121a, 121b or data line 171 extends being directly connected to driver, and contact auxiliary member 81a, 81b, 82 can be used to connect gate line 121a, 121b or data line 171 to driver.

Below, describe common electrode panel 200 in detail with reference to Figure 20-24.

Form the light-blocking member 220 that is called black battle array of anti-stopping leak light on the dielectric base of making by clear glass or plastics etc. 210.Light-blocking member 220 almost identical a plurality of peristomes when having in the face of pixel electrode 190 with pixel electrode 190 shapes.Therewith differently, light-blocking member 220 comprises a plurality of in the face of a plurality of line parts of the data line 171 on the tft array panel 100 and a plurality of wide portion that faces TFTQa, Qb on the tft array panel 100.Yet light-blocking member 220 leaks and also can have multiple shape in order to be breaking near pixel electrode 190 and TFTQa, the Qb light.

Also form a plurality of color filters 230 in the substrate 210.Their major parts are positioned at by light-blocking member 230 region surrounded.Color filter 230 basically along pixel electrode 190 at longitudinal extension.Color filter 230 shows a kind of in the primary colours such as redness, green, blueness.

On color filter 230 and light-blocking member 230, be formed with coating (overcoat) 250.This coating 250 is preferably made by (organic) insulator, and it can prevent that color filter 230 from exposing and tabular surface is provided.Coating 250 also can be omitted.

On coating 250, form common electrode 270.Common electrode 270 preferably by make and have to organize cut 271,273,275 such as the transparent conductor of ITO, IZO etc. more.

One group of cut 271,273,275 comprises top cut 271, central cut 275 simultaneously, reaches undercut portion 273 in the face of pixel electrode 190.Each cut 271,273,275 places between the adjacent cut 94,95 of pixel electrode 190, or between the hypotenuse of cut 94 and pixel electrode 190.Each cut 271,273,275 comprises and the top oblique line portion 91 in gap or at least one oblique line portion of bottom oblique line portion 93 substantially parallel extensions.Cut 271,273,275 is with respect to the anti-phase basically symmetry of storage electrode line 131.

Top and undercut portion 271,273 comprise 271o of oblique line portion or 273o respectively, transverse part 271t or 273t, and longitudinal part 271l or 273l.Extend from the limit, left side of pixel electrode 190 from 271o of oblique line portion or 273o, and approximate bottom or the top edge that arrives pixel electrode 190.The edge along pixel electrode 190 extends from each end of 271o of oblique line portion or 273o for each transverse part 271t or 273t and longitudinal part 271l or 273l, and overlapping with the limit of pixel electrode 190, thereby forms the obtuse angle with respect to the 271o of oblique line portion, 273o.

Central authorities' cut 275 comprises a pair of oblique line 275o1 of portion, 275o2, and a pair of termination longitudinal part 275l1,275l2.The 275o1 of oblique line portion, 275o2 are from the approximate right edge that arrives pixel electrode 190 of extending of limit, the left side central authorities of pixel electrode 190.Stop longitudinal part 275l1,275l2 and extend along the right edge of pixel electrode 190 from the end of the 275o1 of each oblique line portion, 275o2, and the right edge of overlaid pixel electrode 190, make the relative oblique line 275o1 of portion, 275o2 in obtuse angle.

The quantity of cut 271,273,275 depends on design factor, and light-blocking member 220 is overlapping with cut 271,273,275, passes through the light that cut 271,273,275 is leaked with blocking.

It can be vertical oriented layer 11,21 that the medial surface of panel 100,200 is coated with.

Preferably, the lateral surface of panel 100,200 is provided with polarizer 12,22, thereby its polarizing axis intersects, and one of them polarizing axis is parallel to gate line 121.When LCD was reflection type LCD, one of them polarizer can omit.

LCD also comprises the retardation films (not shown) that is used to compensate 3 delay of LC layer.LCD also can comprise the backlight (not shown), by polarizer 12,22, and retardation films, and panel 100.200 to LC layer 3 supply light.

Preferably, LC layer 3 has negative dielectric anisotropy, and carries out vertical orientation, is not having to be substantially perpendicular to panel 100,200 under the situation of electric field thereby the LC molecule wherein in the LC layer 3 is directed its longitudinal axis.Therefore, incident light can not be by the polarizer system 12,22 of intersecting.

To common electrode 270 apply common-battery press, when pixel electrode 190 applies data voltage, form almost electric field, and pixel electrode 190 and common electrode 270 are referred to as " produce electrode " perpendicular to panel 100,200 surfaces.LC molecules in response electric field and change its orientation, thus its major axis is perpendicular to direction of an electric field.

Produce the cut 94,95,271,273,275 of electrode 190,270 and the limit of pixel electrode 190 makes the electric field distortion, thereby have the horizontal cell on the limit of the limit of cut of being substantially perpendicular to 94,95,271,273,275 and pixel electrode 190.

Therefore, electric field points favours the direction of the Surface Vertical of counter plate 100,200.Liquid crystal molecule trends towards redirecting, thereby its major axis is perpendicular to direction of an electric field.Because near the electric field on cut 94,95,271,273,275 and pixel electrode 190 limits and be not parallel to the long axis direction of LC molecule, and at an angle, the LC molecule rotates along long axis direction, and has the shortest displacement in the plane that the major axis of LC molecule and electric field limit.

With reference to Figure 21, one group of cut 94,95,271,273,275 is divided into a plurality of subregions with pixel electrode 190, and all subregion has two main limits that form the oblique angle with the main limit of pixel electrode 190.The polarizing axis shape of the main limit of all subregion and polarizer 12,22 is at 45, with the maximization optical efficiency.

Because the most of LC molecules on all subregion tilt perpendicular to main limit, therefore, the azimuthal distribution of vergence direction is positioned at four direction, thereby has increased the benchmark visual angle of LCD.

The shape of cut 94,95,271,273,275 and arrange and to change.

At least one cut 94,95,271,273,275 can be replaced by projection (not shown) or depression (not shown).Projection is preferably made by the organic or inorganic material, and place on electric field generating electrode 190 or 270 or under.

Describe LCD according to another embodiment of the present invention in detail referring now to Figure 25 and Figure 26.

Figure 25 is the block diagram of LCD according to another embodiment of the present invention; Figure 26 is the equivalent circuit diagram of the pixel of LCD according to another embodiment of the present invention.

As shown in figure 25, the LCD according to this embodiment of the invention comprises LC panel assembly 300, gate drivers 490, data driver 590, grayscale voltage generator 800, reaches signal controller 600.

Panel assembly 300 comprises a plurality of gate lines G 1-Gn, a plurality of data line D1-D2m, reaches a plurality of pixel PX.The quantity of gate lines G 1-Gn be before half of embodiment, and the quantity of data line D1-D2m be before the twice of embodiment.Pair of data lines D1-D2m is arranged on the left and right sides of pixel column.

As Figure 25 and shown in Figure 26, each pixel PX comprises a pair of sub-pixel PXa, PXb.A sub-pixel PXa (hereinafter to be referred as first sub-pixel) comprises the on-off element Qa that is connected on gate line and the right side data line, is connected the LC capacitor Clca on the on-off element Qa, and is connected the holding capacitor Csta on the on-off element Qa.Another sub-pixel PXb (hereinafter to be referred as second sub-pixel) comprises the on-off element Qb that is connected on gate line and the left data line, is connected the LC capacitor Clcb on the on-off element Qb, and is connected the holding capacitor Cstb on the on-off element Qb.

Describe the example of Figure 25 and LCD shown in Figure 26 in detail below with reference to Figure 27,28,29,30A, 30B.

Figure 27 is the schematic layout pattern of the lower panel (tft array panel) according to the embodiment of the invention; Figure 28 is the schematic layout pattern of the top panel (common electrode panel) according to the embodiment of the invention; Figure 29 is the schematic layout pattern that comprises the LC panel assembly of tft array panel shown in Figure 27 and common electrode panel shown in Figure 28; Figure 30 A and 30B are LC panel assembly shown in Figure 29 sectional views along line XXXA-XXXA and XXXB-XXXB intercepting.

With reference to Figure 27-30B, comprise according to the LC panel assembly of this embodiment of the invention: tft array panel 100, the common electrode panel of facing with tft array panel 100 200, and be folded in liquid crystal layer 3 between panel 100 and 200.

At first, with reference to Figure 25, Figure 30 A, and Figure 30 B describe tft array panel 100 in detail.

On the dielectric base of making such as transparent glass etc. 110, be formed with many to gate line 121 and a plurality of storage electrode line 131.Each gate line 121 comprises a plurality of gate electrodes 124 and wide end 129.Each storage electrode line 131 comprises the rectangle storage electrode 133 of expansion up and down.Each storage electrode line 131 is between two adjacent gate lines 121, and is and equidistant with gate line 121.

On gate line 121 and storage electrode line 131, form gate insulator 140.

On gate insulator 140, form a plurality of semiconductor island 154a, 154b.Each semiconductor island 154a, 154b are arranged on the gate electrode 124.

On semiconductor island 154a, 154b, form a plurality of Ohmic contact bands and island 163a, 163b, 165a, 165b. Ohmic contact part 163a, 163b, 165a, 165b are positioned on semiconductor island 154a, the 154b in pairs, and the Ohmic contact part faces with each other with respect to grid 124.

On Ohmic contact part 163a, 163b, 165a, 165b and gate insulator 140, form many to data line 171a, 171b and a plurality of drain electrode 175a, 175b.

Each data line 171a, 171b comprise source electrode 173a, the 173b of U type and wide end 179a, 179b.Each drain electrode 175a, 175b comprise wide end and narrow end, and wherein wide end and storage electrode 133 are overlapping.The limit of the wide end of drain electrode 175a, 175b is arranged essentially parallel to the limit of storage electrode 133.

On the exposed portions serve of data line 171a, 171b and drain electrode 175a, 175b and semiconductor island 154a, 154b, form passivation layer 180.

On passivation layer 180, have a plurality of a plurality of contact hole 185a, 185b, 182a, 182b that expose end 179a, the 179b of drain electrode 175a, 175b and data line 171a, 171b respectively, have a plurality of contact holes 181 of the end 129 of exposing gate line 121 on passivation layer 180 and the gate insulator 140.

Form a plurality of pixel electrodes 190 that comprise first and second pixel electrode 190a, 190b on passivation layer 180, guard electrode 88 reaches a plurality of contact auxiliary members 81,82a, 82b.

Preferably, the area of the second pixel electrode 190b is greater than the area of the first pixel electrode 190a, and the twice of the area of the first pixel electrode 190a preferably.Suffer LC molecule among the sub-pixel PXb of low data voltage to have relatively orientation near its initial orientation, thereby low-voltage LC molecule is less relatively to the influence of the distortion of side visibility, the increase of pixel electrode 190b has improved side visibility.Particularly, when the area ratio was about 2: 1, side visibility can improve widely.

A pair of first and second pixel electrode 190a, 190b are located substantially on by in data line 171a, 171b and gate line 121 region surrounded, the major part of the outer boundary of first and second pixel electrode 190a, 190b is parallel with gate line 121 or data line 171a, 171b, thereby forms rectangle.First and second pixel electrode 190a, 190b are separated from one another.The first pixel electrode 190a comprises two parts of the upper and lower sides that is separately positioned on the second pixel electrode 190b, and connects by vertical web member each other.The second pixel electrode 190b is arranged between two parts of the first pixel electrode 190a.

Four corners of each pixel electrode 190 are notched, and the relative gate line 121 of the hypotenuse that is notched of pixel electrode 190 forms about miter angle.

Pixel electrode 190 has central cut 91,92, and the 93a of undercut portion, 94a, 95a reach top cut 93b, 94b, 95b, and cut 91,92,93a, 93b, 94a, 94b, 95a, 95b are divided into a plurality of zones.Cut 91,92,93a, 93b, 94a, 94b, 95a, 95b are with respect to storage electrode line 131 anti-phase symmetries.First and second pixel electrode 190a, 190b are separated from one another by the incision web member 99 of cut 93a, 93b and connection cut 93a, 93b.

Bottom and top cut 93a, 93b, 94a, 94b, 95a, 95b are from the limit, left side of pixel electrode 190, the angle of turning left, lower side, or the approximate right edge that tilts to extend to pixel electrode 190 of upper side edge.93a-95a of undercut portion and top cut 93b-95b are separately positioned on two equally divided positions up and down of pixel electrode 190, and it can be separated by storage electrode line 131.Bottom and top cut 93a-95b and gate line 121 forms miter angles, and their extensions that is perpendicular to one another.

Each central cut 91,92 is included in the central part of horizontal expansion, and a pair of cut 93a-95a and the last cut 93b-95b oblique line portion of being arranged essentially parallel to down.Central authorities' cut 92 is connected to cuts on the web member 99.

Therefore, the following demifacet of pixel electrode 190 is divided into six zones by following cut 91-95a, and the upper half plane of pixel electrode 190 is divided into six zones by last cut 91-95b.The quantity of separating or the quantity of cut depend on design factor, for example, and the ratio on the widthwise edge of the size of pixel electrode 190, pixel electrode 190 and vertical limit, the kind of liquid crystal layer 3 or characteristic etc.

Pixel electrode 190 and adjacent gate lines 121, or adjacent data line 171a, 171b are overlapping, to improve the aperture ratio.

Contact auxiliary member 81,82a, 82b are connected on end 179a, the 179b of the end 129 of gate line 121 and data line 171a, 171b by contact hole 181,182a, 182b.

Guard electrode comprises a plurality of transverse parts that extend along gate line 121, and the longitudinal part that extends along data line 171a, 171b.The complete cover data line of longitudinal part 171a, 171b, and transverse part is narrow than gate line 121, to expose the edge, upper and lower of gate line 121.The transverse part of two adjacent complete covered protection electrodes 88 of data line 171a, 171b.Yet, also can change by the given covering of guard electrode.

Below with reference to Figure 28 and Figure 30 B explanation common electrode panel 200.

On the dielectric base of making such as clear glass or plastics etc. 210, form light-blocking member 220.Light-blocking member 200 comprises a plurality of line parts in the face of data line 171 that are positioned on the tft array panel 100, and is positioned at the wide portion in the face of TFT Qa, Qb on the tft array panel 100.Shape and pixel electrode 190 a plurality of peristomes much at one when therewith differently, light-blocking member 220 has in the face of pixel electrode 190.

In substrate 210, also form a plurality of color filters 230, form coating 250 on color filter 230 and the light-blocking member 220.

Form common electrode 270 on the coating 250, common electrode 270 has many group cut 71-76b.

One group of cut 71-76b faces pixel electrode 190, and comprises central cut 71-73, and the 74a of undercut portion, 75a, 76a reach top cut 74b, 75b, 76b.Each cut 71-76b places between the cut 91-95b of adjacent pixel electrodes 190 or between the hypotenuse of the 95a of edge slit portion, 95b and pixel electrode 190.And each cut 71-76b comprises the 93a-95a of undercut portion that is parallel to pixel electrode 190 or at least one oblique line portion of top cut 93b-95b.

Bottom and top cut 74a-76b comprise oblique line portion respectively, a pair of horizontal and vertical portion, or a pair of longitudinal part.Oblique line portion is from the approximate the right that extends to pixel electrode 190 in the left side, left comer, bottom or the top of pixel electrode 190.Transverse part and longitudinal part extend along the limit of pixel electrode 190 from each end of oblique line portion, and overlapping with the limit of pixel electrode 190, form the obtuse angle with oblique line portion.

Each central cut 71-73 comprises central transverse part, a pair of oblique line portion, and a pair of terminal longitudinal part.Central authorities' transverse part extends along storage electrode line 131 from the center or the right hand edge of pixel electrode 190.Oblique line portion is similar to the left side that extends to pixel electrode from the end of central transverse part, and is the oblique angle with respect to central transverse part.Extend on the left side of terminal longitudinal part from each oblique line portion along pixel electrode 190, overlapping with the left side of plain electrode 190, and each oblique line portion is in obtuse angle relatively.

The quantity of cut 71-76b can be depending on design factor and changes, and light-blocking member 220 can be overlapping with cut 71-76b, to stop the light that leaks by cut 71-76b.

Simultaneously, owing to do not have electric field between common electrode 270 and guard electrode 88, the LC molecule of guard electrode 88 keeps its initial orientation, and therefore stops the light that incides on it.Therefore, guard electrode can be used as light-blocking member.

The shape of cut 71-76b and 91-95b and arrange and to change.

At least one cut 91-95b, 71-76b can be by projection (not shown) or depression (not shown) and replacing.Projection is preferably made by the organic or inorganic material, and be provided with generation electrode 191 on the scene or 270 on or under.

Be coated with oriented layer 11,21 respectively at panel 100,200 medial surfaces, this oriented layer can be similar (homeotropic) or even (homogeneous).

Lateral surface at panel 100,200 is provided with polarizer 12,22, thereby the polarizing axis of two polarizers intersects, and one of them polarizing axis is parallel to gate line 121.When LCD is reflection type LCD, can omit in two polarizers 12,22.

Preferably, LC layer 3 has negative dielectric anisotropy, and it carries out vertical orientation, thereby the LC molecule in the LC layer 3 is directed, so that its longitudinal axis is substantially perpendicular to panel 100 and 200 under the situation of no electric field.

By this way, comprise TFT Qa and the Qb that is connected on two pixel electrode 190a, the 190b that form single pixel electrode 190, and be connected in pair of data lines 171a and 171b on TFT Qa, the Qb respectively according to the tft array panel of this embodiment.Therefore, two sub-pixel Pxa receive different data-signals with PXb.

Below with reference to Figure 31 to Figure 32 B detailed description LCD panel assembly according to other embodiments of the present invention.

Figure 31 is the schematic layout pattern of tft array panel according to another embodiment of the present invention; Figure 32 A is the sectional view that tft array panel shown in Figure 31 intercepts along line XXXIIA-XXXIIA; Figure 32 B is the sectional view that tft array panel shown in Figure 31 intercepts along line XXXIIB-XXXIIB.

With reference to Figure 31 to Figure 32, identical with shown in Figure 29-30B basically according to the hierarchy of the tft array panel 100 of present embodiment.

Also promptly, formation comprises a plurality of gate lines 121 of gate electrode 124 and end 129 in substrate 110, and a plurality of storage electrode lines 131 that comprise storage electrode 133.On gate line 121 and storage electrode line 131, form gate insulator 140 successively, comprise a plurality of semiconductor tape 151a, the 151b of projection 154a and 154b, and a plurality of Ohmic contact bands 161 that comprise projection 163a and 163b and Ohmic contact island 165a and 165b.On Ohmic contact part 161a, 161b, 165a, 165b, form a plurality of data line 171a, the 171b that comprises source electrode 173a, 173b and end 179a, 179b, and a plurality of drain electrode 175a and 175b.At data line 171a, 171b, individual drain electrode 175a and 175b, gate insulator 140, and form passivation layer 180 on the exposed parts of semiconductor tape 151a, 151b.On passivation layer 180 and gate insulator 140, form a plurality of contact holes 181,182a, 182b, 185a, 185b.On passivation layer 180, form and comprise pixel electrode 190a and 190b and a plurality of pixel electrodes 190 with cut 91-95b, guard electrode 88, and a plurality of contact auxiliary member 81,82a, 82b, and apply oriented layer 11 thereon.

Be different from the TFT shown in Figure 29-30B, semiconductor tape 151a, 151b almost have and data line 171a, 171b, drain electrode 175a, 175b, and the Ohmic contact part 161a of lower floor, the flat shape that 161b, 165a are identical with 165b.Yet semiconductor 151a and 151b comprise some exposed parts, and it is not covered by data line 171a, 171b and drain electrode 175a, 175b, for example, and the part between source electrode 173a, 173b and drain electrode 175a, 175b.

Use a lithography step to form data line 171a, 171b simultaneously, drain electrode 175a, 175b, semiconductor 151a and 151b, and Ohmic contact part 161a, 161b, 165a and 165b according to the manufacture method of the tft array panel of this embodiment.

The photoresist mask pattern that is used for photo-mask process has the thickness that depends on the position, and especially, it has thicker part and thin part.Thicker part is positioned at the wiring zone that is occupied by data line 171a, 171b and drain electrode 175a, 175b, and thin part is positioned at the passage area of TFT.

The thickness that depends on the position of photoresist can obtain by several technologies, for example, provides translucent area on film masks, and transparent region and resistance light zone.Translucent area has the cut pattern, and the grid pattern has the film of intermediate transmission rate or interior thickness.When adopting the cut pattern, preferably, the width of cut or the distance between the cut are less than the resolution of the exposer that is used for photoetching.Another example is to use the photoresist that can reflux.At length, in case but use the rotine exposure mask that only has transparent region and zone of opacity to form the photoresist pattern of making by reflow materials, it can flow to the zone that does not have photoresist by reflow process, thereby forms thin part.

Thus, can simplify manufacturing process by omitting lithography step.

In this LCD, signal controller 600 outputs are used for the view data DAT of two sub-pixel PXa, PXb of pixel column, and data driver 590 provides view data to two sub-pixel Pxa, PXb simultaneously by pair of data lines.

Therefore, the action cycle of gate drivers 490 and data driver 590 is 1 horizontal cycle.

Describe anti-phase according to the LCD of the embodiment of the invention in detail below with reference to Figure 33 and Figure 25.

Figure 33 shows according to the row of the embodiment of the invention polarity of the pixel electrode in anti-phase.

Among Figure 33, data driver 590 is listed as anti-phase, thereby the data voltage that is applied to data line has identical polarity in a frame, have opposite polarity and be applied to two data voltages on the adjacent data line.

Therefore, the first and second pixel electrode 190a of pixel electrode 190 are opposite with the polarity of 190b, and the first pixel electrode 190a of pixel electrode 190 has identical polarity, and the second pixel electrode 190b of pixel electrode 190 also has identical polarity.For example, pixel electrode 190a has positive polarity (+) in a frame, and pixel electrode 190b has negative polarity (-) in a frame.

Thus, anti-phase although data driver 590 is listed as, because pixel electrode 190 has the polarity of positive and negative, therefore there is not the defective of vertical striped.In addition, represent the pixel of same color to have identical polarization state, therefore reduced the image quality that causes owing to the polarity difference between the same color pixel and descended.In addition, in the data line polarity of data voltage by frame reverse, therefore, with by the row reverse polarity situation compare, improved the response time of liquid crystal and the signal delay in the data line.

By this way, can accurately control the voltage of two sub-pixels to improve visuality, aperture ratio and transmissivity.

The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (62)

1. display device comprises:

Pixel comprises first sub-pixel and second sub-pixel;

First signal wire is connected to described first sub-pixel and transmits first signal;

The secondary signal line is connected to described second sub-pixel and transmits secondary signal;

The 3rd signal wire intersects with described first and second signal wires, and is connected in described first and second sub-pixels at least one, and transmits the 3rd signal; And

The 4th signal wire intersects with described first and second signal wires, and transmits the 4th signal,

Wherein, described first sub-pixel is supplied to the data voltage with different sizes with described second sub-pixel, and

The data voltage that is fed into described first and second sub-pixels results from single image information.

2. display device according to claim 1, wherein,

Described first sub-pixel comprises and is connected to first on-off element on described first signal wire and is connected to first liquid crystal capacitor on described first on-off element, and

Described second sub-pixel comprises and is connected to the second switch element on the described secondary signal line and is connected to second liquid crystal capacitor on the described second switch element.

3. display device according to claim 2, wherein,

Described first liquid crystal capacitor comprises first pixel electrode that is connected on described first on-off element, and

Described second liquid crystal capacitor comprises second pixel electrode that is connected on the described second switch element.

4. display device according to claim 3, wherein, the described first and second pixel electrode each intervals make the gap that is the oblique angle with described first to the 4th signal wire.

5. display device according to claim 3, wherein, at least one in described first and second sub-pixels has makes the cut that is the oblique angle with described first to the 4th signal wire.

6. display device according to claim 3, wherein, described first and second sub-pixels also comprise the common electrode with cut, described cut makes and is the oblique angle with described first to the 4th signal wire.

7. display device according to claim 2, wherein, described first on-off element is connected to the described first and the 3rd signal wire, and described second switch element is connected to the described second and the 3rd signal wire.

8. display device according to claim 7, wherein, described first on-off element is connected according to described first signal and is transmitted described the 3rd signal, and described second switch element is connected according to described secondary signal and transmit described the 3rd signal.

9. display device according to claim 7, wherein, described first on-off element is connected according to described the 3rd signal and is transmitted described first signal, and described second switch element is connected according to described the 3rd signal and transmit described secondary signal.

10. display device according to claim 2, wherein, described first sub-pixel is connected to the described first and the 3rd signal wire, and described second sub-pixel is connected to the described second and the 4th signal wire.

11. display device according to claim 2, wherein, described first sub-pixel also comprises first holding capacitor that is connected on described first on-off element, and described second sub-pixel also comprises second holding capacitor that is connected on the described second switch element.

12. display device according to claim 1, wherein, generation has first and second gray scale voltage group that differ from one another, and described first pixel electrode is supplied to the voltage that is selected from described first gray scale voltage group, and second pixel electrode is supplied to the voltage that is selected from second gray scale voltage group.

13. display device according to claim 1, wherein, described image information is processed producing first and second picture signals, and described first and second pixel electrodes are supplied to corresponding to the voltage in the single gray scale voltage group of being selected from of described first and second picture signals.

14. display device according to claim 1, wherein, the electric capacity ground coupling each other of described first sub-pixel and described second sub-pixel.

15. a LCD comprises:

Pixel comprises first sub-pixel and second sub-pixel;

Gate line is connected to described first and second sub-pixels and transmits signal;

First data line intersects with described gate line, and it is connected to described first sub-pixel, and transmits first data voltage; And

Second data line intersects with described gate line, and it is connected to described second sub-pixel, and transmits described second data voltage.

16. LCD according to claim 15, wherein, described first data voltage is different from described second data voltage, and described first and second data voltages result from single image information.

17. LCD according to claim 16, wherein, the polarity of described first data voltage is opposite with the polarity of described second data voltage.

18. LCD according to claim 17, wherein, it is constant that the polarity of described first data voltage keeps in the given time.

19. a display device comprises:

A plurality of pixels are arranged as matrix, and each described pixel comprises first sub-pixel and second sub-pixel;

A plurality of first grid polar curves are connected to described first sub-pixel, and the energising of transmission first grid is pressed;

A plurality of second grid lines are connected to described second sub-pixel, and the energising of transmission second grid is pressed;

A plurality of data lines intersect with described first and second gate lines, are connected to described first and second sub-pixels, and the transmission data voltage;

Grey scale signal produces circuit, produces the first grey scale signal group and the second grey scale signal group;

Select circuit, alternate selection and output first and second sets of signals;

Data driver produces data voltage corresponding to view data based on the described first and second grey scale signal groups, and described data voltage is supplied to described data line; And

Gate drivers is pressed described first and second grids energising in turn and is supplied to described first and second gate lines.

20. display device according to claim 19, wherein, described grey scale signal comprises analog gray voltages.

21. display device according to claim 20, wherein, described selection circuit comprises analog switch.

22. display device according to claim 20, wherein, described selection circuit comprises the simulation Port Multiplier.

23. display device according to claim 20, wherein, described selection circuit is integrated into described data driver.

24. display device according to claim 20, wherein, described grey scale signal produces circuit and comprises that a plurality of aanalogvoltages produce circuit, and each described aanalogvoltage produces circuit and comprises a succession of resistor.

25. display device according to claim 19, wherein, described grey scale signal comprises the digital gray scale data.

26. display device according to claim 25 also comprises the digital simulation electric pressure converter, the digital gray scale data in its described grey scale signal group that will choose by described selection circuit are changed, to produce a plurality of grayscale voltages.

27. display device according to claim 26, wherein, described selection circuit comprises a plurality of Port Multipliers that are connected on the described grey scale signal generation circuit.

28. display device according to claim 19, wherein, the application that application that described first grid energising is pressed and the energising of described second grid are pressed overlaps each other on part at least.

29. display device according to claim 28, wherein, the duration that described first grid energising is pressed equals the duration that described second grid energising is pressed.

30. display device according to claim 28, wherein, the duration that the duration that described first grid energising is pressed presses less than described second grid energising.

31. a LCD comprises:

A plurality of pixels are arranged as matrix, and each described pixel comprises first sub-pixel and second sub-pixel;

A plurality of first grid polar curves are connected to described first sub-pixel, and the energising of transmission first grid is pressed;

A plurality of second grid lines are connected to described second sub-pixel, and the energising of transmission second grid is pressed;

A plurality of data lines intersect with described first and second gate lines, are connected to described first and second sub-pixels, and the transmission data voltage;

Reference voltage generating circuit produces the reference voltage of a plurality of big or small periodically-varieds;

Grayscale voltage produces circuit, produces a plurality of grayscale voltages based on described reference voltage;

Data driver from the data voltage of described gray-scale voltage selection corresponding to view data, and is applied to described data line with described data voltage; And gate drivers, described first and second grids energising is pressed be applied to described first and second gate lines in turn.

32. a LCD comprises:

First and second gate lines extend parallel to each other basically and are isolated from each other;

Data line intersects with described first and second gate lines;

The first film transistor is connected to described first grid polar curve and described second data line;

Second thin film transistor (TFT) is connected to described second grid line and described second data line;

First show electrode is connected to described the first film transistor; And

Second show electrode is connected to described second thin film transistor (TFT),

Wherein, described first and second show electrodes have the hypotenuse that faces with each other.

33. a LCD comprises:

First and second gate lines extend and are isolated from each other at first direction;

Data line intersects with described first and second gate lines;

The first film transistor is connected to described first grid polar curve and described second data line;

Second thin film transistor (TFT) is connected to described second grid line and described second data line;

First show electrode is connected to described the first film transistor; And

Second show electrode is connected to described second thin film transistor (TFT),

Wherein, described first show electrode is longer than described second show electrode in second direction, and described first show electrode is arranged in the second direction length of described second show electrode.

34. a LCD comprises:

First and second gate lines extend and are isolated from each other at first direction;

Data line intersects with described first and second gate lines;

The first film transistor is connected to described first grid polar curve and described second data line;

Second thin film transistor (TFT) is connected to described second grid line and described second data line;

First show electrode is connected to described the first film transistor; And

Second show electrode is connected to described second thin film transistor (TFT),

Wherein, each described first and second show electrode is basically with respect to the straight line symmetry of extending at described first direction.

35. LCD according to claim 34 also comprises the 3rd show electrode of facing with described first and second show electrodes.

36. LCD according to claim 35, wherein, at least one in described first and second show electrodes has cut.

37. LCD according to claim 36, wherein, described the 3rd show electrode has cut or projection.

38. LCD according to claim 35, wherein, at least one in described first and second show electrodes and described the 3rd show electrode have the cut that is arranged alternately.

39. according to the described LCD of claim 38, wherein, the gap between described first and second show electrodes and the cut of described the 3rd show electrode are arranged alternately.

40. LCD according to claim 34 also comprises and the overlapping storage electrode line of described first and second show electrodes.

41. according to the described LCD of claim 40, wherein, each described first and second thin film transistor (TFT) all have be connected to described first or the second grid line on gate electrode, be connected to the source electrode on the described data line and be connected to drain electrode on described first or second show electrode.

42. LCD according to claim 34, wherein, the voltage of described first show electrode is different from the voltage of described second show electrode.

43. according to the described LCD of claim 42, wherein, the voltage of described first show electrode that scheduled voltage deducts is less than the voltage of described second show electrode that is deducted by described predetermined voltage.

44. LCD according to claim 34, also comprise with described data line overlapping and be arranged at guard electrode as the described first and second display pixel electrodes.

45. a thin-film transistor display panel comprises:

Gate line is formed at described substrate;

First and second data lines intersect with described gate line insulation and with described gate line;

The first film transistor is connected to described gate line and described first drain electrode and comprises first drain electrode;

Second thin film transistor (TFT) is connected to described gate line and described second drain electrode and comprises second drain electrode;

Passivation layer is formed at described gate line, described first and second data lines and described first and second thin film transistor (TFT)s, and has first contact hole that exposes described first data line and second contact hole that exposes described second data line; And

Pixel electrode comprises by described first contact hole being connected to first pixel electrode on described first drain electrode, and is connected to second pixel electrode on described second drain electrode by described second contact hole.

46. according to the described thin-film transistor display panel of claim 45, also comprise with the insulation of described first and second pixel electrodes and with described gate line and described first and second data lines at least one overlapping guard electrode.

47. according to the described thin-film transistor display panel of claim 46, wherein, described pixel electrode and described guard electrode are arranged on the described passivation layer.

48. according to the described thin-film transistor display panel of claim 46, also comprise storage electrode line, comprise with described first and second drain electrodes overlapping to form the storage electrode of memory capacitance.

49. according to the described thin-film transistor display panel of claim 48, wherein, described guard electrode and described storage electrode are supplied to single voltage.

50. according to the described thin-film transistor display panel of claim 49, wherein, described guard electrode covers described first and second data lines fully.

51. according to the described thin-film transistor display panel of claim 45, wherein, the zone of described first pixel electrode is different from the zone of described second pixel electrode.

52. the driving method of a LCD, described LCD comprises a plurality of pixels, and each described pixel comprises a plurality of sub-pixels, and described method comprises:

Receive input image data;

Described view data is converted at least two data voltages; And

At least two data voltages are applied to described sub-pixel.

53. according to the described method of claim 51, wherein said conversion comprises:

Produce at least two group grayscale voltages; And

From described two group grayscale voltages, select grayscale voltage corresponding to described input image data to produce data voltage at least.

54. according to the described method of claim 51, wherein said conversion comprises:

Described input image data is converted at least two output image datas; And

From described one group of grayscale voltage, select grayscale voltage corresponding to described at least two output image datas to produce data voltage.

55. the driving method of a LCD, described LCD comprise a plurality of pixels that are arranged in matrix, each described pixel comprises first and second sub-pixels, and described method comprises:

First data voltage that will have first polarity is applied to described first sub-pixel; And

Second data voltage that will have with described first opposite polarity second polarity is applied to described second sub-pixel.

56. according to the described method of claim 55, wherein, described first and second data voltages produce from the single image data.

57. according to the described method of claim 56, wherein, described first sub-pixel of neighbor has opposite polarity in the row, and described second sub-pixel of neighbor has opposite polarity in the row.

58. according to the described method of claim 57, wherein, described first sub-pixel of neighbor has identical polarity in the row, and described second sub-pixel of neighbor has identical polarity in the row.

59. according to the described method of claim 58, wherein, each described data voltage is supplied at least two sub-pixels simultaneously.

60. the driving method of a LCD, described LCD comprises a plurality of pixels, and each described pixel comprises first sub-pixel and second sub-pixel, and described method comprises:

Transmit image data;

Export first group of grayscale voltage;

Described view data is converted to first data voltage that is selected from described first group of grayscale voltage;

Described first data voltage is applied to described first sub-pixel;

By using Port Multiplier to substitute first group of grayscale voltage with second group of grayscale voltage, output varies in size in described second group of grayscale voltage of described first group of grayscale voltage;

Described view data is converted to second data voltage that is selected from described second group of grayscale voltage; And

Described second data voltage is applied to described second sub-pixel.

61., also comprise according to the described method of claim 59:

Produce first and second groups of grayscale voltages;

Wherein, the output of first group of grayscale voltage comprises:

Select described first group of grayscale voltage by the use Port Multiplier, and

Wherein, the output of second group of grayscale voltage comprises:

Select described second group of grayscale voltage by using Port Multiplier.

62., also comprise according to the described method of claim 59:

Store first and second groups of digital gray scale data;

Wherein, the output of first group of grayscale voltage comprises:

Select described first group of digital gray scale data by using Port Multiplier; And

Described first group of digital gray scale digital simulation is converted to described first group of grayscale voltage, and

Wherein, the output of second group of grayscale voltage comprises:

Select second group of digital gray scale data by using Port Multiplier; And

Described second group of digital gray scale digital simulation is converted to described second group of grayscale voltage.

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