KR101071259B1 - Display device and driving method thereof - Google Patents

Abstract

A display device according to an aspect of the present invention includes a plurality of pixels arranged in a matrix form, each pixel including first and second subpixels, and a plurality of pixels connected to the first subpixel and transferring a first gate-on voltage. A first gate line of, a plurality of second gate lines connected to the second subpixel and transferring a second gate-on voltage, intersecting the first and second gate lines, and connecting to the first and second subpixels A plurality of data lines for transmitting data voltages, first and second analog voltage generation circuits for generating first and second analog gray voltage voltage sets, and an analog alternately selecting and outputting the first and second gray voltage voltage sets; A multiplexer selects an analog gray voltage corresponding to image data from a set of gray voltages from the analog multiplexer and applies it to the data line as the data voltage. The data driver includes a data driver and a gate driver configured to sequentially apply the first and second gate-on voltages to the first and second gate lines.

Visibility, Pixel Division, Double Gamma, Gray Voltage, Multiplexer, Resistance String, Digital Gamma

Description

Display device and driving method thereof {DISPLAY DEVICE AND DRIVING METHOD THEREOF}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is an equivalent circuit diagram of one subpixel of a liquid crystal display according to an exemplary embodiment of the present invention;

4 is a waveform diagram of various signals used in the liquid crystal display shown in FIGS. 1 to 3;

5 is a graph illustrating a gamma curve of a liquid crystal display according to an exemplary embodiment of the present invention.

6 is a block diagram of a liquid crystal display according to another exemplary embodiment of the present invention.

7 is a block diagram of a gray voltage generator according to an exemplary embodiment of the present invention.

8 is a block diagram of a gray voltage generator according to another exemplary embodiment of the present invention.

FIG. 9 is a waveform diagram of various signals used in the liquid crystal display shown in FIGS. 6 to 8.

10 is a layout view of a lower panel according to an exemplary embodiment of the present invention.

11 is a layout view of an upper panel according to an exemplary embodiment of the present invention.                 

FIG. 12 is a layout view of a liquid crystal panel assembly including the lower panel of FIG. 10 and the upper panel of FIG. 11.

13 and 14 are cross-sectional views of the liquid crystal panel assembly of FIG. 12 taken along lines XIII-XIII 'and XIV-XIV', respectively.

The present invention relates to a display device and a driving method thereof.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which field generating electrodes such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light to display an image.

Among them, the vertical alignment mode liquid crystal display in which the long axis of the liquid crystal molecules are arranged perpendicular to the upper and lower display panels without an electric field is applied, and thus a high contrast ratio and a wide reference viewing angle can be easily realized. Here, the reference viewing angle refers to a viewing angle having a contrast ratio of 1:10 or a luminance inversion limit angle between gray levels.

Means for implementing a wide viewing angle in a vertical alignment mode liquid crystal display include a method of forming a cutout in the field generating electrode and a method of forming a protrusion on the field generating electrode. Since the inclination and the projection can determine the direction in which the liquid crystal molecules are inclined, the reference viewing angle can be widened by using these to disperse the oblique directions of the liquid crystal molecules in various directions.

However, the liquid crystal display of the vertical alignment type has a problem in that the side visibility is inferior to the front visibility. For example, in the case of a patterned vertically aligned (PVA) type liquid crystal display device having an incision, the image becomes brighter toward the side, and in a severe case, the luminance difference between the high grays disappears and the picture may appear clumped.

In order to solve this problem, one pixel is divided into two subpixels, two subpixels are capacitively coupled, and one subpixel is directly applied with voltage, and the other subpixel causes voltage drop due to capacitive coupling. A method of changing the transmittances by changing the voltages of the two subpixels has been proposed.

However, this method does not have a problem in that the transmittances of the two subpixels cannot be accurately adjusted to a desired level, and in particular, since the light transmittance is different according to the color, this cannot be done despite the fact that the voltage combination for each color must be different. In addition, there is a problem in that the opening ratio decreases due to the addition of a conductor for capacitive coupling, and the transmittance decreases due to the voltage drop caused by the capacitive coupling.

The technical problem to be achieved by the present invention is to solve this problem.

A display device according to an aspect of the present invention includes a plurality of pixels arranged in a matrix form, each pixel including first and second subpixels, and a plurality of pixels connected to the first subpixel and transferring a first gate-on voltage. A first gate line of, a plurality of second gate lines connected to the second subpixel and transferring a second gate-on voltage, intersecting the first and second gate lines, and connecting to the first and second subpixels A plurality of data lines for transmitting data voltages, first and second analog voltage generation circuits for generating first and second analog gray voltage voltage sets, and an analog alternately selecting and outputting the first and second gray voltage voltage sets; A multiplexer selects an analog gray voltage corresponding to image data from a set of gray voltages from the analog multiplexer and applies it to the data line as the data voltage. Includes a data driver and a gate driver which applies the first and second gate turn-on voltage to the first and second gate lines.

The first and second analog voltage generation circuits may each include a plurality of resistor strings.

The display device provides the image data to the data driver, controls the gate driver and the data driver, and provides a selection signal to alternately select the set of first and second gray voltages to the analog multiplexer. The control unit may further include.

The analog multiplexer may output the first and second gray voltage voltage sets once while the data driver applies a bundle of data voltages.

According to another aspect of the present invention, a display device includes a plurality of pixels arranged in a matrix form, each pixel including a first subpixel and a second subpixel, and connected to the first subpixel to transfer a first gate-on voltage. A plurality of first gate lines, a plurality of second gate lines connected to the second subpixel and transferring a second gate-on voltage, and intersecting the first and second gate lines, respectively, to the first and second subpixels. A plurality of data lines connected to each other and transferring data voltages, first and second registers storing first and second digital grayscale data sets, and a selection circuit for alternately selecting the first and second digital grayscale data sets, wherein A digital-to-analog converter for generating a plurality of gray voltages by analog-converting each gray data of the selected digital gray data set by the selection circuit; A data driver which selects a gray voltage corresponding to image data from among a plurality of gray voltages, and applies the first and second gate-on voltages to the first and second gate lines in order; And a gate driver.

The selection circuit may include a plurality of multiplexers connected to the first and second registers.

The display device provides the image data to the data driver, controls the gate driver and the data driver, and provides a selection signal to alternately select the first and second grayscale digital grayscale data sets to the multiplexer. The apparatus may further include a signal controller.

The multiplexer may select the first and second gray level voltage sets once and output them to the digital-to-analog converter while the data driver applies a bundle of data voltages.                     

A driving method of a display device according to an aspect of the present invention is a driving method of a liquid crystal display device including a plurality of pixels each including first and second subpixels, the method comprising: transmitting image data and a first gray voltage; Outputting a set, converting the image data into a first data voltage selected from among the gray voltages of the first gray voltage set, applying the first data voltage to the first subpixel, using a multiplexer Substituting the first gray voltage set with a second gray voltage set having a different value from the first gray voltage set, and converting the image data into a second data voltage selected from gray voltages of the second gray voltage set. And applying the second data voltage to the second subpixel.

The driving method may further include generating the first and second gray voltage voltage sets, and the outputting of the first gray voltage voltage sets may include generating the first gray voltage voltage from the first gray voltage voltage set using the multiplexer. Selecting a first gray voltage set, and outputting the second gray voltage set includes selecting the second gray voltage set from the first and second gray voltage sets using the multiplexer. can do.

The driving method may further include storing first and second digital gradation data sets, and outputting the first gradation voltage sets using the multiplexer, wherein the first and second digital gradation data sets are selected from the first and second digital gradation data sets. Selecting a digital gradation data set; and analog converting the first digital gradation data set to generate the first gradation voltage set, and outputting the second gradation voltage set comprises: Selecting the second digital gradation data set from among the first and second digital gradation data sets using the second digital gradation data set, and generating the second gradation voltage set by analog-converting the second digital gradation data set. Can be.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

1 is a block diagram of a liquid crystal display according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. The equivalent circuit diagram of one subpixel of the liquid crystal display device is shown.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a pair or one gate drivers 400a, 400b, and 400 and a data driver connected thereto. 500, a gray voltage generator 800 connected to the data driver 500, and a signal controller 600 for controlling the gray voltage generator 800.

The liquid crystal panel assembly 300 includes a plurality of display signal lines and a plurality of pixels PX connected to the display signal lines and arranged in a substantially matrix form when viewed in an equivalent circuit. In contrast, in the structure shown in FIG. 3, the liquid crystal panel assembly 300 includes a lower and upper panel 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The display signal line is provided in the lower panel 100, and includes a plurality of gate lines G _1a -G _nb transmitting the gate signals (also called “scan signals”) and data lines D ₁ -D transferring the data signals. _m ). The gate lines G _1a -G _nb extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

2 shows an equivalent circuit of a display signal line and a pixel. In addition to the upper and lower gate lines indicated by reference numerals GLa and GLb and the data lines indicated by reference numeral DL, the display signal lines are substantially parallel to the gate lines G ₁ -G _2b . The extended sustain electrode line SL is included.

Each pixel PX includes a pair of subpixels PXa and PXb, and each of the subpixels PXa and PXb is connected to a corresponding gate line GLa and GLb and a data line DL. Qa, Qb and liquid crystal capacitors C _LC a and C _LC b connected thereto, and a storage capacitor C connected to the switching elements Qa and Qb and the storage electrode line SL. _ST a, C _ST b). The storage capacitors C _ST a and C _ST b can be omitted if necessary, and in this case, the storage electrode lines SL are also not necessary.

Referring to FIG. 3, the switching elements Q of each of the subpixels PXa and PXb are formed of a thin film transistor or the like provided on the lower panel 100, and each of the control terminals connected to the gate line GL; A three-terminal device having an input terminal connected to the data line DL and an output terminal connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST .

The liquid crystal capacitor C _LC has two terminals of the subpixel electrode PE of the lower panel 100 and the common electrode CE of the upper panel 200, and the liquid crystal layer 3 between the two electrodes PE and CE. Functions as a dielectric. The subpixel electrode PE is connected to the switching element Q, and the common electrode CE is formed on the entire surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 3, the common electrode CE may be provided in the lower panel 100. In this case, at least one of the two electrodes PE and CE may be formed in a linear or bar shape.

The storage capacitor C _ST , which serves as an auxiliary part of the liquid crystal capacitor C _LC , is formed by overlapping the storage electrode line SL and the pixel electrode PE provided in the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the SL. However, the storage capacitor C _ST may be formed by the subpixel electrode PE overlapping the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel uniquely displays one of the primary colors (spatial division) or each pixel alternately displays three primary colors over time (time division) so that the spatial and temporal combinations of these three primary colors can be achieved. To recognize the desired color. Examples of primary colors include red, green and blue. 3 illustrates an example of spatial division, in which each pixel includes a color filter CF representing one of primary colors in an area of the upper panel 200. Unlike FIG. 3, the color filter CF may be formed above or below the subpixel electrode PE of the lower panel 100.

Referring to FIG. 1, the gate drivers 400a, 400b, and 400 are connected to the gate lines G _1a -G _nb to form a gate signal including a combination of a gate on voltage Von and a gate off voltage Voff from the outside. Is applied to the gate lines G _1a -G _nb .

The gray voltage generator 800 generates one gray voltage set (or reference gray voltage set) related to the transmittance of the pixel. The gray voltage set includes a gray voltage having a positive value and a gray voltage having a negative value with respect to the common voltage Vcom. However, the gray voltage generator 800 may generate and output only a gray reference voltage as a reference for generating the gray voltage without directly generating the gray voltages for all grays.

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 so that one gray level voltage among the gray voltages from the gray voltage generator 800 is used as the data voltage D _1. -D _m ). However, when the gray voltage generator 800 does not provide all the voltages for all grays, but only the gray reference voltages, the data driver 500 divides the gray reference voltages to generate gray voltages for all grays. Select the data voltage among these.

The gate driver 400a or 400b or the data driver 500 may be directly mounted on the liquid crystal panel assembly 300 in the form of a plurality of driving integrated circuit chips, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP). Alternatively, the gate driver 400 or the data driver 500 may be integrated in the liquid crystal panel assembly 300 together with the display signal lines G _1a -G _nb , D ₁ -D _m and the thin film transistor switching element Q. It may be.

The signal controller 600 controls operations of the gate driver 400 and the data driver 500.

Next, the operation of the liquid crystal display shown in FIGS. 1 to 3 will be described in detail with reference to FIGS. 4 and 5.

4 is a waveform diagram of various signals used in the liquid crystal display shown in FIGS. 1 to 3, and FIG. 5 is a graph illustrating a gamma curve of the liquid crystal display according to the exemplary embodiment.

The signal controller 600 is configured to control the input image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical synchronization signal Vsync and a horizontal synchronization signal ( Hsync, main clock MCLK, and data enable signal DE are provided. Based on the input image signal R, G, B and the input control signal, such as converting one input image signal R, G, B of the signal controller 600 into a pair of output image signals DATa, DATb. The image signals R, G, and B are properly processed according to the operating conditions of the liquid crystal panel assembly 300, and the gate control signal CONT1 and the data control signal CONT2 are generated, and then the gate control signal CONT1. Is sent to the gate driver 400 and the data control signal CONT2 and the processed image signals DATa and DATb are sent to the data driver 500. In this case, the image signal is converted through mapping, which is previously determined by an experiment or the like and stored in a lookup table (not shown), or is performed through the operation of the signal controller 600.

The gate control signal CONT1 includes a scan start signal STV indicating the start of scanning and at least one clock signal controlling the output time of the gate-on voltage Von. The gate control signal CONT1 may also include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 is a load signal for applying a corresponding data voltage to the horizontal synchronization start signal STH and the data lines D ₁ -D _m indicating the transfer of data to a group of subpixels PXa and PXb. (TP) and data clock signal HCLK. The data control signal CONT2 may also include an inversion signal RVS that inverts the polarity of the data voltage with respect to the common voltage Vcom (hereinafter referred to as reducing the polarity of the data voltage with respect to the common voltage). have.

In response to the horizontal synchronization start signal STH and the data clock signal HCLK from the signal controller 600, the data driver 500 performs a group of subpixels PXa and PXb, for example, the upper side of the i-th pixel row. The image data d _ia for the subpixel PXa is received. While receiving the image data d _ia , the data driver 500 applies the data voltage for the lower subpixel PXb of the previous pixel row to the data lines D ₁ -D _m . After the reception of the image data d _ia , the data driver 500 performs image data d among the gray voltages from the gray voltage generator 800 according to the pulse of the load signal TP from the signal controller 600. _The image data d _ia is converted into the corresponding data voltage by selecting the gray voltage corresponding to _ia ), and then applied to the data lines D ₁ -D _m .

As described above, when the gray voltage generator 800 provides only the gray reference voltage, the data driver 500 may divide the gray reference voltage to generate the gray voltage by itself.

The gate driver 400 sets the gate-on voltage Von to the gate line G _1a -G _nb , for example, the upper gate line of the i-th pixel row according to the gate control signal CONT1 from the signal controller 600. G _ia is applied to turn on the switching element Qa connected to the gate line G _ia , and accordingly, the data voltage applied to the data lines D ₁ -D _m is turned on through the switching element Qa. It is applied to the subpixel PXa. In FIG. 4, g _ia and g _ib represent gate signals applied to upper and lower gate lines G _ia and G _ib of the i-th pixel _row , respectively.

Meanwhile, the signal controller 600 finishes transmitting the image data d _ia for the upper subpixel PXa of the i-th pixel row, and then stores the image data d for the lower subpixel PXb of the i-th pixel row. _ib ) is transmitted to the data driver 500 together with the new pulse of the horizontal synchronizing signal STH. Then, the pulse is applied to the reload signal TP again so that the data driver 500 again selects a gray voltage corresponding to each image data d _ib among the gray voltages, and uses the corresponding data line D ₁ -D as the data voltage. _m ).

The gate driver 400 applies the gate-on voltage Von to the next gate line G _1a -G _nb , that is, the lower gate line G of the i-th pixel row according to the gate control signal CONT1 from the signal controller 600. _ib ) turns on the switching element Qb connected to the gate line G _ib , and accordingly, the data voltage applied to the data lines D ₁ -D _m is turned on through the switching element Qb. It is applied to the subpixel PXb.

The difference between the data voltage applied to the subpixels PXa and PXb and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor CLC, that is, the pixel voltage. The liquid crystal molecules have different arrangements according to the magnitude of the pixel voltage, and thus the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

As described above, one input image data is converted into a pair of output image data and they give different transmittances to the pair of subpixels PXa and PXb. Accordingly, as shown in FIG. 5, the two subpixels PXa and PXb show different gamma curves Ta and Tb, and the gamma curve of one pixel PX is a curve T obtained by combining them. When determining the two gamma curves Ta and Tb, the composite gamma curve T is close to the reference gamma curve at the front side. For example, the composite gamma curve T at the front side is determined to be most suitable for the liquid crystal display device. Match the reference gamma curve at the front and the composite gamma curve T at the side to be closest to the reference gamma curve at the front. In FIG. 5, GS1 and GSf mean the lowest input grayscale and the highest input grayscale.

The signal controller 600, the data driver 500, and the gate driver (in units of 1/2 horizontal period (or " 1/2 H ") (one period of the horizontal synchronization signal Hsync and the gate clock CPV)). 400 repeats the same operation. In this manner, the gate-on voltage Von is sequentially applied to all the gate lines G ₁ -G _nb during one frame to apply the data voltage to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarities of the data voltages flowing through one data line change according to the characteristics of the inversion signal RVS within one frame (eg, row inversion and dot inversion), or polarities of data voltages flowing through adjacent data lines at the same time. Can be different (eg, column inversion, dot inversion).

Next, a liquid crystal display according to another exemplary embodiment of the present invention will be described in detail with reference to FIGS. 6 to 8 and FIGS. 2 and 3.

6 is a block diagram of a liquid crystal display according to another exemplary embodiment of the present invention, FIG. 7 is a block diagram of a gray voltage generator according to an exemplary embodiment of the present invention, and FIG. 8 is a liquid crystal according to another exemplary embodiment of the present invention. A block diagram of a gray voltage generator of a display device is shown.

The liquid crystal display shown in FIG. 6 is almost the same as the liquid crystal display shown in FIG. That is, the liquid crystal display according to the present exemplary embodiment includes a liquid crystal panel assembly 300, a pair or one gate drivers 400a, 400b, and 400, a data driver 500, and a data driver The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

Unlike the liquid crystal display shown in FIG. 1, the signal controller 600 according to the present exemplary embodiment includes a selection signal for controlling the gray voltage generator 600 in addition to the gate control signal CONT1 and the data control signal CONT2. Create and print SE).

In addition, the gray voltage generator 800 according to the present embodiment generates two analog gray voltage sets separately and alternately outputs two gray voltage sets according to the selection signal SE, or is stored in advance. Two digital gradation data sets are alternately selected according to the selection signal SE, and an analog gradation voltage set is generated and output based on the selected digital gradation data set. In the latter case, two analog gray voltage sets corresponding to two digital gray data sets are generated alternately. Two sets of gray voltages may be independently provided to two subpixels constituting one pixel, and each set of gray voltages includes a positive value and a negative value with respect to the common voltage Vcom. As described above, the gray voltage generator 800 may generate and output only a gray reference voltage as a reference for generating the gray voltage without directly generating the gray voltages for all grays.

The gray voltage generator 800 illustrated in FIG. 7 includes a register unit 810 including a pair of digital registers 811 and 812, and a plurality of multiplexers MUX connected to the digital registers 811 and 812. And a converter 830 including a plurality of DC-AC converters (DACs) connected to the data selector 820 and the multiplexer MUX.

Two digital registers 811 and 812 store different sets of digital gradation data (γ _1a -γ _Xa , γ _1b -γ _Xb ), and two gradation data sets (γ _1a -γ _Xa , γ _1b -γ _Xb ). Correspond to each other in pairs.

Each multiplexer MUX receives a pair of voltages r _1a r _1b , r _2a r _2b , r _Xa r _xb from two digital registers 811 and 812 as input signals. Depending on the output, select one of the two.

Each DC-AC converter DAC converts digital data from the multiplexer MUX into analog voltages r ₁ , r ₂ , and r _X and outputs the converted data.

The gray voltage generator 800 illustrated in FIG. 8 includes a voltage generator 840 including a pair of resistor strings 841 and 842 and an analog multiplexer (AMUX) 850 connected thereto.                     

Each resistor string 841 generates one set of gray voltages consisting of a plurality of gray voltages, and the gray voltages of the two resistor strings 841 are different from each other.

The analog multiplexer 850 selects and outputs a pair of gray voltage sets from the two pairs of gray voltage sets received from the voltage generator 840 according to the selection signal SE.

Next, the operation of the liquid crystal display shown in FIGS. 6 to 8 will be described in detail with reference to FIG. 9.

FIG. 9 is a waveform diagram of various signals used in the liquid crystal display shown in FIGS. 6 to 8.

9, the signal controller 600 according to the present exemplary embodiment operates at a frequency equal to half the frequency of the signal controller 600 illustrated in FIG. 1. Therefore, the period of the horizontal synchronization start signal STH, the load signal TP, and the data clock signal HCLK is twice as long as in the case of FIG. 5. Instead, the gray voltage set supplied to the data driver 500 is periodically changed. This will be described in detail.

The signal controller 600 properly processes the image signals R, G, and B according to the operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate control signal. After generating the CONT1, the data control signal CONT2, the selection signal SE, and the like, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are generated. Is sent to the data driver 500, and the selection signal SE is sent to the gray voltage generator 800. Unlike the liquid crystal display of FIG. 1, the image signal is not converted.

The gate control signal CONT1 includes a scan start signal STV indicating the start of scanning and at least one clock signal controlling the output time of the gate-on voltage Von. The gate control signal CONT1 may also include an output enable signal OE that defines the duration of the gate-on voltage Von. The clock signal may be used as the above-described selection signal SE.

The data control signal CONT2 is a horizontal synchronization start signal STH for transmitting data to a group of pixels PX and a load signal TP for applying a corresponding data voltage to the data lines D ₁ -D _m . And a data clock signal HCLK. The data control signal CONT2 may also include an inversion signal RVS that inverts the polarity of the data voltage with respect to the common voltage Vcom (hereinafter referred to as reducing the polarity of the data voltage with respect to the common voltage). have.

The selection signal SE is a signal for selecting one of two sets of gray voltages generated by the gray voltage generator 800 and has the same period as the horizontal synchronization start signal STH, the load signal TP, and the like. In the meantime, the period of the clock signal among the gate control signals may be twice the horizontal synchronization start signal STH, and in this case, it may be used as the selection signal SE.

In response to the horizontal synchronizing start signal STH pulse from the signal controller 600, the data driver 500 clocks the image data di for a group of pixels PX, for example, the i-th pixel row. Receives according to signal HCLK. While receiving the image data di, the data driver 500 applies the data voltage for the previous pixel row to the data lines D ₁ -D _m . After reception of the image data di, the gray voltage generator 800 outputs one gray (reference) voltage set determined according to the selection signal SE from the signal controller 600, and the data driver 500. In response to the pulse of the load signal TP from the signal controller 600, the grayscale voltage corresponding to each image data di is selected from the grayscale voltages from the grayscale voltage generator 800 to correspond to the image data di. After conversion to a data voltage, it is applied to the corresponding data lines D ₁ -D _m .

As described above, when the gray voltage generator 800 provides only the gray reference voltage, the data driver 500 may divide the gray reference voltage to generate the gray voltage by itself.

The gate driver 400 applies the gate-on voltage Von to the gate line G _1a -G _nb , for example, the upper subpixel of the i-th pixel row according to the gate control signal CONT1 from the signal controller 600. the applying to the gate line (G _ia) connected to the PXa) sikimyeo turning on the switching element (Qa) is connected to a gate line (G _ia), Accordingly, the data voltage applied to the data lines (D ₁ -D _m) turned It is applied to the corresponding subpixel PXa through the switching element Qa.

Subsequently, the signal controller 600 changes the value of the selection signal SE so that the gray voltage generator 800 generates another gray (reference) voltage set and supplies it to the data driver 500. Then, the data driver 500 reselects the gray voltage corresponding to each image data di from among the new gray voltages and applies it to the corresponding data lines D ₁ -D _m as data voltages.

The gate driver 400 applies the gate-on voltage Von to the next gate line G _1a -G _nb according to the gate control signal CONT1 from the signal controller 600, that is, the lower subpixel PXb of the i-th pixel row. ) connected to a gate line (G _ib) is applied to the gate turn-on sikimyeo the line (the switching device (Qb) is connected to the G _ib), Accordingly, the data lines (D ₁ -D _m), the applied data voltage is a turn-on switching on to the It is applied to the corresponding subpixel PXb through the element Qb.

In this case, the operating frequencies of the signal controller 600 and the data driver 500 can be maintained in the same manner as in the conventional liquid crystal display device, which is more effective than that shown in FIG. 5.

In detail, in FIG. 5, since image data for one pixel row needs to be made in two subpixels and transmitted, the image data of one pixel row should be operated at a frequency twice as fast as a conventional liquid crystal display having no subpixels. For example, the period of the horizontal synchronization start signal STH, the load signal TP, the data clock signal HCLK, etc. should be cut in half, thereby processing and transmitting the image data DAT twice as fast. The duration of the on voltage (Von) is also given in half. That is, these frequencies are 120 Hz instead of the usual 60 Hz. The signal transmission from the signal controller 600 to the data driver 500 is mainly performed by a reduced swing differential signaling (RSDS) method, doubling the frequency of a signal transmitted by the RSDS method through one output channel of the signal controller 600. Is very difficult. Therefore, it is preferable to use a method of increasing the number of channels rather than increasing the frequency of each channel. However, this method not only doubles the number of channels of the signal controller 600 but also doubles the number of signal lines between the signal controller 600 and the data driver 500 and the number of input channels of the data driver 500. Can be complicated. Also, since a pair of output image data is generated and output for one input image data, a line memory (not shown) must be additionally used in the signal controller 600.

In the case of the liquid crystal display illustrated in FIGS. 6 to 9, all of these problems may be solved.

An example of the liquid crystal panel assembly will now be described in detail with reference to FIGS. 10 to 14.

FIG. 10 is a layout view of a lower panel according to an exemplary embodiment of the present invention, FIG. 11 is a layout view of an upper panel according to an exemplary embodiment of the present invention, and FIG. 12 includes a lower panel of FIG. 10 and an upper panel of FIG. 11. 13 and 14 are cross-sectional views taken along the lines XIII-XIII 'and XIV-XIV' of the liquid crystal panel assembly of FIG. 12, respectively.

10 to 14, the liquid crystal display 400 according to the present exemplary embodiment includes a lower panel 100, an upper panel 200 facing each other, and a liquid crystal layer 3 interposed therebetween. .

First, the lower panel 100 will be described in detail with reference to FIGS. 10 and 12 to 14.

A plurality of pairs of first and second gate lines 121a and 121b and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 made of transparent glass or the like.

The gate lines 121a and 121b mainly extend in the horizontal direction, are physically and electrically separated from each other, and transmit gate signals. The first and second gate lines 121a and 121b are disposed at an upper side and a lower side, respectively. It includes end portions 129a and 129b that are large in area for connection and are disposed on the left and right sides, respectively. However, these ends 129a and 129b may both be disposed to the left or to the right.

The storage electrode line 131 extends mainly in the horizontal direction and is closer to the first gate line 121a than the second gate line 121b. Each storage electrode line 131 includes a plurality of pairs of first and second storage electrodes 137a and 137b extending up and down. The first storage electrode 137a has a longer length and a width than the second storage electrode 137b. Is narrow. However, the shape and arrangement of the storage electrode lines 131 including the storage electrodes 137a, 137b, and 137 may be modified in various forms.

The gate line 121 and the storage electrode line 131 may be formed of aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, and copper-based metals such as copper (Cu) and copper alloys. Metal, molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys, chromium (Cr), titanium (Ti), tantalum (Ta) is preferably made of. However, the gate line 121 and the storage electrode line 131 may have a multilayer structure including two conductive layers (not shown) having different physical properties. One of the conductive films may be formed of a low resistivity metal such as an aluminum-based metal, a silver-based metal, or a copper-based metal so as to reduce signal delay or voltage drop between the gate line 121 and the storage electrode line 131. Is done. In contrast, the other conductive layer is made of a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, titanium, tantalum and the like. A good example of such a combination is a chromium bottom film and an aluminum top film and an aluminum bottom film and a molybdenum top film. However, the gate line 121 and the storage electrode line 131 may be made of various metals and conductors.

In addition, side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is about 30-80 °.

A gate insulating layer 140 made of silicon nitride (SiN _x ) is formed on the gate lines 121a and 121b and the storage electrode line 131.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon, polycrystalline silicon, or the like are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction, from which a plurality of first and second projections 154a and 154b extend toward the first and second gate electrodes 124a and 124b, respectively. In addition, the linear semiconductor 151 increases in width near a point where the linear semiconductor 151 meets the gate lines 121a and 121b and the storage electrode line 131, thereby covering a large area of the gate lines 121a and 121b.

A plurality of linear and island ohmic contacts 161 and 165a made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed on the semiconductor 151. have. The linear contact member 161 has a plurality of protrusions 163a, and the protrusions 163a and the island contact members 165a are paired and positioned on the protrusions 154a of the semiconductor 151. Although not shown, the protrusion of the linear contact member 161 and the island contact member are paired with each other on the second protrusion 154b of the semiconductor 151.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165a are also inclined with respect to the surface of the substrate 110 and have an inclination angle of 30-80 °.

A plurality of data lines 171 and a plurality of pairs of first and second drain electrodes 175a and 175b are formed on the ohmic contacts 161 and 165a and the gate insulating layer 140, respectively. have.

The data line 171 mainly extends in the vertical direction and crosses the gate line 121 and the storage electrode line 131 and transmits a data voltage. Each data line 171 is connected to a plurality of first and second source electrodes 173a and 173b extending toward the first and second drain electrodes 175a and 175b, respectively, from another layer or an external device. It includes an end portion 179 extending in width.

The first and second drain electrodes 175a and 175b start from the rod-shaped ends positioned over the first and second protrusions 154a and 154b of the semiconductor 151, respectively, and the first and second sustain electrodes 137a and 137b. ) Has wide areas 177a and 177b which overlap with each other. Each of the source electrodes 173a and 173b is bent to surround the rod-shaped ends of the drain electrodes 175a and 175b. The first and second gate electrodes 124a and 124b, the first and second source electrodes 173a and 173b, and the first and second drain electrodes 175a and 175b are first and second protrusions of the semiconductor 151. The first and second thin film transistors TFTs Qa / Qb are formed together with the second and second source electrodes 154a and 154b, and the channels of the thin film transistors Qa and Qb are formed of the first and second source electrodes. 173a / 173b and protrusions 154a / 154b between the drain electrodes 175a / 175b.

The data line 171 and the drain electrodes 175a and 175b are preferably made of a refractory metal such as chromium, molybdenum-based metal, tantalum, and titanium, and include a lower film (not shown) such as a refractory metal and a low resistance thereon. It may have a multilayer structure consisting of a material upper layer (not shown). Examples of the multilayer film structure include a triple film of molybdenum film, aluminum film, and molybdenum film in addition to the above-described double film of chromium lower film and aluminum upper film or aluminum lower film and molybdenum upper film.

The data line 171 and the drain electrodes 175a and 175b are also inclined at an angle of about 30 to 80 degrees, similarly to the gate line 121 and the storage electrode line 131.

The ohmic contacts 161 and 165a exist only between the lower semiconductor 151 and the upper data line 171 and the drain electrodes 175a and 175b and serve to lower the contact resistance. The linear semiconductor 151 has portions exposed between the source electrodes 173a and 173b and the drain electrodes 175a and 175b, and are not covered by the data line 171 and the drain electrodes 175a and 175b. Although the width of the linear semiconductor 151 is smaller than the width of the data line 171, as described above, the width of the linear semiconductor 151 increases in a portion where the linear semiconductor 151 meets the gate lines 121a and 121b and the storage electrode line 131 so as to soften the profile of the surface so that the data line ( To prevent disconnection.

A passivation layer 180 is formed on the data line 171, the drain electrodes 175a and 175b, and the exposed portion of the semiconductor 151. The passivation layer 180 is formed of an inorganic material made of silicon nitride or silicon oxide, an organic material having excellent planarization characteristics, photosensitivity, or a-Si: C: O formed by plasma enhanced chemical vapor deposition (PECVD), It consists of low dielectric constant insulating materials, such as a-Si: O: F. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer in order to protect the exposed portion of the semiconductor 151 while maintaining the excellent characteristics of the organic layer.

The passivation layer 180 includes a plurality of contact holes 182, 185a, and 185b exposing end portions 179 of the data line 171 and the extended portions 177a and 177b of the drain electrodes 175a and 175b, respectively. A plurality of contact holes 181a and 181b exposing end portions 129a and 129b of the gate lines 121a and 121b are formed in the passivation layer 180 and the gate insulating layer 140.                     

On the passivation layer 180, a plurality of pixel electrodes 190 including the first and second subpixel electrodes 190a and 190b, a plurality of shielding electrodes 88, and a plurality of contact assistants, respectively. ) 81a, 81b, 82 are formed. The pixel electrode 190 and the contact auxiliary members 81a, 81b, and 82 are made of a transparent conductor such as ITO or IZO or a reflective conductor such as aluminum.

The first and second subpixel electrodes 190a and 190b are physically and electrically connected to the first and second drain electrodes 175a and 175b through the contact holes 185a and 185b to form the first and second drain electrodes ( Data voltage is applied from 175a / 175b).

The subpixel electrodes 190a and 190b to which the data voltage is applied generate an electric field together with the common electrode 270 to determine the arrangement of liquid crystal molecules of the liquid crystal layer 3 between the two electrodes 190 and 270.

In addition, as described above, each of the subpixel electrodes 190a and 190b and the common electrode 270 form liquid crystal capacitors C _LC a and C _LC b to maintain the applied voltage even after the thin film transistors Qa and Qb are turned off. And the storage capacitors C _ST a and C _ST b connected in parallel with the liquid crystal capacitors C _LC a and C _LC b to enhance the voltage holding capability. The first and second subpixel electrodes 190a and 190b are connected to each other. And overlapping the drain electrodes 175a and 175b and the first and second sustain electrodes 137a and 137b connected thereto.

Each pixel electrode 190 is chamfered at the left corner, and the chamfered hypotenuse forms an angle of about 45 degrees with respect to the gate lines 121a and 121b.                     

The pair of first and second subpixel electrodes 190a and 190b constituting one pixel electrode 190 are engaged with each other with a gap 94 therebetween, and an outer boundary thereof is substantially rectangular. The first subpixel electrode 190a is a rotated equilateral trapezoid, the left side of which is located near the second storage electrode 137b, the right side of the opposite side thereof, and an upper hypotenuse which is approximately 45 ° with the gate lines 121a and 121b. And lower hypotenuse. The second subpixel electrode 190b includes a pair of trapezoids facing the hypotenuse of the first subpixel electrode 190a and a vertical portion facing the left side of the first subpixel electrode 190a. Accordingly, the gap 94 between the first subpixel electrode 190a and the second subpixel electrode 190b has a substantially uniform width and has upper and lower diagonal portions (45 °) that form about 45 ° with the gate lines 121a and 121b. 91, 93 and longitudinal sections 92 having a substantially uniform width.

The first subpixel electrode 190a has a cutout 95 extending along the storage electrode line 131, and is bisected into an upper half and a lower half by the cutout 95. The cutout 95 has an inlet at the right side of the first subpixel electrode 190a, and the inlet of the cutout 95 is formed with the upper diagonal 91 and the lower diagonal 93 of the gap 94, respectively. It has a pair of hypotenuses that are substantially parallel. The gap 94 and the cutout 95 are substantially inversion symmetry with respect to the storage electrode line 131.

In this case, the number of divided portions or the number of cutout portions varies depending on the size of the pixel, the ratio of the length of the horizontal side to the vertical side of the pixel electrode 190, and the type or characteristics of the liquid crystal layer 3. Hereinafter, for convenience of explanation, the gap 94 is also expressed as a cutout.                     

In addition, the first subpixel electrode 190a overlaps the first gate line 121a and the second subpixel electrode 190b overlaps both the first and second gate lines 121a and 121b and the first gate. The line 121a passes near the center of the upper half of the pixel electrode 190.

The shielding electrode 88 extends along the data line 171 and completely covers the data line 171. A common voltage is applied to the shielding electrode 88. The common electrode is connected to the storage electrode line 131 through a contact hole (not shown) of the passivation layer 180 and the gate insulating layer 140, or the common voltage is applied to the thin film transistor array panel. The display device may be connected to a short point (not shown) transferred from the 100 to the common electrode display panel 200. At this time, it is preferable to minimize the distance between the shielding electrode 88 and the pixel electrode 190 so that the aperture ratio decreases to a minimum.

As such, when the shielding electrode 88 to which the common voltage is applied is disposed on the data line 171, the shielding electrode 88 is disposed between the data line 171 and the pixel electrode 190, and the data line 171 and the common electrode ( By blocking the electric field formed between the 270, the voltage distortion of the pixel electrode 190 and the signal delay of the data voltage transmitted by the data line 171 are reduced.

Also, in order to prevent a short circuit between the pixel electrode 190 and the shielding electrode 88, a distance is required between them so that the pixel electrode 190 is further away from the data line 171, thereby reducing the parasitic capacitance therebetween. Furthermore, since the permittivity of the liquid crystal layer 3 is higher than that of the passivation layer 180, the parasitic capacitance between the data line 171 and the shielding electrode 88 is absent when the shielding electrode 88 is absent. It is smaller than the parasitic capacitance between 171 and the common electrode 270.                     

In addition, since the pixel electrode 190 and the shielding electrode 88 are made of the same layer, the distance between them is kept constant and thus the parasitic capacitance between them is constant. Although the parasitic capacitance between the pixel electrode 190 and the data line 171 may still vary depending on the exposure area divided during the split exposure process, the parasitic capacitance between the pixel electrode 190 and the data line 171 is relatively low. The overall parasitic capacity is almost constant. Therefore, stitch defects can be minimized.

The contact auxiliary members 81a, 81b, and 82 may contact the end portions 129a and 129b of the gate lines 121a and 121b and the end portions 179 of the data lines 171 through the contact holes 181a, 181b and 182. Each is connected. The contact auxiliary members 81a, 81b, and 82 complement adhesiveness between the end portions 129a and 129b of the gate lines 121a and 121b and the respective end portions 179 of the data line 171 and the external device, and It protects you.

When the gate drivers 400a and 400b or the data driver 500 illustrated in FIG. 1 are integrated on the assembly 300, the gate lines 121a and 121b or the data line 171 may be extended to be directly connected to them. In this case, the contact auxiliary members 81a, 81b, and 82 may be used to connect the gate lines 121a and 121b or the data lines 171 and the driving units 400a, 400b, and 500, and the like.

On the pixel electrode 190, the contact auxiliary members 81a, 81b, 82, and the passivation layer 180, an alignment layer 11 capable of aligning the liquid crystal layer is coated.

Next, the upper panel 200 will be described with reference to FIGS. 11 to 14.                     

A light blocking member 220 called a black matrix for preventing light leakage is formed on an insulating substrate 210 made of transparent glass or the like. The light blocking member 220 has a plurality of openings facing the pixel electrode 190 and having substantially the same shape as the pixel electrode 190. Alternatively, the light blocking member 220 may include a portion corresponding to the data line 171 and a portion corresponding to the thin film transistor. However, the light blocking member 220 may have various shapes to block light leakage near the pixel electrode 190 and the thin film transistors Qa and Qb.

A plurality of color filters 230 is also formed on the substrate 210. The color filter 230 may be mostly located in an area surrounded by the light blocking member 230, and may extend in the vertical direction along the pixel electrode 190. The color filter 230 may display one of primary colors such as red, green, and blue.

An overcoat 250 is formed on the color filter 230 and the light blocking member 230 to prevent the color filter 230 from being exposed and to provide a flat surface.

The common electrode 270 formed of a transparent conductor such as ITO or IZO is formed on the overcoat 250.

The common electrode 270 has a plurality of cutouts 271, 273, and 275.

One set of cutouts 271, 273, and 275 includes an upper cutout 271, a center cutout 272, and a lower cutout 273 facing the pixel electrode 190. Each of the cutouts 271, 273, and 275 is disposed between adjacent cutouts 94 and 95 of the pixel electrode 190 or between the cutout 94 and the hypotenuse of the pixel electrode 190. Further, each cutout 271, 273, 275 defines at least one diagonal line 271o, 273o, 275o1, 275o2 extending in parallel with the upper diagonal line 91 or the lower diagonal line 93 of the gap 94. It is substantially inverted symmetry with respect to the storage electrode line 131.

Each of the upper and lower incisions 271 and 273 is a pixel from each end of the oblique portions 271o and 273o extending from the left side of the pixel electrode 190 toward the upper or lower side, and the diagonal portions 271o and 273o. It includes a horizontal portion (271t, 273t) and the vertical portion (271 l , 273 l ) extending along the side of the electrode 190 and overlapping the side and forming an obtuse angle with oblique portions (271o, 273o).

The center cutout 275 includes a pair of oblique portions 275o1 and 275o2, and oblique portions 275o1 and 275o2 extending from the center of the left side of the pixel electrode 190 to the right side of the pixel electrode 190 at an angle. Each of the ends of the pixel electrode 190 includes a vertical portion 275 l 1 and 275 l 2 which extends while overlapping the right side and forms an obtuse angle with the oblique portions 275 o 1 and 275 o 2.

The number of cutouts 271, 273, and 275 may vary depending on design factors, and the light blocking member 220 overlaps the cutouts 271, 273, and 275 so that the light leakage near the cutouts 271, 273, and 275 may occur. Can be blocked.

An alignment layer 21 is disposed on the common electrode 270 to align the liquid crystal molecules.

Orthogonal polarizing plates 12 and 22 are provided on the outer surfaces of the display panels 100 and 200. The transmission axes of the two polarizing plates 12 and 22 are orthogonal and one of the transmission axes (or absorption axis) is parallel to the horizontal direction. In the case of a reflective liquid crystal display, one of the two polarizing plates 12 and 22 may be omitted.

The liquid crystal layer 3 has negative dielectric anisotropy and the liquid crystal molecules are aligned such that their major axes are substantially perpendicular to the surfaces of the two display panels 100 and 200 when there is no electric field.

When a common voltage is applied to the common electrode 270 and a data voltage is applied to the pixel electrode 190, an electric field substantially perpendicular to the surfaces of the display panels 100 and 200 is generated. The cutouts 94, 95, 271, 273, 275 of the electrodes 190, 270 distort this electric field to create a horizontal component perpendicular to the sides of the cutouts 94, 95, 271, 273, 275. . Accordingly, the electric field indicates a direction inclined with respect to the direction perpendicular to the surfaces of the display panels 100 and 200. In response to the electric field, the liquid crystal molecules change their long axis to be perpendicular to the direction of the electric field. In this case, the electric field near the sides of the cutouts 94, 95, 271, 273, and 275 and the pixel electrode 190 is a liquid crystal. The liquid crystal molecules rotate in a direction in which the movement distance is short on a plane formed by the long axis direction of the liquid crystal molecules and the electric field because they are formed at an angle without being parallel to the long axis direction of the molecules. Accordingly, one set of cutouts 94, 95, 271, 273, and 275 and the side of the pixel electrode 190 may be arranged in a plurality of different directions in which liquid crystal molecules are inclined to a portion of the liquid crystal layer 3 positioned on the pixel electrode 190. Divide into domains, thereby expanding the reference viewing angle.

At least one cutout 94, 95, 271, 273, 275 may be replaced with a protrusion or depression, and the shape and arrangement of the cutouts 94, 95, 271, 273, 275 may be modified.

 By precisely adjusting the voltages of the two subpixels to the desired level, the visibility is improved, the aperture ratio is increased, and the transmittance is improved.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (11)

delete delete delete delete A plurality of pixels arranged in a matrix and including first and second subpixels, A plurality of first gate lines connected to the first subpixel and transferring a first gate on voltage; A plurality of second gate lines connected to the second subpixel and transferring a second gate on voltage; A plurality of data lines crossing the first and second gate lines and connected to the first and second subpixels and transferring data voltages; First and second registers for storing the first and second digital gradation data sets, A selection circuit for alternately selecting the first and second digital gradation data sets, A digital-to-analog converter for generating a plurality of gray voltages by analog converting each gray data of the digital gray data set selected by the selection circuit; A data driver which selects a gray voltage corresponding to image data from among the plurality of gray voltages from the digital-analog converter and applies it to the data line as the data voltage; and A gate driver configured to sequentially apply the first and second gate-on voltages to the first and second gate lines Display device comprising a. The method of claim 5, And the selection circuit includes a plurality of multiplexers connected to the first and second registers. In claim 6, A signal controller configured to provide the image data to the data driver, control the gate driver and the data driver, and provide a selection signal to the multiplexer to alternately select the first and second digital gradation data sets. Display device. 8. The method of claim 7, And the multiplexer selects the first and second digital gradation data sets once and outputs them to the digital-analog converter while the data driver applies a bundle of data voltages. A driving method of a liquid crystal display device including a plurality of pixels each including a first subpixel and a second subpixel, Transmitting image data, Outputting a first set of gray voltages, Converting the image data into a first data voltage selected from gray voltages of the first gray voltage set; Applying the first data voltage to the first subpixel, Substituting the first gray voltage set with a second gray voltage set having a different value from the first gray voltage set using a multiplexer, and outputting the second gray voltage set; Converting the image data into a second data voltage selected from gray voltages of the second gray voltage set; and Applying the second data voltage to the second subpixel Method of driving a liquid crystal display comprising a. The method of claim 9, The driving method further includes generating the first and second gray voltage sets. The outputting of the first gray voltage set includes selecting the first gray voltage set from among the first and second gray voltage sets using the multiplexer. The outputting of the second gray voltage set includes selecting the second gray voltage set from the first and second gray voltage sets using the multiplexer. Driving method of liquid crystal display device. The method of claim 9, The driving method further includes storing first and second digital gradation data sets, The first gray voltage set output step, Selecting the first digital gradation data set from the first and second digital gradation data sets using the multiplexer, and Analog converting the first digital gray data set to generate the first gray voltage set Including, The second gray voltage set output step, Selecting the second digital gradation data set from the first and second digital gradation data sets using the multiplexer, and Analog converting the second digital gray data set to generate the second gray voltage set Containing Driving method of liquid crystal display device.

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