KR20090009576A - Liquid crystal display - Google Patents

Abstract

A liquid crystal display is provided to securing a driving timing margin by reducing capacitance of the gate line. A liquid crystal panel assembly(300) comprises a plurality of display signal lines, and a plurality of pixels(PX) which is arranged in the form of approximately, the matrices while being connected to the signal wire. A gate driving unit(400) applies the gate signal received from outside which is made of the combination of the gate-off-voltage(Voff) and gate on voltage(Von) to the gate line(G1-Gn). A gray voltage generator(gray voltage generator)(800) produces two gradation voltage combination generations relating to the transmittance of pixel. Each data driver(500, 502) supplies those combination. A pair of data driver are connected to data line(D1a-Dma, D1b-Dmb) of the pair as long as the liquid crystal panel assembly includes. A signal control unit(600) controls the operation of data driver and gate driving unit.

Description

Liquid crystal display

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display capable of securing a driving timing margin by reducing a capacitance of a gate line.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which field generating electrodes such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light to display an image.

Among them, the vertical alignment mode liquid crystal display in which the long axis of the liquid crystal molecules are arranged perpendicular to the upper and lower display panels without an electric field is applied, and thus a high contrast ratio and a wide reference viewing angle can be easily realized. Here, the reference viewing angle refers to a viewing angle having a contrast ratio of 1:10 or a luminance inversion limit angle between gray levels.

Means for implementing a wide viewing angle in a vertical alignment mode liquid crystal display include a method of forming a cutout in the field generating electrode and a method of forming a protrusion on the field generating electrode. Since the inclination and the projection can determine the direction in which the liquid crystal molecules are tilted, the reference viewing angle can be widened by using these to disperse the oblique directions of the liquid crystal molecules in various directions.

However, the liquid crystal display of the vertical alignment type has a problem in that the side visibility is inferior to the front visibility. For example, in the case of a patterned vertically aligned (PVA) type liquid crystal display device having an incision, the image becomes brighter toward the side, and in a severe case, the luminance difference between the high grays disappears and the picture may appear clumped.

In order to solve such a problem, a method of applying a separate voltage to each subpixel by dividing a pixel into a pair of subpixels and forming a switching element in each subpixel has been proposed.

However, this method has an advantage in that the side visibility can be improved by freely applying a desired voltage to the divided pair of subpixels. However, since one pair of switching elements must be driven for one pixel, There is a disadvantage in driving timing than a liquid crystal display device having one switching element.

In addition, high frequency driving is required to improve the display quality of the moving image of the liquid crystal display. For example, when a pair of switching elements are used for each pixel in a high frequency drive such as a 120 Hz drive, a driving timing margin is absolutely insufficient.

An object of the present invention is to provide a liquid crystal display device capable of securing a driving margin by reducing a capacitance of a gate line.

Problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a plurality of pixels arranged in a matrix form, each pixel including a first subpixel and a second subpixel, and the first and second subpixels. Are connected to each other, and different gate signals are transmitted to each other, the first and second gate lines and the first and second gate lines connected to one gate driver and a first data signal are provided to the first subpixel. A plurality of first data lines and a plurality of second data lines crossing the first and second gate lines and transmitting a second data signal to the second subpixel are included.

Specific details of other embodiments are included in the detailed description and the drawings.

As described above, according to the liquid crystal display according to the present invention, by forming one thin film transistor on one gate line, it is possible to reduce the capacitance of the gate line to secure a driving timing margin.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400 connected thereto, and a pair of data drivers connected thereto. And a gray voltage generator 800 connected to the data drivers 500 and 502, and a signal controller 600 for controlling them.

The liquid crystal panel assembly 300 includes a plurality of display signal lines and a plurality of pixels PX connected to the display signal lines and arranged in a substantially matrix form when viewed in an equivalent circuit. Here, the liquid crystal panel assembly 300 includes a lower panel (not shown) facing each other, an upper panel (not shown), and a liquid crystal layer (not shown) interposed therebetween.

The display signal line is provided in the lower panel and includes a plurality of gate lines G1 -Gn for transmitting the gate signal and data lines D1a-Dma and D1b -Dmb for transmitting the data signal. The gate lines G1 -Gn extend substantially in the row direction, and are substantially parallel to each other, and the data lines D1a-Dma and D1b-Dmb extend substantially in the column direction and are substantially parallel to each other.

In Fig. 2, an equivalent circuit of a display signal line and a pixel is shown. The display signal line includes gate lines indicated by reference numerals GLa and GLb, data lines indicated by reference numerals DLa and DLb, and the like.

Referring to FIG. 2, each pixel PX includes a pair of subpixels PXa and PXb, and each subpixel PXa and PXb includes a corresponding data line DLa and DLb and a pair of gate lines. Switching elements Qa and Qb connected to GLa and GLb, liquid crystal capacitors Clca and Clcb connected thereto, and storage capacitors Csta and Cstb connected thereto are included. Here, the same gate signal is transmitted to the pair of gate lines Gla and GLb positioned above and below each pixel PX. The storage capacitors Csta and Cstb can be omitted as necessary.

The switching elements Qa and Qb of each of the subpixels PXa and PXb are formed of thin film transistors and the like provided on the lower display panel, and are connected to control terminals and data connected to the gate lines GLa and GLb to which gate signals are applied. A three-terminal device having an input terminal connected to the lines DLa and DLb, and an output terminal connected to the liquid crystal capacitors Clca and Clcb and the storage capacitors Csta and Cstb.

The liquid crystal capacitors Clca and Clcb have two terminals, a subpixel electrode of the lower panel and a common electrode of the upper panel, and the liquid crystal layer between the subpixel electrode and the common electrode functions as a dielectric. Each subpixel electrode is connected to each of the switching elements Qa and Qb, and the common electrode is formed on the front surface of the upper panel and receives the common voltage Vcom. Here, the common electrode may be provided on the lower panel, and at this time, at least one of the subpixel electrode and the common electrode may be linear or rod-shaped.

The storage capacitors Csta and Cstb, which serve as an auxiliary part of the liquid crystal capacitors Clca and Clcb, are formed by overlapping the storage electrode line and the subpixel electrode provided on the lower panel with an insulator interposed therebetween, and the common voltage Vcom on the storage electrode line. A predetermined voltage is applied. Here, the storage capacitors Csta and Cstb may be formed by the subpixel electrode overlapping the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel uniquely displays one of the primary colors (spatial division) or each pixel alternately displays three primary colors over time (time division) so that the spatial and temporal combinations of these three primary colors can be achieved. To recognize the desired color. Examples of primary colors include red, green and blue. As an example of spatial division, each pixel may include a color filter representing one of the primary colors in an area of the upper panel. In addition, the color filter may be formed above or below the subpixel electrode of the lower panel.

Referring back to FIGS. 1 and 2, the gate driver 400 is connected to the gate lines G1 -Gn to receive a gate signal formed by a combination of a gate on voltage Von and a gate off voltage Voff from the outside. It is applied to the gate lines G1 -Gn. The gate driver 400 is positioned on one side of the liquid crystal panel assembly 300 and is connected to gate lines G1 -Gn passing through the top and bottom of each pixel PX, respectively. As described above, the gate lines Gla and GLb passing through the upper and lower portions of each pixel PX may transmit the same gate signal or different gate signals to a pair of subpixels constituting each pixel PX. have. Here, different gate signals may have different gate voltages transmitted to the gate lines GLa and GLb, respectively. For example, a gate voltage of 20V may be transferred to the gate line GLa and 18V to the gate line GLb. Can be. In addition, different gate signals may be gate signals overlapping in a predetermined section.

The gray voltage generator 800 may generate two gray voltage sets (or reference gray voltage sets) related to the transmittance of the pixel and provide them to each data driver 500 and 502. That is, two sets of gray voltages may be independently provided to a pair of subpixels forming one pixel. However, the present invention is not limited thereto and only one gray voltage set may be generated instead of two gray voltage sets.

The pair of data drivers 500 and 502 are connected to the pair of data lines D1a-Dma and D1b-Dmb of the liquid crystal panel assembly 300, respectively. The data driver 500 positioned on the liquid crystal panel assembly 300 transfers a data voltage to any one of a pair of subpixels constituting one pixel through the data lines D1a -Dma. In addition, the data driver 502 disposed under the liquid crystal panel assembly 300 may have a separate data voltage at another subpixel among a pair of subpixels constituting one pixel through the data lines D1b-Dmb. To pass. Since the pair of data drivers 500 and 502 are disposed separately above and below the liquid crystal panel assembly 300, the number of driving circuits constituting each of the data drivers 500 and 502 is reduced by half, and thus, from each data driver. The pitch between the data lines coming out can be secured.

The gate driver 400 or the data drivers 500 and 502 may be mounted directly on the liquid crystal panel assembly 300 in the form of a plurality of driver integrated circuit chips, or may be mounted on a flexible printed circuit film (not shown). It may be mounted and attached to the liquid crystal panel assembly 300 in the form of a tape carrier package. Alternatively, the gate driver 400 or the data driver 500, 502 may be connected to the liquid crystal panel assembly 300 along with the display signal lines G1 -Gn, D1a-Dma, and D1b-Dmb and the thin film transistor switching element Q. It may be integrated.

The signal controller 600 controls operations of the gate driver 400 and the data driver 500.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 to 7.

FIG. 3 is a layout view of a lower panel for the liquid crystal display of FIG. 1, FIG. 4 is a cross-sectional view taken along line IV-IV ′ of FIG. 3, and FIG. 5 is a layout view of an upper panel for the liquid crystal display of FIG. 1. 6 is a layout view of a liquid crystal display including the lower panel of FIG. 3 and the upper panel of FIG. 5, and FIG. 7 is a cross-sectional view taken along the line VII-VII ′ of FIG. 6.

First, the lower panel of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.

A pair of first and second gate lines 22a and 22b and a storage electrode line 28 are formed on an insulating substrate made of transparent glass or the like.

The first and second gate lines 22a and 22b mainly extend in the horizontal direction, are physically and electrically separated from each other, and transmit gate signals. The first and second gate lines 22a and 22b are disposed above and below each pixel, respectively. In addition, a pair of first and second gate electrodes 26a and 26b are formed on the first and second gate lines 22a and 22b, respectively, and protrude downward and upward, and the first and second gate lines 22a are formed. Gate end ends 24a and 24b connected to the ends of the second and second ends of the second and second gate lines 22a and 22b to receive the gate signals from another layer or the outside. The gate line ends 24a and 24b have a large area for connection with the outside and are disposed on the left or right side with respect to the pixel area. As illustrated in FIG. 3, the first gate line 22a and the second gate line 22b may be connected to different gate line ends 24a and 24b, respectively. In this case, however, the same gate signal may be transmitted to the first and second gate lines 22a and 22b, and different gate signals may be transmitted as described above.

The storage electrode line 28 mainly extends in the horizontal direction, and the shape and arrangement of the storage electrode line 28 may be modified in various forms.

The first and second gate lines 22a and 22b and the storage electrode line 28 may be formed of aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, and copper (Cu) and the like. Copper-based metals such as copper alloys, molybdenum (Mo) and molybdenum-based metals such as molybdenum alloys, it may be made of chromium (Cr), titanium (Ti), tantalum (Ta). In addition, the first and second gate lines 22a and 22b and the storage electrode line 28 may have a multilayer structure including two conductive films (not shown) having different physical properties. One of the conductive films is a low resistivity metal such as an aluminum-based metal or a silver-based metal so as to reduce signal delay or voltage drop of the first and second gate lines 22a and 22b and the sustain electrode line 28. It consists of a metal, a copper type metal, etc. In contrast, the other conductive layer is made of a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, titanium, tantalum and the like. A good example of such a combination is a chromium bottom film and an aluminum top film and an aluminum bottom film and a molybdenum top film. However, the present invention is not limited thereto, and the first and second gate lines 22a and 22b and the storage electrode line 28 may be made of various metals and conductors.

A gate insulating layer 30 made of silicon nitride (SiNx) is formed on the first and second gate lines 22a and 22b and the storage electrode line 28.

A pair of semiconductor layers 40a and 40b made of hydrogenated amorphous silicon, polycrystalline silicon, or the like are formed on the gate insulating film 30. The semiconductor layers 40a and 40b may have various shapes such as island shape, linear shape, and the like, and may be formed in island shape as in the present embodiment.

On top of each of the semiconductor layers 40a and 40b, ohmic contact layers 55a and 56a made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of silicide or n-type impurities are formed. have. The ohmic contacts 55a and 56a are paired and positioned on the semiconductor layers 40a and 40b.

The pair of first and second data lines 62a and 62b and the first and second data lines 62a and 62b are respectively disposed on the ohmic contact layers 55a and 56a and the gate insulating layer 30. Corresponding pairs of first and second drain electrodes 66a and 66b are formed.

The first and second data lines 62a and 62b mainly extend in the vertical direction to intersect the first and second gate lines 22a and 22b and the storage electrode line 28 and transmit a data voltage. First and second source electrodes 65a and 65b are formed on the first and second data lines 62a and 62b to extend toward the first and second drain electrodes 66a and 66b, respectively. At the end of the first and second data lines 62a and 62b, the data line ends 68a and 68b receive a data signal from another layer or the outside and transfer the data signals to the first and second data lines 62a and 62b, respectively. Is formed. At this time, the data line ends 68a and 68b are extended in width for connection with an external circuit. The data line ends 68a and 68b may be disposed above or below, but as in the present embodiment, the data line ends 68a and the data line ends 68b may be separated from each other and disposed above or below, respectively. Can be. As shown in FIG. 3, one pixel is divided into a pair of subpixels, the first data line 62a transmits a data signal to one subpixel, and the second data line 62b is another subpixel. It transmits a separate data signal to the pixel.

The first and second data lines 62a and 62b, the first and second source electrodes 65a and 65b, and the drain electrodes 66a and 66b are made of a refractory metal such as chromium, molybdenum-based metal, tantalum, and titanium. Preferably, it may have a multilayer structure consisting of a lower layer (not shown) such as a refractory metal and an upper layer (not shown) of a low resistance material disposed thereon. Examples of the multilayer film structure include a triple film of molybdenum film, aluminum film, and molybdenum film in addition to the above-described double film of chromium lower film and aluminum upper film or aluminum lower film and molybdenum upper film.

The first and second source electrodes 65a and 65b overlap at least a portion of the semiconductor layers 40a and 40b, respectively, and the first and second drain electrodes 66a and 66b respectively form the gate electrodes 26a and 26b. At least a portion of the semiconductor layer 40a and 40b may be overlapped with the first and second source electrodes 65a and 65b. Here, the aforementioned ohmic contact layers 55a and 56a include the lower semiconductor layers 40a and 40b, the first and second source electrodes 65a and 65b, and the first and second data lines. It exists between 62a and 62b) and lowers contact resistance.

A passivation layer 70 is formed on the first and second data lines 62a and 62b, the drain electrodes 66a and 66b, and the exposed portions of the semiconductor layers 40a and 40b. The passivation layer 70 is an inorganic material made of silicon nitride or silicon oxide, an organic material having excellent planarization characteristics and photosensitivity, or a-Si: C: O formed by plasma enhanced chemical vapor deposition (PECVD), It consists of low dielectric constant insulating materials, such as a-Si: O: F. In addition, the passivation layer 70 may have a double layer structure of the lower inorganic layer and the upper organic layer in order to protect the exposed portions of the semiconductor layers 40a and 40b while maintaining excellent characteristics of the organic layer.

The passivation layer 70 has first and second subpixel electrodes electrically connected to the first and second drain electrodes 66a and 66b through contact holes 76a and 76b and positioned in the pixel region, respectively. 82a and 82b are formed. Further, the auxiliary gate line ends 86a and 86b connected to the gate line ends 24a and 24b and the data line ends 68a and 68b, respectively, through the contact holes 74a, 74b, 78a and 78b on the passivation layer 70. ) And auxiliary data line ends 88a and 88b. Here, the first and second subpixel electrodes 82a and 82b, the auxiliary gate line ends 86a and 86b, and the auxiliary data line ends 88a and 88b may be transparent conductors such as ITO or IZO or reflective conductors such as aluminum. Made of sieve.

The first and second subpixel electrodes 82a and 82b are physically and electrically connected to the first and second drain electrodes 66a and 66b through the contact holes 76a and 76b, respectively. Different data voltages are applied from 66a and 66b.

The first and second subpixel electrodes 82a and 82b to which the data voltage is applied generate an electric field together with the common electrode of the upper panel, thereby forming a liquid crystal layer between the first and second subpixel electrodes 82a and 82b and the common electrode. Determines the arrangement of liquid crystal molecules.

In addition, as described above, each of the subpixel electrodes 82a and 82b and the common electrode form liquid crystal capacitors Clca and Clcb to maintain the applied voltage even after the thin film transistors Qa and Qb are turned off and maintain the voltage holding capability. In order to reinforce, the storage capacitors Csta and Cstb connected in parallel with the liquid crystal capacitors Clca and Clcb may include the first and second subpixel electrodes 82a and 82b or the drain electrodes 66a and 66b and the storage electrode lines connected thereto. (28) is made of overlapping.

The first and second subpixel electrodes 82a and 82b constituting one pixel electrode are engaged with each other with a predetermined gap 83 (gap) 83 interposed therebetween, and the outer boundary thereof is substantially rectangular. The first subpixel electrode 82a is a rotated equilateral trapezoid, the left side of which is located near the first data line 62a, the right side of the opposite side thereof, and an upper hypotenuse which is approximately 45 ° with the gate lines 22a and 22b. And lower hypotenuse. The second subpixel electrode 82b includes a pair of trapezoids facing the hypotenuse of the first subpixel electrode 82a and a vertical portion facing the right side of the first subpixel electrode 82a. Therefore, the gaps 83 and 83 between the first subpixel electrode 82a and the second subpixel electrode 82b have a substantially uniform width, and an upper diagonal line forming about 45 ° with the gate lines 22a and 22b. It includes the upper and lower oblique portion and the vertical portion connecting them. In this case, the size and shape of the first and second subpixel electrodes 82a and 82b may be variously changed according to design elements.

The auxiliary gate line ends 86a and 86b and the auxiliary data line ends 88a and 88b are connected to the gate line ends of the first and second gate lines 22a and 22b through the contact holes 74a, 74b, 78a and 78b. 24 and the respective data line ends 68a and 68b of the first and second data lines 62a and 62b, respectively, and the auxiliary gate line ends 86a and 86b and the auxiliary data line ends 88a and 88b. Adhesiveness between the gate line end 24 of the first and second gate lines 22a and 22b and the data line end 68a and 68b of the first and second data lines 62a and 62b and an external device Complement and protect them.

When the gate driver 400 or the data drivers 500 and 502 shown in FIG. 1 are integrated on the liquid crystal panel assembly 300, the first and second gate lines 22a and 22b or the first and second data lines are illustrated. 62a and 62b may be extended to be directly connected to them, in which case the auxiliary gate line ends 86a and 86b and the auxiliary data line ends 88a and 88b may be connected to the first and second gate lines 22a and 22b, or The first and second data lines 62a and 62b and the driving units 400, 400a, 400b, 500, and 502 may be used.

An alignment layer (not shown) capable of orienting the liquid crystal layer on the first and second subpixel electrodes 82a and 82b, the auxiliary gate line ends 86a and 86b, the auxiliary data line ends 88a and 88b, and the passivation layer 70. ) Is applied.

Next, the upper panel will be described with reference to FIGS. 5 to 7.

A common electrode made of a black matrix 94 for preventing light leakage on the insulating substrate 96 made of transparent glass, a color filter 98 of red, green, and blue, and a transparent conductive material such as ITO or IZO. ) 90 is formed. The black matrix 94 may be formed of a portion corresponding to the first and second gate lines 22a and 22b and the first and second data lines 62a and 62b and a portion corresponding to the thin film transistor. In addition, the black matrix 94 may have various shapes to block light leakage near the first and second subpixel electrodes 82a and 82b and the thin film transistors Qa and Qb.

The common electrode 90 faces the first and second subpixel electrodes 82a and 82b and has cutouts 92a and 92b. Here, each of the cutouts 92a and 92b has an oblique line that forms approximately 45 ° with respect to the gate lines 22a and 22b.

An alignment layer (not shown) may be coated on the common electrode 90 to align the liquid crystal molecules.

FIG. 6 is a layout view of a liquid crystal display including the lower display panel of FIG. 3 and the upper display panel of FIG. 5, wherein oblique portions of the cutouts 92a and 92b of the common electrode 90 are formed of the first subpixel electrode 82a and the first subpixel electrode 82a. The upper diagonal portion and the lower diagonal portion of the gap 83 between the two subpixel electrodes 82b are arranged in the center.

When the lower panel and the upper panel of the structure are aligned and combined, and a liquid crystal material is injected and vertically aligned therebetween, a basic structure of the liquid crystal display is provided. When the lower display panel and the upper display panel are aligned, the gap 83 between the first subpixel electrode 82a and the second subpixel electrode 82b and the cutouts 92a and 92b of the common electrode 90 are formed in the pixel area. Is divided into a number of small domains, which expands the reference viewing angle.

Here, the at least one cutout 92a and 92b may be replaced with a protrusion or a depression, and the shape and arrangement of the cutouts 92a and 92b may be variously modified.

Hereinafter, the display operation of the liquid crystal display device of the present invention will be described in detail with reference to FIGS. 1 and 2.

The signal controller 600 may control input image signals R, G, and B and display thereof from an external graphic controller (not shown), for example, a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync. ), The main clock MCLK, and the data enable signal DE are provided. Based on the input image signals R, G, and B and the input control signal of the signal controller 600, the image signals R, G, and B may be appropriately processed according to the operating conditions of the liquid crystal panel assembly 300, and the gate control signal may be used. After generating the CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. 502).

The gate control signal CONT1 includes a scan start signal STV indicating the start of scanning and at least one clock signal controlling the output time of the gate-on voltage Von. The gate control signal CONT1 may also include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 is a load signal for applying a corresponding data voltage to the horizontal synchronization start signal STH for transmitting data to a group of pixels PX and the data lines D1a-Dma and D1b-Dmb. LOAD) and data clock signal HCLK. The data control signal CONT2 also inverts the signal RVS which inverts the polarity of the data voltage with respect to the common voltage Vcom (hereinafter referred to as "polarity of the data voltage" by reducing the "polarity of the data voltage with respect to the common voltage"). It may include.

According to the data control signal CONT2 from the signal controller 600, the data drivers 500 and 502 receive respective image data DAT for the pair of subpixels PXa and PXb and generate a gray voltage. By converting each image data DAT to the corresponding data voltage by selecting the gray scale voltage corresponding to each image data DAT from the unit 800, and applying the gray voltage to the corresponding data lines D1a-Dma and D1b-Dmb. do.

The gate driver 400 applies a gate-on voltage Von to the gate lines G1 -Gn according to the gate control signal CONT1 from the signal controller 600, and is connected to the gate lines G1 -Gn. (Qa, Qb) is turned on, and accordingly data voltages applied to the data lines D1a-Dma and D1b-Dmb are applied to the corresponding subpixels PXa and PXb through the turned-on switching elements Qa and Qb. .

The difference between the data voltage applied to each of the subpixels PXa and PXb and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitors Clca and Clcb, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage. Accordingly, the polarization of light passing through the liquid crystal layer changes, which is represented by a change in the transmittance of light.

In the liquid crystal display of the present invention, as shown in FIG. 2, the gate voltage is transmitted to the pair of subpixels PXa and PXb through the pair of gate lines GLa and GLb. In this case, the same gate signal or different gate signals may be applied through the pair of gate lines GLa and GLb. In addition, unlike the structure in which two switching elements are connected to one gate line, one switching element is connected to one gate line, thereby effectively reducing the capacitance of the gate line. For example, the capacitance of the gate lines GLa and GLb may be 2000 pF or less. Therefore, the driving time of the gate signal can be sufficiently secured, so that the driving margin of the gate signal can be secured. In addition, the side visibility can be improved by connecting the pair of data signals DLa and DLb to the pair of subpixels PXa and PXb, respectively.

Furthermore, when the liquid crystal display device of the high-definition product is driven at a high frequency, a sufficient charging rate of the liquid crystal capacitors Clca and Clcb may not be obtained because the driving time of the gate signal is very short. For example, when the liquid crystal display of 1920 x 1080 resolution is driven at 120 Hz, the driving time of the gate signal is only about 7.5 mW. In this case, various types of dot inversion can be used by simultaneously applying a gate signal to the first and second gate lines. Furthermore, in order to more effectively prevent flickering, column inversion can be used to achieve the first and second gate lines. The driving timing margin can be secured by applying the second gate signal to overlap the time.

8 illustrates a signal waveform of a liquid crystal display according to an exemplary embodiment of the present invention over time, and illustrates a signal waveform by thermal inversion. Here, Vg (i) is a gate voltage applied to the pixel located in the (i) th row, Vg (i + 1) is a gate voltage applied to the pixel located in the (i + 1) th row, and Vda_pos is a first The positive data voltage flowing through the data line, Vda_neg is the negative data voltage flowing through the first data line, Vdb_pos is the positive data voltage flowing through the second data line, and Vdb_neg is the negative data voltage flowing through the second data line. As shown in FIG. 2, the same gate voltage, for example, Vg (i) or Vg (i + 1) is applied to each gate of the switching elements Qa and Qb to simultaneously turn on the switching elements Qa and Qb. Accordingly, one of the data voltages of Vda_pos and Vda_neg is applied to the subpixel PXa, and one of the data voltages of Vdb_pos and Vdb_neg is applied to the subpixel PXa.

9 illustrates a signal waveform of a liquid crystal display according to another exemplary embodiment of the present invention over time, and illustrates signal waveforms due to thermal inversion. Here, Vg (i) denotes a gate voltage applied to the pixel located in the (i) th row, and Vg (i + 1) denotes a gate voltage applied to the pixel located in the (i + 1) th row. Vg (i + 1) is a signal that is delayed for a predetermined time and overlaps with Vg (i). Since the upper and lower adjacent pixels have the same polarity, pre-charge may be performed by applying a data voltage of adjacent pixels. In this case, as shown in FIG. 9, the charging times of all the subpixels may be overlapped for a predetermined time or more.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 3 is a layout view of a lower panel for the liquid crystal display of FIG. 1.

4 is a cross-sectional view taken along the line IV-IV ′ of FIG. 3.

FIG. 5 is a layout view of an upper panel for the liquid crystal display of FIG. 1.

FIG. 6 is a layout view of a liquid crystal display including the lower panel of FIG. 3 and the upper panel of FIG. 5.

FIG. 7 is a cross-sectional view taken along the line VII-VII 'of FIG. 6.

8 illustrates a signal waveform of a liquid crystal display according to an exemplary embodiment of the present invention over time.

9 is a diagram illustrating signal waveforms of a liquid crystal display according to another exemplary embodiment of the present invention over time.

(Explanation of symbols for the main parts of the drawing)

22a, 22b: gate line 24a, 24b: gate line end

26a, 26b: gate electrode 28: sustain electrode line

40a, 40b: semiconductor layers 62a, 62b: data lines

65a, 65b: source electrode 66a, 66b: drain electrode

68a, 68b: data line ends

74a, 74b, 76a, 76b, 78a, 78b: contact hole

82a and 82b: subpixel electrodes 86a and 86b: auxiliary gate line ends

88a, 88b: auxiliary data line end 300: liquid crystal panel assembly

400: gate driver 500, 502: data driver

600: signal controller 800: gray voltage generator

Claims (1)

A plurality of pixels arranged in a matrix form, each pixel including a first subpixel and a second subpixel; A plurality of first and second gate lines connected to the first and second subpixels, different gate signals are transmitted, and connected to one gate driver; And A plurality of first data lines intersecting the first and second gate lines and transferring a first data signal to the first subpixel; And And a plurality of second data lines crossing the first and second gate lines and transferring a second data signal to the second subpixel.

Images