KR20060040515A - Plasma display panel - Google Patents

Abstract

A plasma display panel is disclosed. The present invention provides a front panel comprising a front substrate, X and Y electrodes formed on an inner surface thereof, an M electrode disposed therebetween, and a front dielectric layer embedded therein; a rear substrate disposed to face the front substrate; A rear panel formed on an inner surface thereof and having an address electrode disposed in a direction intersecting the X and Y electrodes and a rear dielectric layer embedded therein, the rear panel disposed between the front and rear panels and partitioning a discharge space; And a red, green, and blue phosphor layer coated in the partition wall, wherein the M electrode is disposed in the display area of the panel for implementing an image and in the terminal area of the panel connected to the external terminal. And a portion disposed in the connection region between the display region and the terminal region are electrically connected to each other, and the width of the electrode portion disposed in the terminal region is equal to that of the electrode portion disposed in the connection region. Formed relatively wider than the width, the width of the M electrode disposed between the X and Y electrodes causing display sustain discharge is limited to a specific value in the terminal region and the connection region, thereby preventing the disconnection of the electrode in advance.

Description

Plasma display panel {Plasma display panel}

1 is a perspective view showing a part of the structure of a conventional discharge electrode,

2 is an exploded perspective view of a plasma display panel partially cut out according to an embodiment of the present invention;

3 is a configuration diagram of a plasma display device according to an embodiment of the present invention;

4 is a perspective view illustrating an electrode of a discharge cell according to an embodiment of the present invention;

5 is a waveform diagram of signals applied to the electrode line of FIG. 4;

6 to 11 illustrate changes in the wall charge distribution of FIG. 5.

FIG. 6 is a cross-sectional view showing a change in wall charge distribution of discharge cells at t ₁ to t ₂ hours in FIG. 5;

FIG. 7 is a cross-sectional view showing a change in wall charge distribution of discharge cells at t ₂ to t ₃ time of FIG. 5;

FIG. 8 is a cross-sectional view showing a change in wall charge distribution of discharge cells at t ₃ to t ₄ hours in FIG. 5;

9 is a cross-sectional view showing a change in the wall charge distribution of the discharge cells at t ₅ to t ₆ hours in FIG. 5;

FIG. 10 is a cross-sectional view showing wall charge distribution changes of discharge cells at t ₇ to t ₈ hours in FIG. 5;

FIG. 11 is a cross-sectional view illustrating a change in wall charge distribution of discharge cells at t ₈ to t ₁₂ hours in FIG. 5.

<Brief description of symbols for the main parts of the drawings>

400 ... substrate 401 ... display area

402 ... non-display area 403 ... connection area

404 ... terminal area 410 ... X electrode

420 ... Y electrode 430 ... M electrode

431 ... Third Transparent Electrode Line 432. Third Bus Electrode Line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, wherein a width of a portion connected to an external terminal of an M electrode disposed between X and Y electrodes is different from that of another electrode portion of a substrate.

In general, a plasma display panel injects and discharges a discharge gas on two substrates on which a plurality of discharge electrodes are formed, and then applies a discharge voltage. When the gas emits light between the two electrodes due to the discharge voltage, an appropriate pulse voltage is applied. It refers to a flat displat device that applies the address to the point where the two electrodes intersect to implement the desired number, letter or graphic.

Such a plasma display panel may be classified into a direct current type and an alternating current type according to a type of driving voltage applied to a discharge cell, for example, a discharge type, and may be classified into a counter discharge type and a surface discharge type according to the configuration of the electrodes.

1 shows a plasma display panel 100 disclosed in Japanese Patent Laid-Open No. 4-56039.

Referring to the drawings, the plasma display panel 100 has a plurality of pairs of discharging electrodes 102 for deciding the discharging cells for emitting light on the inner surface of the glass substrate 101 are arranged in parallel in the X direction. On the inner surface of the glass substrate on the rear side, which is not shown, an address electrode for selecting a light-emitting dot is arranged.

Moreover, the terminal part 103 which enlarged the electrical discharge electrode 102 is formed in the edge of the said glass substrate 101 in order to connect with a drive circuit. The discharging electrode 102 includes a strip-shaped transparent electrode 104 and a bus electrode 105 overlapping the transparent electrode 104 in the extending direction. The bus electrode 105 protrudes in the X direction with respect to the transparent electrode 104, and the protruding portion includes the terminal portion 103 and is formed directly on the glass substrate 101.

In recent years, as the plasma display panel becomes larger, a long gap discharge is generated between the plurality of discharge electrodes 102 to generate a long gap discharge between the discharge electrodes 102, thereby improving luminance. A multi-electrode plasma display panel is being developed.

The multi-electrode plasma display panel is arranged to have a smaller width than the discharge electrode 102 because the M electrode is disposed in the discharge cell. This can cause a bad connection.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the plasma width which prevents the disconnection failure of the electrode by quantifying the relative width relationship between the M electrode portion disposed in the terminal region of the substrate and the M electrode portion disposed in the connection region of the substrate The purpose is to provide a display panel.

In order to achieve the above object, the plasma display panel according to an aspect of the present invention,

A front panel comprising a front substrate, an X and Y electrode formed on an inner surface thereof, an M electrode disposed between the X and Y electrodes, and a front dielectric layer embedded therein;

A rear panel formed on a rear substrate facing the front substrate, an rear surface panel formed on an inner surface thereof and having an address electrode disposed in a direction crossing the X and Y electrodes, and a rear dielectric layer embedded therein;

A partition wall disposed between the front and rear panels and partitioning a discharge space;

It includes; red, green, blue phosphor layer applied in the partition wall,

The M electrode may be electrically disposed in a display area of a panel embodying an image, in a terminal area of a panel connected to an external terminal, and in a connection area between the display area and the terminal area. Is connected,

The width of the electrode portion disposed in the terminal region may be formed to be relatively wider than the width of the electrode portion disposed in the connection region.

The width of the electrode portion disposed in the terminal region and the width of the electrode portion disposed in the connection region satisfy the following equation.

Equation

0.42 ≤ W ₁ / W ₂ ≤ 1.0

Here, W ₁ is the width of the M electrode portion disposed in the connection region, and W ₂ is the width of the M electrode portion disposed in the terminal region.

In addition, the width of the electrode portion disposed in the connection region may be substantially the same as the width of the electrode portion disposed in the display region.

Further, the M electrode is characterized by consisting of a transparent electrode line and a bus electrode line superimposed on the transparent electrode line.

In addition, the M electrode is disposed in the discharge gap between the X and Y electrodes, the width is characterized in that formed relatively narrower than the width of the X and Y electrodes.

Further, a trigger discharge voltage is applied between the X and M electrodes, and a sustain discharge voltage is applied between the X and Y electrodes.

Hereinafter, a plasma display panel according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 illustrates a four-electrode surface discharge plasma display panel 200 according to an embodiment of the present invention.

Referring to the drawings, the plasma display panel 200 includes a front panel 210 and a back panel 260 coupled to the front panel 210. Frit glass is applied to opposing inner edges of the front and rear panels 210 and 260 to seal them to form a discharge space.

The front panel 210 is provided with a transparent substrate, for example, a front substrate 211 such as soda lime glass. X and Y electrodes 212 and 213 are disposed on the inner surface of the front substrate 211.

The X and Y electrodes 212 and 213 are arranged in a stripe shape along the X direction of the panel 200, and are disposed in pairs to face each other in the unit discharge cell. The X electrode 212 includes a first transparent electrode line 212a and a first bus electrode line 212b disposed along one edge of the first transparent electrode line 212a and the Y electrode 213. ) Is composed of a second transparent electrode line 213a and a second bus electrode line 212b disposed along one edge of the second transparent electrode line 212a.

Between the pair of X and Y electrodes 212 and 213, an M electrode 214, which is another discharge electrode, is disposed to induce their long gap discharge. The M electrode 214 is disposed in parallel with the X and Y electrodes 212 and 213. In addition, the M electrode 214 is striped like the X and Y electrodes 212 and 213, and a voltage different from that of the X and Y electrodes 212 and 213 is applied.

Alternatively, the shape of the X and Y electrodes 212 and 213 and the M electrode 214 or the structure disposed in the discharge cell may be arranged in each unit discharge cell to initiate discharge from the gap between the electrodes. If it can, it is not limited to any one shape or structure.

The X and Y electrodes 212 and 213 and the M electrode 214 interposed therebetween are embedded by the front dielectric layer 215. The front dielectric layer 215 is coated on the front substrate 211 using a transparent dielectric such as PbO—B ₂ O ₃ —SiO ₂ . Alternatively, the front dielectric layer 215 may be selectively applied only to the portions where the X and Y electrodes 212 and 213 and the M electrode 214 are formed.

A passivation layer 216 made of magnesium oxide (MgO) is formed on the front surface of the front dielectric layer 215 to increase secondary electron emission. The passivation layer 216 is applied to the entire surface of the front dielectric layer 215.

The back panel 260 is provided with a back substrate 261 made of a transparent glass substrate, for example, soda lime glass. The rear substrate 261 is disposed to face the front substrate 211.

An address electrode 262 is formed on the inner surface of the back substrate 261. The address electrode 262 is striped and disposed in a direction crossing the X and Y electrodes 212 and 213. The address electrode 262 extends across the discharge cells disposed adjacent to the Y direction of the panel 200. The address electrode 262 is made of a metal material having excellent conductivity, such as silver paste.

The address electrode 262 is embedded by the back dielectric layer 263. The back dielectric layer 263 is made of a high dielectric material substantially the same as the front dielectric layer 216.

The partition wall 264 is disposed between the front and rear panels 210 and 260. The partition wall 264 may include a first partition wall 264a disposed in a direction orthogonal to a direction in which the address electrode 262 is disposed, and a second partition wall disposed in a direction parallel to the direction in which the address electrode 262 is disposed ( 264b). The second partition 264b extends in a direction opposite from the inner walls of the pair of adjacent first partitions 264a to partition the discharge space.

The first and second partitions 264a and 264b are integrally coupled to each other, and the divided discharge space is substantially rectangular. Alternatively, the partition wall 264 may be manufactured in various shapes such as a waffle type, meander type, or delta type, and the discharge space may also be circular, triangular, or hexagonal. It will be said that various embodiments exist.

On the other hand, red, green, and blue phosphor layers 265 are coated on the inner wall of the partition wall 264 and the upper surface of the back dielectric layer 263 for each discharge cell. In addition, a discharge gas of neon (Ne) -xenon (Xe) is injected into the discharge space defined by the front and rear panels 210 and 260 and the partition wall 264.

3 is a block diagram of a plasma display device 300 employing a four-electrode plasma display panel according to an embodiment of the present invention.

Referring to the drawings, the plasma display device 300 includes a plasma display panel 310, an image processor 301, a logic controller 302, an address driver 303, an X driver 304, a Y driver 305, and the like. The M driver 306 is included.

The image processor 301 processes an external image signal to generate an internal image signal including red, green, and blue digital image data, a clock signal, and vertical and horizontal synchronization signals. The logic controller 302 generates drive-control signals S _M , S _A , S _X , S _Y in accordance with an internal image signal from the image processor 301.

The address driver 303 processes the address signals S _A from the logic controller 302 to generate display data signals, and transmits the generated display data signals to the address electrode lines A ₁ , ... Am. Is authorized.

The drive M 306 M driven from the logic controller (302) operates in accordance with a control signal (S _M) M electrode lines and drives the _{(M 1, ..., M n} ). The X driver 304 operates in accordance with the X drive-control signal S _X from the logic controller 302 to drive the X electrode lines X ₁ ,..., X _m . The Y driver 305 operates in accordance with the Y drive-control signal S _Y from the logic controller 302 to drive the Y electrode lines Y ₁ ,..., Y _n .

At this time, scanning pulses are sequentially applied to each of the M electrode lines M ₁ ,..., And M _n , and at the same time, a data pulse is applied to an address electrode line selected from among the address electrode lines A ₁ , ... Am. This is done.

Next, between all X electrode lines (X ₁ , ..., X _n ) and all Y electrode lines (Y ₁ , ..., Y _n ) so that the discharge cells selected by addressing cause display-holding discharges. AC voltage is applied.

Accordingly, all X and Y electrode line pairs (X ₁ Y ₁ , X ₂ Y ₂ ,..., X _n Y _n ) and all Y and X electrode line pairs (Y ₁ X ₂ , Y ₂ X ₃ ,. ..., Y _{n -1} X _n ), the discharge cells can be set.

Further, by the addressing, a wall charge state necessary for display-holding discharge is formed for both the X and Y electrodes of the selected discharge cell, and at least one of the X- and Y electrodes of the unselected discharge cell is required for display-holding discharge. No wall charge is formed.

For example, in four M electrode lines arranged in series, if there are two unselected discharge cells between two selected discharge cells, display-maintained discharge at either of the X and Y electrodes of each of the two unselected discharge cells. The wall charge condition required for the Therefore, while the discharge cells are set by all the X and Y electrode lines and all the Y and X electrode lines, a progressive driving method can be applied.

At this time, the M electrode disposed between the X and Y electrodes is formed to be relatively wider than the width of the other portion of the portion connected to the external terminal, this relative width is limited by a specific value.

4 illustrates the structure of the discharge electrodes 410 to 430 according to an embodiment of the present invention.

Referring to the drawings, the substrate 400 may include a display area 401 for implementing an image by applying a predetermined discharge voltage to the discharge electrodes 410 to 430, and the discharge electrodes 410 to 430 having external terminals. And a non display area 402 to be connected to.

The non-display area 402 may be divided into a connection area 403, which is an edge area of the display area 401, and a terminal area 404, which is an edge area of the connection area 403. The connection area 403 is an area where the discharge electrodes 410 to 430 are drawn out from the display area 401, and the terminal area 404 is where the discharge electrodes 410 to 430 are flexible printed cables. It is an area to be connected with external terminal such as cable).

The X electrode 410 and the Y electrode 420 are disposed on one side thereof on the substrate 400. An M electrode 430 is disposed between the X and Y electrodes 410 and 420. The X and Y electrodes 410 and 420 and the M electrode 430 are all stripe-shaped, and three electrodes are positioned side by side in each unit discharge cell.

The X electrode 410 includes a first transparent electrode line 411 formed on the surface of the substrate 400 and a first bus electrode line 412 formed at one edge of the first transparent electrode line 411. have. The first transparent electrode line 411 is disposed in the display area 401, and the first bus electrode line 412 is shown from the display area 401 along the length direction of the first transparent electrode line 411. It extends to the non-display area opposite to the non-substrate 400.

The Y electrode 420 may include a second transparent electrode line 421 formed on a surface of the substrate 400 and a second bus electrode line 422 disposed along one edge of the second transparent electrode line 421. It is included. The second transparent electrode line 421 is disposed in the display area 401, and the second bus electrode line 422 extends from the display area 401 along the length direction of the second transparent electrode line 421. It extends over the connection area 403 and the terminal area 404. The second bus electrode line 422 overlaps the second transparent electrode line 421 in the display area 401. The X and Y electrodes 410 and 420 may be electrically connected to external terminals in different directions of the substrate 400.

The M electrode 430 includes a third transparent electrode line 431 formed on the surface of the substrate 400, and a third bus electrode line 432 electrically connected to the third transparent electrode line 431. .

The third transparent electrode line 431 is disposed in the display area 401, and the third bus electrode line 432 extends from the display area 401 to connect the connection area 403 and the terminal area 404. It extends over.

The M electrode 430 has a double layer structure including a third transparent electrode line 431 and a third bus electrode line 432 superimposed on the third transparent electrode line 431. In this case, the third transparent electrode line 431 is formed to be wider than the third bus electrode line 432. Alternatively, the M electrode 430 may have a single layer structure in which only one of the third bus electrode line 432 and the third transparent electrode line 431 is disposed.

The third bus electrode line 432 extends from the display area 401 of the substrate 400 to the terminal area 404 over the connection area 403 and consists of one single line. In addition, the third bus electrode line 432 and the third transparent electrode line 431 may not be limited to any one structure such that the third bus electrode line 432 and the third transparent electrode line 431 may be arranged to overlap the connection region 403.

For example, when only the third bus electrode line 432 is drawn from the display area 401 to the terminal area 404 via the connection area 403, the third bus electrode line 431 is an image. An electrode portion 432a disposed in the display region 401, an electrode portion 432b disposed in the connection region 402 drawn out of the display region 401, and a terminal region connected to an external terminal. It can be divided into the electrode portion 432c disposed in the 404, they are all integrally connected together.

In this case, the electrode portion 432c disposed in the terminal region 404 is formed relatively wider than the electrode portion 432b disposed in the connection region 402. In addition, the relative widths of the two electrode portions 432b and 432c satisfy the following equation.

Equation

0.42 ≤ W ₁ / W ₂ ≤ 1.0

Here, W ₁ is the width of the electrode portion 432b disposed in the connection region 403, and W ₂ is the width of the electrode portion 432c disposed in the terminal region 404.

That is, in order to prevent disconnection failure of the M electrode 430, it is preferable that the relational expression of the relative widths of the electrode portions 432b and 432c disposed in the connection and terminal regions 403 and 404 satisfy the above equation. .

In addition, the width of the electrode portion 432b disposed in the connection region 403 is substantially the same as the width of the electrode portion 432a disposed in the display region 401. Alternatively, the width of the electrode portion 432b disposed in the connection region 403 may be made larger than the width of the electrode portion 432a disposed in the display region 401.

On the other hand, since the M electrode 430 is disposed in the discharge gap between the X electrode 410 and the Y electrode 420, the overall width of the M electrode 430 is the X and Y in consideration of the influence of the opening ratio The electrodes 410 and 420 are formed to be relatively narrower than the total width of each.

In addition, the first to third transparent electrode lines 411 to 431 are all made of a transparent electrode, for example, an indium tin oxide (ITO) film, and the first to third bus electrode lines 412 to 432 are conductive. It is preferable that this excellent material is made of a multi-metal film of silver paste (Ag paste) or chromium-copper-chromium (Cr-Cu-Cr).

Hereinafter, the disconnection failure according to the width change of the electrode by the applicant's experiment is as shown in Table 1.

TABLE 1

W ₁ W ₂ Disconnection W ₁ / W ₂ W ₁ W ₂ Disconnection W ₁ / W ₂ 75 225 9 0.33 155 225 0 0.69 85 225 6 0.38 165 225 0 0.73 95 225 0 0.42 175 225 0 0.78 105 225 0 0.47 185 225 0 0.82 115 22 0 0.51 195 225 0 0.87 125 225 0 0.56 205 225 0 0.91 135 225 0 0.60 215 225 0 0.96 145 225 0 0.64 225 225 0 1.00

Here, W ₁ is an M electrode portion disposed in the connection region, and W ₂ is an M electrode portion disposed in the terminal region.

Referring to Table 1, the relative change (W ₁ / W ₂ ) of the width W ₁ of the M electrode portion disposed in the connection region of the substrate and the width W ₂ of the M electrode disposed in the terminal region is less than 0.42. When larger and smaller than 1.0, disconnection failure of the electrode is 0, whereas disconnection failure occurs when the relative width change is less than 0.42. Therefore, in order to prevent disconnection failure of the electrode, the size of the M electrode should be designed to fall within the above range.

Hereinafter, the operation of the multi-electrode plasma display panel according to an embodiment of the present invention will be described.

5 illustrates a signal applied to an electrode line of the plasma display panel of FIG. 4, and FIGS. 6 to 11 illustrate changes in wall charge distribution of unit discharge cells at t ₁ to t ₁₂ hours of FIG. 5.

Here, the X and Y electrodes 410 and 420 and the M electrode 430 are buried by the front dielectric layer 616, and a protective film layer 617 is deposited on the surface of the front dielectric layer 616. In addition, the address electrode 662 disposed in the direction crossing the X and Y electrodes 410 and 420 is embedded by a back dielectric layer 663, and a phosphor layer 667 is coated on the surface thereof.

5, a unit in the last display immediately before the end time (t ₁₂₎ of the sub-field sustain pulse is therefore applied to all the X electrode lines, any one unit in the last point in time (t ₁₂₎ of the sub-field that is, units of the sub-fields At the initial time point t ₁ of the unit subfield following, negative wall charges are formed around the X electrode of the discharge cells selected in the previous subfield, and positive polarities are formed around the Y electrode of the discharge cells selected in the previous subfield. Wall charges are formed.

5 and 6, in the wall charge erase time t ₁ to t ₂ of the resetting time R of the unit subfield, all pulses of the second voltage Vs are applied to all the Y electrode lines. The voltage applied to the M electrode line is continuously lowered from the second voltage Vs to the ground voltage V _G as the third voltage. At this time t ₁ to t ₂ , the ground voltage V _G is applied to the X electrode line and the address electrode line. Accordingly, wall discharges of all the discharge cells are erased while weak discharges occur between the electrodes of all the discharge cells.

5 and 7, the wall charge accumulation time t ₂ to t ₃ is applied to all the M electrode lines while the ground voltage V _G is applied to the X electrode line, the Y electrode line, and the address electrode line. The voltage to be continuously increased to the first voltage V _SET + Vs which is higher by the fourth voltage V _SET than the second voltage Vs. Here, it may be raised nonlinearly as shown by the solid line, or it may be raised linearly as shown by the dotted line. Accordingly, while a weak discharge occurs between the electrodes of all the discharge cells, a large number of negative wall charges are formed around the M electrode, and positive wall charges are formed around the remaining electrodes.

Referring to FIGS. 5 and 8, in the wall charge distribution time (t ₃ ~ t _4), the voltage applied to all the X electrode lines and Y-electrode lines are maintained at a second voltage (V _S), the address electrode lines In the state where the ground voltage V _G is applied, the voltage applied to all M electrode lines is continuously lowered from the second voltage V _S to the ground voltage V _G as the third voltage. Here, it may be nonlinearly lowered as shown by the solid line or linearly lowered as shown by the dashed line. As a result, a weak discharge occurs between the electrodes of all the discharge cells, and a part of the negative wall charges around the M electrode moves around the X and Y electrodes. In addition, more positive wall charges around the address electrodes.

Accordingly, the wall potentials of the X electrode line and the Y electrode line are lower than the wall potential of the address electrode line and higher than the wall potential of the M electrode line. As a result, the addressing voltage V _A -V _G required for the counter discharge between the selected address electrode line and the Y electrode line may be lowered at the subsequent addressing time A. FIG.

5 and 19, at a subsequent addressing time A, a display data signal is applied to an address electrode line and biased with a fifth voltage V _SCAN lower than a second voltage V _S. Scanning pulses of ground voltage V _G are sequentially applied to the line. The display data signal applied to each address electrode line has a positive addressing voltage when the discharge cell is selected and a ground voltage otherwise. Here, the ground voltage is applied to all the X electrode lines, and the second voltage V _S is applied to all the Y electrode lines. Accordingly, in the selected discharge cell, when the display data signal of the positive addressing voltage V _A is applied while the scan pulse of the ground voltage V _G is applied, addressing discharge occurs. Due to this addressing discharge, positive wall charges are formed around the X and M electrodes of the selected discharge cell, and negative wall charges are formed around the Y and address electrodes of the selected discharge cell.

5, 10 and 11, in the following display-hold time S, the second voltage V _S is applied to all M electrode lines and the ground voltage V _G is applied to all address electrode lines. In the applied state, the display-holding pulse of the second voltage V _S is alternately applied to all X electrode lines and all Y electrode lines. This causes a discharge for display-holding in the discharge cell in which the wall charge was formed in the above state at the addressing time A. FIG. As such, long-gap discharge occurs in the X and Y electrode lines after the trigger discharge between the X electrode line and the M electrode in the discharge cell selected by the address discharge.

As described above, the plasma display panel of the present invention can obtain the following effects.

First, since the width of the M electrode disposed between the X and Y electrodes causing the display sustain discharge is limited to a specific value in the terminal region and the connection region, disconnection failure of the electrode can be prevented in advance.

Second, as the width in the terminal region of the M electrode is enlarged, connection with an external terminal is easy.

Third, as addressing is performed while the M electrodes formed between all the X and Y electrodes are scanned, the discharge cells by all the X and Y electrodes can be set.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (8)

A front panel comprising a front substrate, an X and Y electrode formed on an inner surface thereof, an M electrode disposed between the X and Y electrodes, and a front dielectric layer embedded therein; A rear panel formed on a rear substrate facing the front substrate, an rear surface panel formed on an inner surface thereof and having an address electrode disposed in a direction crossing the X and Y electrodes, and a rear dielectric layer embedded therein; A partition wall disposed between the front and rear panels and partitioning a discharge space; It includes; red, green, blue phosphor layer applied in the partition wall, The M electrode may be electrically disposed in a display area of a panel embodying an image, in a terminal area of a panel connected to an external terminal, and in a connection area between the display area and the terminal area. Is connected, The width of the electrode portion disposed in the terminal area is relatively wider than the width of the electrode portion disposed in the connection area. The method of claim 1, The width of the electrode portion disposed in the terminal region and the width of the electrode portion disposed in the connection region satisfy the following equation. Equation 0.42 ≤ W ₁ / W ₂ ≤ 1.0 Here, W ₁ is the width of the M electrode portion disposed in the connection region, and W ₂ is the width of the M electrode portion disposed in the terminal region. The method of claim 2, And the width of the electrode portion disposed in the connection area is substantially the same as the width of the electrode portion disposed in the display area. The method of claim 2, And the M electrode comprises a transparent electrode line and a bus electrode line superimposed on the transparent electrode line. The method of claim 4, wherein And the transparent electrode line is wider than the bus electrode line. The method of claim 2, The M electrode is a plasma display panel, characterized in that consisting of a single layer bus electrode line. The method of claim 2, The M electrode is disposed in the discharge gap between the X and Y electrodes, the width is formed relatively narrower than the width of the X and Y electrodes plasma display panel. The method of claim 2, A trigger discharge voltage is applied between the X and M electrodes, and a sustain discharge voltage is applied between the X and Y electrodes.

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