KR20060038616A - Fabricating method of semicondutor device - Google Patents

Fabricating method of semicondutor device Download PDF

Info

Publication number
KR20060038616A
KR20060038616A KR1020040087712A KR20040087712A KR20060038616A KR 20060038616 A KR20060038616 A KR 20060038616A KR 1020040087712 A KR1020040087712 A KR 1020040087712A KR 20040087712 A KR20040087712 A KR 20040087712A KR 20060038616 A KR20060038616 A KR 20060038616A
Authority
KR
South Korea
Prior art keywords
etching
hard mask
layer
etch
semiconductor device
Prior art date
Application number
KR1020040087712A
Other languages
Korean (ko)
Inventor
김영찬
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020040087712A priority Critical patent/KR20060038616A/en
Publication of KR20060038616A publication Critical patent/KR20060038616A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 식각잔류물에 의한 콘택홀의 낫오픈(Not-Open)을 방지할 수 있는 반도체 소자의 제조 방법에 관한 것으로, 피식각층 상에 하드마스크용 폴리실리콘막을 형성하는 단계; 상기 폴리실리콘막 상에 포토레지스트 패턴을 형성하는 단계;The present invention relates to a method for manufacturing a semiconductor device capable of preventing not-open contact holes due to etching residues, the method comprising: forming a polysilicon film for hard mask on an etching layer; Forming a photoresist pattern on the polysilicon film;

상기 포토레지스트 패턴을 식각마스크로 상기 폴리실리콘막을 식각하여 하드마스크를 형성하는 단계; F(Flourine)를 포함하는 가스를 이용하여 상기 하드마스크의 측면 및 노출되는 상기 피식각층 상에 잔류하는 식각잔류물을 제거하는 단계; 및 적어도 상기 하드마스크를 식각마스크로 상기 피식각층을 식각하여 소정의 패턴을 형성하는 단계를 포함한다.
Etching the polysilicon layer using the photoresist pattern as an etch mask to form a hard mask; Removing etch residues remaining on the side of the hard mask and the exposed etching layer by using a gas including F (Flourine); And etching the etched layer using at least the hard mask as an etch mask to form a predetermined pattern.

식각잔류물, 낫오픈(Not-Open), F(Flourine)Etch residue, Not-Open, F (Flourine)

Description

반도체 소자의 제조 방법{FABRICATING METHOD OF SEMICONDUTOR DEVICE} Manufacturing method of semiconductor device {FABRICATING METHOD OF SEMICONDUTOR DEVICE}             

도 1a 내지 도 1c는 종래기술에 따른 반도체 소자의 제조 방법을 도시한 공정단면도,1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art;

도 2는 하드마스크의 측면에 식각잔류물이 잔류하는 모습을 보여주는 TEM사진도,2 is a TEM photograph showing the appearance of the etching residues on the side of the hard mask,

도 3은 콘택홀이 낫오픈(Not-Open)된 모습을 보여주는 TEM사진도,3 is a TEM photograph showing a contact hole not-open (Not-Open) state,

도 4a 내지 도 4d는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조 방법을 도시한 공정단면도,4A to 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention;

도 5는 하드마스크측면에 존재하는 식각잔류물이 제거된 모습을 보여 주는 TEM사진도,5 is a TEM photograph showing a state in which the etching residue existing on the side of the hard mask is removed;

도 6은 콘택홀이 오픈(Open)된 모습을 보여주는 TEM사진도.
6 is a TEM photograph showing a state in which a contact hole is opened.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

40 : 기판 41 : 도전막40: substrate 41: conductive film

42 : 하드마스크용 절연막 43 : 실리콘산화막42: insulating film for hard mask 43: silicon oxide film

44 : 하드마스크용 폴리실리콘막 45 : 포토레지스트 패턴 44 polysilicon film for hard mask 45 photoresist pattern                 

G4 : 도전패턴
G4: Challenge Pattern

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 식각잔류물에 의한 콘택홀의 낫오픈(Not-Open)을 방지할 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing not-open contact holes due to etching residues.

반도체 소자의 디자인룰이 지속적으로 감소함에 따라 딥콘택(Deep Contact)의 종횡비(Aspect Ratio) 또한 지속적으로 높아져서, 딥콘택(Deep Contact)의 깊이가 30000Å에 이른다. 이에 따른 PR마진부족을 해결하기 위해 하드마스크를 도입하고 있다. As the design rule of the semiconductor device continues to decrease, the aspect ratio of the deep contact also increases continuously, resulting in a depth of the deep contact reaching 30000Å. As a result, a hard mask is introduced to solve the lack of PR margin.

도 1a 내지 도 1c는 종래기술에 따른 반도체 소자의 제조 방법을 도시한 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 1a을 참조하면, 기판(10) 상에 하드마스크용 절연막(12)/도전막(11)의 적층구조로 이루어진 도전패턴(G1)을 형성한다. 이어서, 도전패턴(G1) 상에 실리콘산화막(13)을 형성하고, 실리콘산화막(13)상에 하드마스크용 폴리실리콘막(14)을 형성한다. 이어서, 폴리실리콘막(14) 상에 포토레지스트 패턴(15)을 형성한다.Referring to FIG. 1A, a conductive pattern G1 having a stacked structure of an insulating film 12 for a hard mask / conductive film 11 is formed on a substrate 10. Subsequently, the silicon oxide film 13 is formed on the conductive pattern G1, and the polysilicon film 14 for hard mask is formed on the silicon oxide film 13. Next, the photoresist pattern 15 is formed on the polysilicon film 14.

이어서, 도 1b에 도시된 바와 같이, 포토레지스트 패턴(15)을 식각마스크로 폴리실리콘막(14)을 식각하여 하드마스크(14a)를 형성한다. Subsequently, as shown in FIG. 1B, the polysilicon layer 14 is etched using the photoresist pattern 15 as an etch mask to form a hard mask 14a.                         

도 2는 하드마스크의 측면에 식각잔류물이 잔류하는 모습을 보여주는 TEM사진도이다.2 is a TEM photograph showing the etching residues remaining on the side of the hard mask.

도 2에 A에 도시된 바와 같이, 폴리실리콘막(14)을 식각 후, 폴리머와 같은 식각잔류물(R)이 하드마스크(14a)의 측면 및 노출된 실리콘산화막(13) 상에 존재하게 된다.As shown in FIG. 2A, after etching the polysilicon film 14, an etching residue R such as a polymer is present on the side of the hard mask 14a and on the exposed silicon oxide film 13. .

이어서, 도 1c에 도시된 바와 같이, 포토레지스트 패턴(15)을 제거하고, 하드마스크(14a)를 식각마스크로 실리콘산화막(13)을 식각하여 도전패턴(G1)의 도전막(11)이 노출되도록 콘택홀(C1)을 형성한다.Subsequently, as shown in FIG. 1C, the photoresist pattern 15 is removed, and the silicon oxide film 13 is etched using the hard mask 14a as an etch mask to expose the conductive film 11 of the conductive pattern G1. The contact hole C1 is formed to be possible.

도 3은 콘택홀이 낫오픈(Not-Open)된 모습을 보여주는 TEM사진도이다.3 is a TEM photograph showing a contact hole not-open (Not-Open).

도 3의 B에 도시된 바와 같이, 폴리실리콘막(14)의 식각 후, 남은 잔류물 및 실리콘산화막(13)의 식각 후, 남은 잔류물로 인하여 콘택홀(Con1)이 도전막(11)과 연결되지 못하고 낫오픈(Not-Open)됨을 알 수 있다.As shown in FIG. 3B, after the etching of the polysilicon film 14, the remaining residue and the etching residue of the silicon oxide film 13, the contact hole Con1 is formed by the conductive film 11. You can see that it is not connected and not open.

상기한 종래기술에 의한 반도체 소자의 제조 방법은 하드마스크를 형성하는 공정 후, 하드마스크의 측면 및 노출된 실리콘산화막 상에 남아 있는 식각잔류물이 외부로 완전히 제거되지 못하여 콘택홀 형성 후, 콘택홀의 낫오픈(Not-Open)을 유발하는 문제점이 있었다.
In the method of manufacturing a semiconductor device according to the related art, after the process of forming the hard mask, the etch residues remaining on the side surfaces of the hard mask and the exposed silicon oxide film are not completely removed to the outside and the contact holes are formed. There was a problem that caused Not-Open.

본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 식각잔류물에 의한 콘택홀의 낫오픈(Not-Open)을 방지할 수 있는 반도체 소자의 제조 방법을 제공 하는데 그 목적이 있다.
An object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing the not-open of a contact hole due to an etching residue.

상기한 목적을 달성하기 위해 본 발명은 피식각층 상에 하드마스크용 폴리실리콘막을 형성하는 단계; 상기 폴리실리콘막 상에 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 식각마스크로 상기 폴리실리콘막을 식각하여 하드마스크를 형성하는 단계; F(Flourine)를 포함하는 가스를 이용하여 상기 하드마스크의 측면 및 노출되는 상기 피식각층 상에 잔류하는 식각잔류물을 제거하는 단계; 및 적어도 상기 하드마스크를 식각마스크로 상기 피식각층을 식각하여 소정의 패턴을 형성하는 단계를 포함하는 반도체 소자의 제조 방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of forming a polysilicon film for a hard mask on the etching layer; Forming a photoresist pattern on the polysilicon film; Etching the polysilicon layer using the photoresist pattern as an etch mask to form a hard mask; Removing etch residues remaining on the side of the hard mask and the exposed etching layer by using a gas including F (Flourine); And etching the etched layer using at least the hard mask as an etch mask to form a predetermined pattern.

상기 식각잔류물을 제거하는 단계에서, 상기 피식각층의 일부를 식각하여 패턴형성 영역을 정의한다.
In the removing of the etching residue, a portion of the etching layer is etched to define a pattern formation region.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 4a 내지 도 4d는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조 방법을 도시한 공정단면도이다.4A through 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 4a을 참조하면, 기판(40) 상에 하드마스크용 절연막(42)/도전막(41)의 적층구조로 이루어진 도전패턴(G1)을 형성한다. 이어서, 도전패턴(G1) 상에 실리콘산 화막(43)을 형성하고, 실리콘산화막(43) 상에 하드마스크용 폴리실리콘막(44)을 형성한다. 이어서, 폴리실리콘막(44) 상에 포토레지스트 패턴(45)을 형성한다.Referring to FIG. 4A, a conductive pattern G1 having a laminated structure of a hard mask insulating film 42 and a conductive film 41 is formed on the substrate 40. Next, the silicon oxide film 43 is formed on the conductive pattern G1, and the polysilicon film 44 for hard mask is formed on the silicon oxide film 43. Next, the photoresist pattern 45 is formed on the polysilicon film 44.

이어서, 도 4b에 도시된 바와 같이, 포토레지스트 패턴(45)을 식각마스크로 폴리실리콘막(44)을 식각하여 하드마스크(44a)를 형성한다. 4B, the polysilicon layer 44 is etched using the photoresist pattern 45 as an etch mask to form a hard mask 44a.

이때, 도 2에 A에 도시된 바와 같이, 폴리실리콘막(44)을 식각 후, 폴리머와 같은 식각잔류물(R)이 하드마스크(44a)의 측면 및 노출된 실리콘산화막(43) 상에 존재하게 된다.In this case, as shown in FIG. 2A, after etching the polysilicon film 44, an etching residue R such as a polymer is present on the side of the hard mask 44a and on the exposed silicon oxide film 43. Done.

이어서, 도 4c에 도시된 바와 같이, F(Flourine)를 포함하는 가스인 CF4가스를 이용하여 하드마스크(44a)의 측면 및 노출된 실리콘산화막(43) 상에 존재하는 식각잔류물(R)을 제거한다. 여기서, 식각잔류물(R)을 제거는 CF4가스에 Ar 및 O2가스를 더 포함하는 가스를 이용하여, 8초 내지 20초 동안 실시할 수 있다.Subsequently, as shown in FIG. 4C, the etching residue R existing on the side of the hard mask 44a and the exposed silicon oxide layer 43 using CF 4 gas, which is a gas including F (Flourine), is used. Remove it. Here, the removal of the etching residue (R) may be performed for 8 seconds to 20 seconds using a gas further comprising Ar and O 2 gas in CF 4 gas.

또한, 식각잔류물(R)을 제거공정에서 노출된 실리콘산화막(43)의 일부가 함께 제거되어 콘택홀 형성영역(Con2)을 정의한다. In addition, a portion of the silicon oxide film 43 exposed during the removal process of the etch residue R is removed together to define the contact hole forming region Con2.

도 5는 하드마스크측면에 존재하는 식각잔류물이 제거된 모습을 보여 주는 TEM사진도이다.5 is a TEM photograph showing a state in which the etching residues present on the side of the hard mask are removed.

도 5의 C에 도시된 바와 같이, 하드마스크(44a)의 측면 및 노출된 실리콘산화막(43) 상에 존재하는 식각잔류물(R)을 제거함과 동시에 노출된 실리콘산화막(43)을 식각하여 종래기술에 의해 제조되는 콘택홀 보다 콘택홀의 형성영역을 증가시켜 콘택홀의 낫오픈(Not-Open)을 방지할 수 있다. As shown in FIG. 5C, the exposed silicon oxide film 43 is etched at the same time as the etching residue R existing on the side of the hard mask 44a and the exposed silicon oxide film 43 is removed. It is possible to prevent the not-open of the contact hole by increasing the forming area of the contact hole than the contact hole manufactured by the technology.                     

이어서, 도 4d에 도시된 바와 같이, 포토레지스트 패턴(45)을 제거하고, 하드마스크(44a)를 식각마스크로 실리콘산화막(43)을 식각하여 도전패턴(G4)의 도전막(41)이 노출되도록 콘택홀(Con3)을 형성한다.Subsequently, as shown in FIG. 4D, the photoresist pattern 45 is removed, and the silicon oxide film 43 is etched using the hard mask 44a as an etch mask to expose the conductive film 41 of the conductive pattern G4. The contact hole Con3 is formed as much as possible.

도 6은 콘택홀이 오픈(Open)된 모습을 보여주는 TEM사진도이다.6 is a TEM photograph showing a state in which a contact hole is opened.

도 6의 D에 도시된 바와 같이, 식각잔류물이 완전히 제거되어 콘택홀과 도전패턴과 접합하는 영역이 완전히 오픈(OPEN)됨을 알수 있다.As shown in FIG. 6D, it can be seen that the etching residue is completely removed to completely open the contact area between the contact hole and the conductive pattern.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의해야 한다. 또한, 본 발명의 기술 분야의 통상의 지식을 가진자라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명에 의하면, F(Flourine)를 포함하는 가스를 이용하여 하드마스크형성 후에 발생하는 식각잔류물을 제거함과 동시에 콘택홀의 형성영역을 증가시킴으로써, 콘택홀의 낫오픈(Not-Open)을 방지할 수 있다.According to the present invention described above, by using a gas containing F (Flourine) to remove the etching residues generated after the formation of the hard mask and at the same time increasing the contact hole forming area, to prevent the (Not-Open) of the contact hole can do.

Claims (6)

피식각층 상에 하드마스크용 폴리실리콘막을 형성하는 단계;Forming a polysilicon film for a hard mask on the etched layer; 상기 폴리실리콘막 상에 포토레지스트 패턴을 형성하는 단계;Forming a photoresist pattern on the polysilicon film; 상기 포토레지스트 패턴을 식각마스크로 상기 폴리실리콘막을 식각하여 하드마스크를 형성하는 단계; Etching the polysilicon layer using the photoresist pattern as an etch mask to form a hard mask; F(Flourine)를 포함하는 가스를 이용하여 상기 하드마스크의 측면 및 노출되는 상기 피식각층 상에 잔류하는 식각잔류물을 제거하는 단계; 및Removing etch residues remaining on the side of the hard mask and the exposed etching layer by using a gas including F (Flourine); And 적어도 상기 하드마스크를 식각마스크로 상기 피식각층을 식각하여 소정의 패턴을 형성하는 단계Etching the etched layer using at least the hard mask as an etch mask to form a predetermined pattern 를 포함하는 반도체 소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 식각잔류물을 제거하는 단계에서, 상기 피식각층의 일부를 식각하여 패턴형성 영역을 정의하는 반도체 소자의 제조 방법.And removing a portion of the etch residue to form a pattern formation region by etching a portion of the layer to be etched. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 피식각층은 실리콘산화막을 포함하는 반도체 소자의 제조 방법.The etching layer is a semiconductor device manufacturing method comprising a silicon oxide film. 제3항에 있어서,The method of claim 3, 상기 소정의 패턴은 콘택홀 패턴인 반도체 소자의 제조 방법.And the predetermined pattern is a contact hole pattern. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 F(Flourine)를 포함하는 가스는 CF4가스인 반도체 소자의 제조 방법.The gas containing F (Flourine) is CF 4 gas manufacturing method of a semiconductor device. 제5항에 있어서,The method of claim 5, 상기 식각잔류물을 제거하는 단계에서, 상기 F(Flourine)를 포함하는 가스에 Ar 및 O2가스를 더 포함하는 가스를 이용하여, 8초 내지 20초 동안 실시하는 반도체 소자의 제조 방법.In the step of removing the etch residue, using a gas further comprising Ar and O 2 gas in the gas containing F (Flourine), the method of manufacturing a semiconductor device for 8 seconds to 20 seconds.
KR1020040087712A 2004-10-30 2004-10-30 Fabricating method of semicondutor device KR20060038616A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020040087712A KR20060038616A (en) 2004-10-30 2004-10-30 Fabricating method of semicondutor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020040087712A KR20060038616A (en) 2004-10-30 2004-10-30 Fabricating method of semicondutor device

Publications (1)

Publication Number Publication Date
KR20060038616A true KR20060038616A (en) 2006-05-04

Family

ID=37146090

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020040087712A KR20060038616A (en) 2004-10-30 2004-10-30 Fabricating method of semicondutor device

Country Status (1)

Country Link
KR (1) KR20060038616A (en)

Similar Documents

Publication Publication Date Title
TWI261864B (en) Recess gate and method for fabricating semiconductor device with the same
JP3946724B2 (en) Manufacturing method of semiconductor device
KR100555366B1 (en) Polysilicon etching method and semiconductor memory manufacturing method
KR100714287B1 (en) Method for forming a pattern of semiconductor device
KR100669560B1 (en) Method for forming interconnect of semiconductor device
JP2007013104A (en) Semiconductor device manufacturing method
KR100652795B1 (en) Method for forming storagenode contact in semiconductor device using metal hardmask contain nitrogen component
JP2005191567A (en) Contact formation method of semiconductor device
KR20060038616A (en) Fabricating method of semicondutor device
JP2006128613A (en) Manufacture of semiconductor element
KR20080089029A (en) Method for forming contact hole in semiconductor device
JP2007135129A (en) Manufacturing method of piezoelectric vibrating piece and piezoelectric vibrating piece manufactured by method
KR20080060349A (en) Method for forming a fine pattern in semiconductor device
KR100373363B1 (en) Method of forming contact hole of semiconductor device
KR100265340B1 (en) Method of fabricating semiconductor device
KR101051949B1 (en) Pattern Forming Method of Semiconductor Device
KR100425935B1 (en) Method for forming a contact hole in a semiconductor device
KR100434312B1 (en) Method for making contact hole in semiconductor device
KR100548562B1 (en) method for forming storge node plug
KR100886641B1 (en) Method for fabricating capacitor in semiconductor device
KR20080084280A (en) Forming method for gate of semiconductor device
KR20090030507A (en) Method for fabricating semiconductor device
KR100587607B1 (en) Method for manufacturing semiconductor device
KR100935197B1 (en) Method for forming of semiconductor device
KR100396697B1 (en) Method for Fabricating of Semiconductor Device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination