KR20060038592A - Method for fabrication of cell contact plug in semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can increase the process margin when forming the cell contact plug and ensure the stability of the process, the present invention comprises the steps of forming a plurality of gate electrodes on the substrate; Forming insulating spacers on sidewalls of the plurality of gate electrodes; Forming a conductive film for a plug on the entire surface including the gate electrode; Performing a planarization process on a target to which the gate electrode is exposed; And selectively removing the plug conductive film in which the cell contact is not made from the planarized plug conductive film.

Cell contact plugs, chemical mechanical polishing (CMP), damascene, plug conductive films, slurries.

Description

Method for forming cell contact plug of semiconductor device {METHOD FOR FABRICATION OF CELL CONTACT PLUG IN SEMICONDUCTOR DEVICE}             

1 is a flow chart schematically illustrating a part of a semiconductor device manufacturing process including cell contact formation according to the prior art.

2 is a plan view illustrating a semiconductor device in which a gate electrode is formed according to the related art.

3 is a plan view illustrating a semiconductor device in which contact holes for cell contacts are formed according to the related art.

4A to 4G are cross-sectional views illustrating a semiconductor device manufacturing process including forming a cell contact plug according to the prior art.

5 is a flow chart schematically illustrating a part of a semiconductor device manufacturing process including cell contact formation according to the present invention.

6 is a plan view illustrating a semiconductor device in which a gate electrode is formed in accordance with an embodiment of the present invention.

FIG. 7 is a plan view illustrating a semiconductor device in which an isolated cell contact plug is formed without an interlayer dielectric layer in accordance with an embodiment of the present invention. FIG.                 

8A through 8F are cross-sectional views illustrating a semiconductor device manufacturing process including forming a cell contact plug according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

800 substrate 801 gate conductive film

802: gate hard mask 803: spacer

804c: conductive film for isolated plug

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of simplifying the process and simplifying the process.

The semiconductor device includes a plurality of unit devices therein. As semiconductor devices are highly integrated, devices must be formed at a high density on a constant cell area, thereby decreasing the size of unit devices.

In particular, as a design rule decreases in a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), the size of semiconductor devices formed in a cell is gradually decreasing.

In fact, in recent years, the minimum line width of a semiconductor DRAM device is formed to 0.1 μm or less, and even 80 nm or less is required. Therefore, many difficulties arise in the manufacturing process of the semiconductor elements forming the cell.

Meanwhile, as the high integration of semiconductor devices is accelerated, various elements of the semiconductor devices have a stacked structure, and thus, a contact plug (or pad) concept has been introduced.

In forming such a contact plug, techniques are used to increase the contact area with a minimum area at the bottom and to increase the process margin for subsequent processes at the top.

1 is a flowchart schematically illustrating a part of a semiconductor device manufacturing process including forming a cell contact according to the prior art, and looks at a conventional semiconductor device manufacturing process with reference to this.

After forming a field oxide film on the substrate to define a field region and an active region, forming a well, and performing channel ion implantation, a plurality of gate electrodes are formed on the substrate (S101). Impurity ion implantation is performed in the active region of the substrate aligned with the side of the gate electrode to form a source / drain junction.

In this process, a gate spacer forming process and a lightly doped drain (LDD) ion implantation process are performed.

A first interlayer insulating film is formed on the entire surface where the gate electrode is formed (S102). In order to prevent defects during the mask process, the upper portion of the first interlayer insulating film is planarized.

The first interlayer dielectric layer is selectively etched to form a contact hole exposing the source / drain junction between the gate electrodes (S103).

In this case, an etching process using a self alignment contact (SAC) method is used to prevent contact open failure due to an increase in an aspect ratio due to an increase in a step difference of a gate electrode and a decrease in space between the gate electrodes. .

The plug material is deposited to be in contact with the source / drain junction exposed through the contact hole (S104). As the plug material, a polysilicon film is mainly used.

A plurality of cell contact plugs are formed by isolating the deposited plug material by applying etch back and chemical mechanical polishing (CMP) processes alone or in combination (S105).

A second interlayer insulating film is formed on the entire surface where the cell contact plug is formed (S106).

Subsequently, a photolithography process is performed to form a mask pattern, and the second interlayer insulating layer is etched using the mask pattern to expose a portion of the cell contact plug to which the bit line contact is to be made, and then form a bit line (S107).

Hereinafter, a conventional cell contact plug forming process will be described with reference to an actual process diagram.

2 is a plan view illustrating a semiconductor device having a gate electrode according to the related art.

Referring to FIG. 2, the gate electrodes G1 to G5 of the line type spaced apart at regular intervals are formed in the cell region, and the gate electrode G6 is formed in the peripheral region.

3 is a plan view illustrating a semiconductor device in which contact holes for cell contacts are formed according to the related art.

Referring to FIG. 3, a plurality of gate electrodes G1 to G6 are formed in a cell region and a peripheral region.

In the cell region, a mask pattern M is formed, and the first interlayer insulating film is etched through a selective etching process using the mask pattern M as a mask to expose source / drain junctions between the gate electrodes G1 to G5. Contact holes C / T are formed.

4A to 4G are cross-sectional views illustrating a semiconductor device manufacturing process including forming a cell contact plug according to the prior art.

As shown in FIG. 4A, a first interlayer insulating film 404 is formed on a cross section taken along the a-a 'direction of the plan view of FIG. 2.

The gate electrodes G1 to G6 include a stacked structure of a gate hard mask 402 / gate conductive film 401 / gate insulating film (not shown) and spacers 403 on sidewalls thereof.

The step difference of the first interlayer insulating film 404 occurs between the cell region and the peripheral region due to the difference in the pattern density of the gate electrodes G1 to G6. The planarization process is performed to secure process margins in subsequent mask processes and to reduce such steps.

Even after the planarization process, a first interlayer insulating film 404 having a thickness of 't1' remains on the gate electrodes G1 to G5 in the cell region, and a first interlayer insulating film having a thickness of 't2' on the gate electrode G6 in the peripheral region. 404 remains.

As shown in FIG. 4B, a photoresist pattern 405, which is a mask for cell contact, is formed on the first interlayer insulating layer 404.                         

Prior to performing the SAC etching process, the thickness of the gate hard mask 402 is 't3'.

As shown in FIG. 4C, the first interlayer insulating film 404 is etched using the photoresist pattern 405 as an etch mask, so that the source / gate between G1 and G2, G2 and G3, and G3 and G4 in the cell region. A contact hole 406 is formed to expose the drain junction.

At this time, the SAC etching process is applied, and in the process, the gate hard mask 402 is partially lost, leaving a thickness of 't4'.

Subsequently, a photoresist strip process is performed to remove the photoresist pattern 405, and then a cleaning process is performed to remove the etching residues.

FIG. 4C corresponds to a cross-sectional view taken along line b-b 'of FIG. 3, and the region P of FIG. 3 shows a portion covered with the first interlayer insulating film 404 in FIG. 4C, and the region Q of FIG. 3 is the first in FIG. 4C. The interlayer insulating film 404 is etched to show the contact hole 406.

As shown in FIG. 4D, a plug forming conductive film 407a is formed on the entire surface where the contact hole 406 is formed. As the conductive film 407a, a polysilicon film is used.

The conductive film 407a is deposited by a thickness of 't5', and the P and Q regions of FIG. 3 have a step of 't6' due to the topology formed by the contact hole 406.

In the planarization process for plug isolation, the conductive layer 407a, the first interlayer dielectric layer 404, and the gate hard mask 402 should be removed to a thickness greater than t7. On the other hand, the thickness of the conductive film 407a as much as 't5' is determined in consideration of the step generated before the deposition of the conductive film 407a.

As shown in FIG. 4E, an etchback process is performed before the planarization process through CMP to remove the conductive film 407a on the first interlayer insulating film 404.

As shown in FIG. 4F, a planarization process using CMP is performed as a target to which the gate hard mask 402 is exposed in the cell region to form a plurality of isolated cell contact plugs 407c.

During the CMP process, the polishing is performed on the gate hard mask 402 in the peripheral region without the conductive film 407c.

On the other hand, in the CMP process, the periphery of the cell region and the peripheral region, the peripheral speed due to the difference in the polishing speed between the gate hard mask 402 and the conductive film 407b and the first interlayer insulating film 404 during the plug 407c isolation. The margin of the gate hard mask 402 in the region is insufficient.

That is, the polishing rate of the first interlayer insulating film 404 in the peripheral region is high, so that the first interlayer insulating film 404 is easily removed, and further, the lower gate hard mask 402 is exposed and polished early, so that The thickness 't9' of the gate hard mask 402 is lower than the thickness 't8' of the gate hard mask 402 of the cell region.

Lack of margin of the gate hard mask 402 increases the likelihood of misalignment in a subsequent process, resulting in a bridge between the gate electrodes G1-G5 and the storage node contact, or leakage current. Increases the failing of the semiconductor device.

As shown in FIG. 4G, a second interlayer insulating film 408 is deposited on the entire surface where the cell contact plug 407c is formed to insulate the bit line, and then a planarization process such as CMP is performed to perform gate electrodes G1 to G6. The thickness of the 't10' is left on the second interlayer insulating film 408.

In a subsequent process, a bit line contact process is performed to expose a portion of the cell contact plug 407c to which a bit line contact is to be made.

The following problem occurs in the conventional cell contact plug forming process as described above.

1) When depositing the conductive film for the plug, the thickness of the first interlayer insulating film 404 on the gate electrodes G1 to G5 should be taken into consideration as 't1' shown in FIG. 4A. Increases.

2) As shown in FIG. 4F, in the CMP process for plug isolation, excessive or underpolishing due to a difference in polishing rate between the conductive film, the gate hard mask, and the first interlayer insulating film and the resulting plug seam Problems, such as dishing (Dishing) occurs.

3) Due to the increase in the aspect ratio due to the increase in the thickness of the gate electrodes G1 to G6 and the decrease in the space, the burden of the SAC etching process is large when the contact hole 406 of FIG. 4C is formed, and SAC fail frequently occurs.

The present invention has been proposed to solve the above problems of the prior art, an object of the present invention is to provide a method for manufacturing a semiconductor device that can increase the process margin when forming the cell contact plug and ensure the stability of the process.

In order to achieve the above object, the present invention comprises the steps of forming a plurality of gate electrodes on the substrate; Forming insulating spacers on sidewalls of the plurality of gate electrodes; Forming a conductive film for a plug on the entire surface including the gate electrode; Performing a planarization process on a target to which the gate electrode is exposed; And selectively removing the plug conductive film in which the cell contact is not made from the planarized plug conductive film.

The present invention does not deposit a first interlayer insulating film after forming a gate electrode, and immediately after the plug conductive film is deposited, performs an isolation process, deposits a first interlayer insulating film, and selectively removes the first interlayer insulating film, and then contacts the cell. Form a plug.

As a result, targets can be reduced when depositing a conductive film for a plug, a SAC etching process can be omitted, and various problems generated during a CMP process for plug isolation can be solved.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.                     

FIG. 5 is a flowchart schematically illustrating a part of a semiconductor device manufacturing process including cell contact formation according to the present invention, and looks at the semiconductor device manufacturing process of the present invention with reference to the flowchart.

After forming a field oxide film on the substrate to define a field region and an active region, forming a well, and performing channel ion implantation, a plurality of gate electrodes are formed on the substrate (S501). Impurity ion implantation is performed in the active region of the substrate aligned with the side of the gate electrode to form a source / drain junction.

In this process, a gate spacer forming process and an LDD ion implantation process are performed.

A plug material, that is, a plug forming conductive film is deposited on the entire surface where the gate electrode is formed (S502).

In general, an interlayer insulating film is deposited, but in the present invention, a plug conductive film is first deposited to fill all gate electrodes. The gate electrode and the plug conductive film are insulated from each other by a spacer of the gate sidewall. As the plug material, a polysilicon film is mainly used.

The etch back and the CMP process are applied alone or in combination to expose the gate hard mask so that the plug conductive films are isolated from each other by the gate electrode (S503).

The plug conductive film in a region other than the cell contact plug of the plug conductive film is removed, and the interlayer insulating film is filled in the removed portion (S504).

That is, by forming a photoresist pattern on the entire surface where the plug conductive film is formed, by removing the plug conductive film in a region other than the cell contact plug with the photoresist pattern as an etch mask, cell contact plugs isolated from each other without an insulating region are formed. do.

At this time, the existing cell contact mask can be used as it is. For this purpose, a negative type photoresist is used instead of a positive type photoresist.

Therefore, since the portion not exposed using the existing mask for cell contact is dissolved and removed through the developing process, a desired photoresist pattern can be formed.

After removing the photoresist pattern, a cleaning process is performed to remove the etch residue.

An interlayer insulating film is formed on the entire surface where the cell contact plug is formed (S505).

Subsequently, a photolithography process is performed to form a mask pattern, and an interlayer insulating layer is etched using the mask pattern to expose a portion of the cell contact plug to which a bit line contact is to be made, and then a bit line is formed (S506).

Hereinafter, a cell contact plug forming process according to an exemplary embodiment of the present invention will be described with reference to the actual process diagram.

6 is a plan view illustrating a semiconductor device in which a gate electrode is formed in accordance with an embodiment of the present invention.

Referring to FIG. 6, line-type gate electrodes G601 to G605 spaced at regular intervals are formed in the cell region, and gate electrodes G606 are formed in the peripheral region.                     

FIG. 7 is a plan view illustrating a semiconductor device in which an isolated cell contact plug is formed without an interlayer dielectric layer according to an exemplary embodiment of the present invention.

Referring to FIG. 7, a plurality of gate electrodes G601 to G606 are formed in a cell region and a peripheral region.

In the cell region, isolated cell contact plugs (Plug) are formed between the gate electrodes G601 to G605, and the cell contact plugs are isolated from each other by the open area (Open).

8A through 8F are cross-sectional views illustrating a semiconductor device manufacturing process including forming a cell contact plug according to an embodiment of the present invention.

As shown in FIG. 8A, the plug conductive film 804a is formed on the cross section taken along the c-c 'direction of the plan view of FIG. 6.

The gate electrodes G1 to G6 include a stacked structure of a gate hard mask 802 / gate conductive film 801 / gate insulating film (not shown) and spacers 803 on sidewalls thereof.

The gate insulating film uses a conventional oxide film-based insulating film such as a silicon oxide film or an aluminum oxide film.

The gate conductive film usually uses polysilicon doped with impurities, W, WN, WSi _x , TiSi _x , or the like, or a combination thereof.

The gate hard mask is used to protect the gate conductive layer from being attacked in a process of forming an open portion for subsequent contact formation, for example, in an SAC etching process, and any insulating layer having an interlayer dielectric layer and an etching selectivity may be used.

Representative examples thereof include a silicon oxide film, a silicon oxynitride film, and a silicon nitride film.

An impurity diffusion region (not shown) such as a source / drain junction is formed in the substrate 800 between the gate electrodes G601 to G606.

In the case of patterning the gate electrodes G601 to G606, plasma etching may be performed using a chlorine gas such as Cl ₂ or CCl ₄ so as to have a high selectivity with a gate insulating film that is an oxide film.

The spacer 803 is formed by depositing an insulating film for a spacer along the profile in which the gate electrodes G601 to G606 are formed, and then performing an etch back process.

The spacer 803 includes a single structure or a double structure of a nitride film or a multiple structure in which a nitride film and an oxide film are combined.

The plug conductive film 804a is deposited on the entire surface where the gate electrodes G601 to G606 are formed.

In FIG. 8A, the plug conductive film 804a is deposited by the thickness of 't11'.

In the present invention, unlike the prior art, since the plug conductive film 804a is deposited after the formation of the gate electrodes G601 to G606, the deposition thickness thereof can be reduced as compared with the prior art. That is, in the conventional case, the contact hole must be buried, and in this case, the thickness of the interlayer insulating film must be taken into consideration, so that the deposition thickness thereof should be larger than 't11'.

As the plug conductive film 804a, a polysilicon film is mainly used. When depositing a polysilicon film, a source such as SiH ₄ or Si ₂ H ₆ is used.

As shown in FIG. 8B, the planarization process is performed to expose the gate hard mask 802 so that the plug conductive films 804b are isolated from each other by the gate electrodes G601 to G606.

As the planarization process, the etch back and the CMP process may be applied alone or in combination, but it is preferable to apply the CMP process.

By using a slurry whose polishing rate of the polysilicon film used as the plug conductive film 804b for the CMP process is higher than the polishing rate of the nitride film used as the gate hard mask 802 (at least 10 or more), the conductivity for the plug is used. It is possible to prevent dishing of the plug conductive film 804b and corrosion of the gate hard mask 802 generated after the film 804b isolation.

The slurry may be one having a polishing selectivity of 2: 1 to 100: 1 between the polysilicon film and the nitride film, but it is preferable to use one having from 10: 1 to 50: 1.

As such, when a highly selective slurry having a high polishing selectivity with respect to the polysilicon film and the nitride film is used, the nitride film functions as an automatic stop film, thereby increasing flatness and ultimately reducing fail in a subsequent process to yield resistance. There is an advantage that can be prevented.                     

Even if the slurry having the automatic stop function is not used, the part where the cell contact plug will not be formed is removed in a subsequent etching process, so even if a step occurs in the plug conductive film 804b in the peripheral region, a process problem is caused. There is no. That is, even if the thickness of the final plug conductive film 804b in the peripheral region after the CMP process is adjusted by 't12' smaller than 't11', which is the thickness before the CMP, no problem occurs in the subsequent process.

The wastewater (pH) of the slurry may be 2 to 12, and it is preferable to use the wastewater having 5 to 11 wastewater.

In addition, it is preferable to use a slurry to which silica or alumina abrasive with a size of 50 nm to 300 nm is added.

The use of a slurry can add tetramers to the slurry in a manner that increases the polishing rate of the polysilicon. Examples of the oxidant used at this time are 0.01w% to 10w% based on the total amount of the slurry by combining one or more water-soluble organic or inorganic oxidants including hydrogen peroxide.

In order to match the wastewater (pH) of the slurry, inorganic acids such as HCl or HNO ₃ and aqueous ammonia or inorganic salts, as well as acetic acid, citric acid, tartaric acid and succinic acid , Malic acic, maleic acid, maleic acid, fumaric acid, manolic acid, maniclic acid, glycolic acid, oxalic acid, benzoic acid, etc. All the same organic acids and salts thereof, and all organic salts such as monoethanol amine or triethanol amine can be used.

If acetic acid is used in 0.01w% -10w% of the total amount of slurry, the wastewater level (pH) can be set to "5". If monoethanol amine is used in 0.01w% -10w% of the total amount of slurry, wastewater (pH) is used. ) Can be set to "9".

Organic acids used as wastewater (pH) regulators have affinity for the nitride film and thus reduce the polishing rate. In the CMP process, hard pads are used.

As shown in FIG. 8C, the photoresist pattern 805 is formed on the entire surface of the plug conductive film 804b.

At this time, the existing cell contact mask can be used as it is. For this purpose, a negative type photoresist is used instead of a positive type photoresist.

Accordingly, since the portion not exposed using the existing cell contact mask is dissolved and removed through the developing process, the desired photoresist pattern 805 may be formed.

As shown in FIG. 8D, the cell contact plug 804c is isolated from each other without the insulating region by removing the plug conductive film 804b other than the region where the cell contact plug is formed using the photoresist pattern 805 as an etch mask. To form.

FIG. 8D corresponds to a cross-sectional view taken along the line d-d 'of FIG. 7, wherein the R region of FIG. 7 is an open region 806 in FIG. 8D, and the S region of FIG. 7 is an isolated cell contact without an interlayer insulating film in FIG. 8D. The plug 804c is shown.

In this case, a dry etching method is used, and chlorine gas such as Cl ₂ or CCl ₄ is used to obtain a high selectivity between the nitride film and the polysilicon film.

In this case, the SAC etching process may be applied to increase the etching selectivity.

The difference between the thickness 't13' of the gate hard mask 802 in the cell region and the thickness 't14' of the gate hard mask 802 in the peripheral region hardly occurs.

As a result of the above process, the loss of the gate hard mask 802 can be reduced as compared with the conventional cell contact plug 804c after isolation.

Therefore, if the loss of the gate hard mask 802 is reduced as much as possible, the SAC fail may be reduced by increasing the process margin in forming the subsequent bit line and forming the storage node contact.

In addition, since the loss of the gate hard mask 802 is minimized, the thickness of the gate hard mask 802 that is initially deposited may be reduced.

As shown in FIG. 8E, an interlayer insulating film 807 is formed on the entire surface where the cell contact plug 804c is formed.

The interlayer insulating film 807 is between the gate electrodes G601 to G606, between the gate electrodes G601 to G605 and the cell contact plug 804c, between the cell contact plug 804c, and between the gate electrodes G601 to G606 and the bit line. Insulation between the bit line and the bit line and between the bit line and the cell contact plug 804c is simultaneously achieved.

In the related art, after the gate electrodes G601 to G606 are formed, the first interlayer insulating film is deposited, and after the cell contact plug 804c is formed, the second interlayer insulating film is deposited again. However, in the present invention, the two interlayer insulating films are deposited once. 807) by deposition.                     

The interlayer insulating film 807 is an oxide film doped with impurities such as a BPSG (Boro-Phospho-Silicate-Glass) film, a PSG (Phospho-Silicate-Glass) film, or hydrogen peroxide (H ₂ O ₂ ) and silane (SiH) having excellent buried characteristics. ₄ ) APL (Advanced Planarization Layer) film having a fluidity by depositing by Low Pressure Chemical Vapor Deposition (LPCVD) method using as a reaction source. SiH ₄ , SiHa (CH ₃ ) b (0 ≦ a ≦ 4, 0 ≦ b ≦ 4) and N ₂ , as the source, including an oxide film deposited using atomic layer deposition (ALD). An oxide film deposited using a high density plasma method using N ₂ O, NH ₃ , O ₂ , O ₃ , Ar, He, NF ₃ , or the like can be used.

In the case of using the oxide film deposited by the high-density plasma method as the interlayer insulating film 807, a mixed gas atmosphere including H ₂ , O ₂ , N ₂ , O ₃ , N ₂ O, or H ₂ / O _2, etc. after film deposition is used. It is preferable to carry out for 5 minutes or more at the temperature of 500 degreeC-1200 degreeC. In the case of using the Rapid Thermal Process method, the film quality is increased by performing at least 600 seconds at a temperature of 600 ° C. or higher.

As shown in FIG. 8F, the planarization process is performed to leave the thickness of the interlayer insulating film 807 at the top of the gate electrodes G601 to G606 to be 't10'.

In the planarization, a CMP process is used.

As the design rule of the semiconductor device decreases, when the subsequent process is performed without the complete planarization of the interlayer insulating film 807, the margin of focus (hereinafter referred to as DOF) during the exposure operation and the lack of margin during the etching process Because of lack of margin, bridge generation or leakage current increases, so planarization process is necessary.

The present invention has the advantage of performing only one deposition of the interlayer insulating film 807 and only one CMP process, unlike the prior art in which the CMP process is performed twice by depositing the interlayer insulating film twice.

As such, reducing the number of CMP processes for planarization has an advantage in terms of uniformity generated during the CMP process. That is, the final nonuniformity is increased by adding the nonuniformity generated by two subsequent CMP processes to the polishing nonuniformity caused by one CMP, while the nonuniformity can be further reduced by introducing only one CMP process and performing planarization.

Meanwhile, in the present invention, when the interlayer insulating film 807 is planarized using a CMP process, a slurry in which a silica abrasive and a ceria abrasive are mixed to reduce the step difference between the cell region and the peripheral region is used.

The slurry in which the silica abrasive and the ceria abrasive are mixed at a ratio of 0.1: 99.9 to 99.9: 1 is preferably 1: 9 to 9: 1.

Silica abrasives preferentially remove high step areas prior to CMP, and ceria abrasives, which form complexes with polymers when the high steps are removed by silica abrasives, exist in the peripheral area with low step levels. The area plays a role of controlling so that grinding is not good.

The ceria abrasive forms a complex of 'ceria abrasive-polymer' having a diameter of 50 nm to 5000 nm, preferably 200 nm to 1000 nm in solution by adding an anionic polymer compound.

The complex of 'ceria abrasive-polymer' is used to polish the polishing target film by, for example, removing the step before CMP when forming the field oxide film and causing strong ionic interaction with the oxide film in the field oxide film area when the pad nitride film is exposed. Make the speed noticeably slower. In other words, it functions as an auto stop CMP.

The polymer forming the complex of 'ceria abrasive-polymer' is a polymer having a carboxyl group, and a polymer having an anionic R functional group (all high molecular compounds having functional groups such as -NH ₂ , -COHN ₂ , and NO ₂ ) in addition to the carboxyl group Can also be used. The polymer used at this time has a molecular weight of several hundred thousand to millions, and includes all commercially available anionic polymer compounds.

For example, NOVEON Co., Ltd. has a trade name of "CARBOPOL", typically "CARBOPOL940" having a molecular weight of 4 million or "CARBOPOL941" having a molecular weight of about 1.25 million.

As the polymer, polyacrylic acid and its derivatives may be used alone or in combination, and include polymers in the form of acid or salt.

In order to activate a polymer, it is preferable to neutralize using a basic compound. At this time, the basic compound used may be a hydrate of an alkali metal such as potassium hydroxide, ammonium hydroxide, monoethanol amine, diethanol amine, triethanol amine ( Organic series such as Tri Ethanol Amine).                     

The content of the polymer used is adjusted to be 0.01w% to 5.0w%, preferably 0.05 to 1.5w% of the total weight of the slurry.

In the CMP process, the polishing pressure is maintained at 1 psi to 10 psi and the polishing table speed is about 10 rpm to 1000 rpm.

The total concentration of the silica abrasive and the ceria abrasive is maintained at 1w% to 50w%, preferably 5w% to 20w% of the total slurry concentration.

As the silica abrasive, a colloidal form or a fumed form having a size of about 10 nm to 5000 nm, preferably about 50 nm to 1000 nm is used.

Instead of silica abrasives, alumina (Al ₂ O ₃ ), zirconia (ZrO ₂ ), MgO ₂ , TiO ₂ , Fe ₃ O ₄ , HfO ₂ , and the like can be used. This is possible because the interlayer insulating film 807 is an oxide film series.

In the CMP process for removing the step, the slurry has a wastewater (pH) of 4 to 10, preferably 5 to 8, and a pH lowering agent such as a pH reducing agent or a pH increasing agent may be used depending on the mixing ratio.

The pH adjuster may be used by adding an inorganic acid such as HCl or an inorganic base such as NaOH, but more preferably, the pH is adjusted with an organic acid or an organic salt to minimize metal or halogen contamination of the semiconductor device.

As the pH increasing agent, organic groups such as ammonium hydroxide, monoethanol amine, diethanol amine, triethanol amine, and the like are used, and as the pH reducing agent, an organic acid such as acetic acid is used.

Hard pads are used to eliminate steps in the CMP process.

In the case of the present invention described above, it is similar to a damascene process by depositing a plug material after forming a gate electrode and isolating it through a CMP process.

In a subsequent process, a bit line contact process for exposing a portion of the cell contact plug 4480c to be made with the bit line contact is performed.

According to the present invention made as described above, after the gate electrode patterning, the conductive film for the plug is first deposited, and the cell contact is removed by polishing the gate hard mask using a CMP process and then selectively removing the conductive film for the plug in a region other than the cell contact plug. By forming a plug, it was found through the examples that the following advantages.

1) Since the thickness of the first interlayer insulating film on the gate electrode is not taken into consideration when depositing the conductive film for the plug, the deposition thickness may be reduced when the conductive film for the plug is deposited.

2) In the CMP process for plug isolation, excessive or underpolishing due to the difference in polishing rate between the conductive film, the gate hard mask, and the first interlayer insulating film, and the plug seam and dishing caused by this, can be solved.

3) Process burden and SAC fail can be prevented during contact hole formation caused by the increase of the aspect ratio due to the increase of the thickness of the gate electrode and the decrease of the space.

4) The deposition step of the interlayer insulating film can be reduced from the conventional two steps to one step.                     

5) Since the deposition step of the interlayer insulating film can be reduced to one step, the CMP process can be reduced by one step.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can increase the process margin and ensure the stability of the process when forming the cell contact plug, thereby improving the yield of the semiconductor device.

Claims (13)

Forming a plurality of gate electrodes on the substrate; Forming insulating spacers on sidewalls of the plurality of gate electrodes; Forming a conductive film for a plug on the entire surface including the gate electrode; Performing a planarization process on a target to which the gate electrode is exposed; And Selectively removing the plug conductive film that does not make cell contact among the planarized plug conductive films Semiconductor device manufacturing method comprising a. The method of claim 1, After the step of selectively removing the conductive film for the plug, And depositing an interlayer insulating film on the entire surface, and planarizing the interlayer insulating film. The method of claim 1, And using a chemical mechanical polishing process in the step of performing the planarization process. The method of claim 3, wherein The plug conductive film includes a polysilicon film, and the gate electrode includes a gate hard mask made of a nitride film on top thereof. The method of claim 4, wherein And a polishing selectivity between the plug conductive layer and the gate hard mask is 10: 1 to 50: 1 during the chemical mechanical polishing process. The method of claim 5, wherein The method of manufacturing a semiconductor device, characterized in that for the chemical mechanical polishing process using a slurry containing a silica or alumina abrasive of the size of 50nm to 300nm. The method of claim 6, Waste water (pH) of the slurry is 5 to 11, characterized in that the semiconductor device manufacturing method. The method of claim 7, wherein The slurry is a semiconductor device manufacturing method characterized in that it further comprises an oxidizing agent to increase the polishing rate of the polysilicon. The method of claim 2, The interlayer insulating film, An APL (Advanced Planarization Layer) film deposited using a low pressure chemical vapor deposition method using an impurity doped oxide film, hydrogen peroxide (H ₂ O ₂ ) and silane (SiH ₄ ) as a reaction source, and deposited using an atomic layer deposition method. SiH ₄ , SiHa (CH ₃ ) b (0 ≦ a ≦ 4, 0 ≦ b ≦ 4) and N ₂ , N ₂ O, NH ₃ , O ₂ , O ₃ , Ar, He, NF ₃ as oxides or sources A semiconductor device manufacturing method comprising an oxide film deposited using a high density plasma method. The method of claim 9, In the case of using an oxide film deposited by a high density plasma method as the interlayer insulating film, a mixture including H ₂ , O ₂ , N ₂ , O ₃ , N ₂ O or H ₂ / O ₂ after deposition of the interlayer insulating film for film densification The method of manufacturing a semiconductor device, further comprising the step of heat treatment in a gas atmosphere. The method of claim 9, Using a chemical mechanical polishing process in the step of planarizing the layered insulating film, and using a slurry in which silica abrasive and ceria abrasive are mixed in a ratio of 1: 9 to 9: 1. The method of claim 11, The silica abrasive and the ceria abrasive is a semiconductor device manufacturing method, characterized in that 5w% to 20w% of the total weight of the slurry. The method of claim 12, In the chemical mechanical polishing process, The polishing pressure is maintained at 1 psi to 10 psi, and the polishing table speed is maintained at 10 rpm to 100 rpm.

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