KR20060038585A - Method for fabrication of deep contact hole in semiconductor device - Google Patents

Abstract

The present invention is to provide a method for forming a deep contact hole of a semiconductor device capable of suppressing the reduction of CD and ensuring a sufficient bottom CD when forming a deep contact hole. To this end, the present invention provides an insulating film on a conductive layer. Making; Forming a mask pattern on the insulating film; Etching a portion of the insulating layer using the mask pattern as an etching mask; Lowering the pressure of the chamber and evacuating the polymeric residual gas to remove the polymeric residual gas generated during the etching process; And forming an open portion for exposing the conductive layer by etching another portion of the insulating layer which remains the mask pattern as an etch mask, thereby forming a deep contact hole in the semiconductor device.

Deep contact holes, bit lines, hard masks, polymeric residual gases, metal wiring and exhaust.

Description

Method for forming deep contact hole in semiconductor device {METHOD FOR FABRICATION OF DEEP CONTACT HOLE IN SEMICONDUCTOR DEVICE}             

1 is a cross-sectional view illustrating a semiconductor memory device in which deep contact holes are formed using a hard mask.

FIG. 2 is a SEM photograph showing a cross section after gap-filling a contact hole by depositing a metal film after forming a deep contact hole in the absence of a heterogeneous material layer. FIG.

FIG. 3 is a SEM photograph showing a cross section after gap-filling a contact hole by depositing a metal film after forming a deep contact hole in the case where there is a dissimilar material layer. FIG.

4 is a SEM photograph showing the plane of FIG.

FIG. 5 is a SEM photograph showing the plane of FIG. 3. FIG.

6 is a flowchart illustrating a deep contact hole forming process flow of the present invention.

7A to 7D are cross-sectional views illustrating a contact hole process for forming a bit line metal wiring in a peripheral region of a semiconductor memory device according to an embodiment of the present invention.

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a deep contact hole in a semiconductor device.

In general, a semiconductor device includes a plurality of unit devices therein. As semiconductor devices are highly integrated, various elements must be formed at a high density on a certain cell area, thereby decreasing the size of unit devices such as transistors and capacitors. In particular, in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), as the design rule decreases, the size of unit elements formed inside the cell gradually decreases, but in order to secure the capacity of the capacitor, the aspect ratio increases. This is unavoidable, which causes difficulties in the process of forming deep contact holes.

When applying the photolithography process using ArF (argon fluoride) exposure having a wavelength of 193 nm in a semiconductor device having a line width of 80 nm or less, the requirements for the conventional etching process (exact pattern formation and vertical etching profile, etc.) There is a further need for preventing the deformation of photoresist generated during etching. Accordingly, when manufacturing a semiconductor device of 80 nm or less, the development of process conditions for simultaneously satisfying the existing requirements and the new requirements of pattern deformation prevention has become a major problem in terms of etching.

Meanwhile, as the degree of integration of the device increases and the design rule decreases, the distance between adjacent conductive patterns (eg, gate electrodes) decreases. In contrast, as the thickness of the conductive pattern increases, the height of the conductive pattern and the conductive patterns decrease. The aspect ratio, which represents the ratio of the distances between, gradually increases.

A representative example is a deep contact hole forming process for forming a metal line of a bit line in a peripheral region after forming a bit line and forming a capacitor of a cell region in manufacturing a semiconductor memory device.

In order to form such a bit line metal wiring, it must be suitable for a process such as ArF or F ₂ photolithography to match the fine pattern forming process. When the contact size is 150 nm or less (design rule of 80 nm or less) and the aspect ratio is 15/1 or more, the photoresist pattern alone does not act as a masking, and the problem of weak etching resistance against fluorine-based gas of the ArF photoresist must also be overcome. do.

In order to overcome the limitations of the ArF photolithography process, a hard mask is used.

FIG. 1 is a cross-sectional view illustrating a process of forming a deep contact hole for forming a bit line metal line using a hard mask in a semiconductor memory device.

Referring to FIG. 1, a bit line 101 is formed on a substrate 100 on which various devices such as a transistor are formed. The bit line is surrounded by the first insulating film 102.

The second insulating film 103, the third insulating film 104, and the fourth insulating film 105 are stacked on the first insulating film 102. The storage node contact and the capacitor forming process are performed in the cell region between the second insulating film 103 and the fourth insulating film 105.                         

Therefore, in order to form the bit line metal wirings, all of the second insulating film 103 to the fourth insulating film 105 must be etched. To this end, a hard mask 106 is formed on the fourth insulating layer 105. The hard mask 106 may use a material such as nitride film, silicon, or tungsten.

On the hard mask 106, an organic antireflection film 107 and a photoresist pattern 108, which is a mask for forming contact holes for bit line metal wirings, are formed.

After the hard mask 106 is formed in the etching process, the photoresist pattern 108 may be removed and then the photoresist pattern 108 and the hard mask 106 may be removed without removing the photoresist pattern 108. It may be performed as an etching mask. In this case, the photoresist pattern 108 and the hard mask 106 are used as etching masks.

The second contact layer 103 to the fourth insulating layer 105 are etched by an etching process using the photoresist pattern 108 and the hard mask 106 as an etching mask to expose the conductive layer of the bit line 101. 109 is formed.

The bit line 101 generally has a laminated structure of an insulating bit line hard mask / bit line conductive film / barrier film, and etching is performed to the bit line hard mask to form metal wires.

The use of the hard mask 106 has the advantage of overcoming the limitations of the photoresist pattern 108 as an etch mask, while providing a gap-fill margin in subsequent metal film deposition by increasing the thickness of the hard mask 106. Decrease. In addition, the gap in the upper opening of the contact hole 109 is narrower, the gap-fill problem becomes more serious.                         

FIG. 2 is a SEM (Scanning Electron Microscopy) photograph showing a cross section after gap-filling a contact hole by depositing a metal film after forming a deep contact hole in the absence of a heterogeneous material layer, and FIG. SEM image showing a cross section after gap-filling a contact hole by depositing a metal film after contact hole formation.

Referring to FIG. 2, it can be seen that the metal film M is deposited to gap-fill the contact hole H. For example, in the case of a deep contact hole for forming a bit line interconnection in the cell peripheral region, the etching depth is very deep, such as 30000Å, and as a result, the critical dimension (CD) gradually decreases from cd1 to cd4 as shown below. Done.

In FIG. 2, as an ideal case, each of the insulating films ILD1 to ILD4 is made of a substantially similar series, for example, an oxide-based material, and the CD decreases with increasing etching depth.

4 is a SEM photograph showing the plane of FIG. 2. Referring to FIG. 4, it can be seen that the CD of the contact hole H is reduced than originally intended.

However, in practice, different types of insulating films are stacked between the insulating films ILD1 to ILD4. In the case where the insulating films ILD1 to ILD4 are oxide film-based examples, a representative example is a case where the nitride film-based insulating films Nt1 and Nt2 are stacked. The nitride films Nt1 and Nt2 serve as hard masks or etch stop films and are often left.

An etching process for forming a deep contact hole is usually performed by combining a hard mask or a photoresist pattern and a hard mask into one gas combination. However, since it is very difficult to control the etch selectivity with respect to heterogeneous insulating films 1: 1, as shown by 'X' of FIG. 3, a sudden decrease of CD in the nitride films Nt1 and Nt2 (cd3-> cd4, cd5). -> cd6) occurs.

FIG. 5 is an SEM photograph showing the plane of FIG. 3. Referring to FIG. 5, it can be seen that the CD of the contact hole H is markedly reduced compared to FIG. 4.

On the other hand, in order to solve this problem, if the etching process between the insulating film is different, the productivity is lowered, it is impossible to use the actual process.

The reduction of CD causes deterioration of the gap-fill characteristics of the metal film M, which causes problems such as lifting of the metal wiring and electromigration (EM).

On the other hand, in order to solve this gap-fill problem, the contact size of the mask may be increased, but in this case, it may cause a problem of overlap margin with neighboring patterns.

As the CD decreases, the contact resistance increases, and in severe cases, it may cause contact not open.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a method for forming a deep contact hole in a semiconductor device capable of suppressing a reduction in CD and securing a sufficient bottom CD when forming a deep contact hole. It is done.

The present invention to achieve the above object, forming an insulating film on the conductive layer; Forming a mask pattern on the insulating film; Etching a portion of the insulating layer using the mask pattern as an etching mask; Lowering the pressure of the chamber and evacuating the polymeric residual gas to remove the polymeric residual gas generated during the etching process; And forming an open portion for exposing the conductive layer by etching another portion of the insulating layer which remains the mask pattern as an etch mask, thereby forming a deep contact hole in the semiconductor device.

In addition, to achieve the above object, the present invention, forming a bit line having a laminated structure of a bit line hard mask / bit line conductive film; Forming an insulating film on the bit line; Forming a mask pattern on the insulating film; Etching a portion of the insulating layer using the mask pattern as an etching mask; Lowering the pressure of the chamber and evacuating the polymeric residual gas to remove the polymeric residual gas generated during the etching process; And forming an open portion for exposing the bit line conductive layer by etching the other portion of the insulating layer and the bit line hard mask, the mask pattern remaining as an etch mask, to form a deep contact hole in the semiconductor device. .

Problems such as a decrease in contact size or deformation of a contact shape when forming a deep contact hole may cause polymer gas generated as a by-product as the by-product continues to be accumulated in the contact hole without being pumped out. Ion bombardment) keeps pointing to one side as it goes on. This tendency is exacerbated when the depth of etching becomes longer and the time of etching becomes longer, and it becomes difficult to keep the chuck properly. In other words, if the wafer cooling is insufficient and the temperature rises, the amount of polymer generated increases.

In order to solve this problem, the present invention minimizes polymer generation by adding a step of evacuating the polymer gas generated during the etching process in the middle of the etching process for forming the deep contact hole. In addition, when the plasma generation is stopped in such an exhausting step, the cooling process of the wafer may be simultaneously achieved during this step, thereby further reducing the generation of polymeric etching gas.

Therefore, the shape of the contact hole may be prevented from being deformed when the deep contact hole is formed, and the CD of the contact bottom may be increased.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can more easily implement the present invention.

FIG. 6 is a flowchart illustrating a deep contact hole forming process flow of the present invention, and looks at the deep contact hole forming process of the present invention with reference to the flowchart.

An insulating film is formed on the substrate on which the predetermined process is completed (S601). Here, the insulating film includes a structure in which an oxide film-based insulating film and a nitride film-based insulating film are stacked.

A mask pattern for forming a deep contact hole is formed on the insulating layer (S602).                     

The mask pattern may include a single structure of the photoresist pattern, a structure in which the photoresist pattern and the sacrificial hard mask are stacked, a single structure in which the photoresist pattern is removed and only the sacrificial hard mask, and an antireflection film is added or not added thereto. Include all structures.

As the sacrificial hard mask, a polysilicon film, a nitride film, an amorphous carbon film or a tungsten film is used.

The insulating layer is etched using the mask pattern as an etch mask. In this case, a self alignment contact (hereinafter referred to as SAC) etching process may be applied. In this case, a gas including F, in particular, a CF-based gas is used as an etching gas.

During the etching process, gases such as carbon and nitrogen are generated, and they combine to form a polymer. Therefore, in the present invention, the etching process is stopped after etching only a part of the insulating film without performing the insulating film etching process at once (S603).

After stopping the etching process, the pressure in the chamber is lowered compared to the etching process and the polymer residual gas generated during the etching process is discharged.

Exhaust of the polymeric residual gas results in a significant reduction in the generation of polymers in subsequent processes.

At this time, the wafer is cooled when the temperature in the chamber is lowered by not operating the plasma generator. Cooling of the wafer contributes to reducing polymer generation in subsequent etching processes.

Subsequently, the remaining portion of the insulating layer is etched to form a contact hole (S605).                     

Since the etching process is performed while the wafer is cooled, generation of polymer gas is reduced. In addition, since the existing polymer residual gas is removed, the generation of the polymer occurs extremely insignificantly. As a result, the CD (Critical Dimension) reduction of the contact hole or the distortion of the contact hole shape hardly occurs, and the contact not open phenomenon does not occur.

Here, the size of the contact hole is 0.25 mu m or less in diameter, and the thickness of the insulating film, that is, the depth of the contact hole is 20,000 kPa or more.

7A to 7D are cross-sectional views illustrating a contact hole process for forming a bit line metal interconnection in a peripheral region of a semiconductor memory device according to an embodiment of the present invention, with reference to the deep contact hole forming process of the present invention. It explains in detail.

In the embodiment of the present invention described below, a process of forming a space pattern, for example, a contact hole pattern, of a semiconductor device is described as an example. The contact hole pattern to which the present invention is applied is a metal wiring contact and a bit line. Alternatively, the present invention may be applied to a process for forming a contact pad and contact with an impurity bonding layer in a substrate such as a source / drain junction for a storage node contact of a capacitor.

First, as shown in FIG. 7A, a stack structure of a bit line hard mask 702 / bit line conductive layer 701 and a spacer 703 on a sidewall thereof are formed on a substrate 700 on which various elements for forming a semiconductor device are formed. To form a bit line (B / L) having a.

Tungsten is mainly used as the bit line conductive film 701, and an insulating film based on a nitride film such as a silicon nitride film or a silicon oxynitride film is mainly used as the bit line hard mask 702.

The bit line B / L is contacted with a source / drain junction, a cell contact plug, or a gate electrode below the structure of Ti / TiN via a barrier layer. Here, since the peripheral region of the semiconductor memory device is taken as an example, the bit line B / L is in contact with the source / drain junction or the gate electrode.

The first insulating layer 704 and the second insulating layer 705 are formed on the bit lines B / L.

Here, the first and second insulating films 704 and 705 include a structure in which an oxide film-based insulating film and a nitride film-based insulating film are stacked.

When the second insulating layer 705 is formed, a cell capacitor is formed in the cell region. In addition, since the second insulating film 705 corresponds to the vertical height of the capacitor, its vertical thickness is quite large.

Examples of the oxide-based insulating film include HDP (High Density Plasma) oxide film, TEOS (Tetra Ethyl Ortho Silicate) film, BPSG (Boro Phospho Silicate Glass) film, BSG (Boro Silicate Glass) film, PSG (Phospho Silicate Glass) film, SOG (Spin On Glass) film, APL (Advanced Planarization Layer) film, and the like, and the nitride film-based insulating film includes a silicon oxynitride film or a silicon nitride film.

Subsequently, a material layer 706a for hard mask is formed on the second insulating layer 705 by using a material having a selectivity with the second insulating layer 704 and the first insulating layer 704 as the etching target layer.

The hard mask material film 706a includes a nitride film, a polysilicon film, an Al film, a W film, a WSix (x is 1 to 2) film, a WN film, a Ti film, a TiN film, a TiSix (x is 1 to 2) film, TiAlN film, TiSiN film, Pt film, Ir film, IrO ₂ film, Ru film, RuO ₂ film, Ag film, Au film, Co film, Au film, TaN film, CrN film, CoN film, MoN film, MoSix (x At least one thin film selected from the group consisting of 1 to 2) film, Al ₂ O ₃ film, AlN film, PtSix (x is 1 to 2) film, CrSix (x is 1 to 2) film, and amorphous carbon film Include.

Subsequently, due to the high light reflectivity of the lower portion, that is, the hard mask material layer 706a during exposure for forming a pattern on the material layer 706a for hard mask, diffuse reflection is prevented from forming an unwanted pattern. An anti-reflective film (not shown, anti-reflective coating) is formed to improve adhesion between the mask material film 706a and the subsequent photoresist. The anti-reflection film mainly uses an organic material that is similar to the photoresist and has an etching property thereof, which can be simultaneously removed through a photoresist strip process.

Subsequently, a photoresist (e.g., a photoresist including COMA or acrylate) is applied on the antireflective film by a spin coating method or the like to an appropriate thickness, and then the F ₂ exposure source or the ArF exposure source and the bit A predetermined portion of the photoresist is selectively exposed using a predetermined reticle (not shown) for defining the width of the deep contact hole for the line metal wiring, and the portion exposed or not exposed by the exposure process through the developing process is left. Next, the photoresist pattern 707 is formed by removing the etching residues through a post-cleaning process or the like.

Subsequently, the antireflection film is selectively etched through a selective etching process using the photoresist pattern 707 as an etching mask.

In this case, in order to minimize the loss of the photoresist pattern 707, the etching process is mainly performed using a plasma using a chlorine gas such as Cl ₂ , BCl ₃ , CCl _4, or HCl, or C when using a CF gas. The etching process is performed using a plasma having a gas having a low / F ratio, for example, any one selected from the group consisting of CF ₄ , C ₂ F ₂ , CHF ₃ and CH ₂ F ₂ .

When the antireflection film is etched, the CD should be easily controlled, so it is preferable to apply the above etching conditions to hardly generate polymer.

As shown in FIG. 7B, the hard mask material layer 706a is etched using the photoresist pattern 707 as an etch mask to form a hard mask 706b.

In this process, the photoresist pattern 707 and the anti-reflection film are naturally removed during the process. If not removed, a separate photoresist strip process may be performed.

Hereinafter, the etching process of the above-described hard mask material film 706a will be described in detail.

When the hard mask material film 706a is a thin film containing tungsten (W) such as a W film, a WSix film, or a WN film, a plasma using a mixed gas of SF ₆ / N ₂ is used, in which case SF ₆ / to use the mixing ratio of N ₂ is 0.10 ~ 0.60 are preferred.

When the hard mask material film 706a is a thin film containing titanium (Ti) such as a polysilicon film or a Ti film, a TiN film, a TiSix film, a TiAlN film or a TiSiN film, chlorine-based gas, in particular, Cl ₂ In this case, oxygen (O ₂ ) or CF gas is appropriately added to control the etching profile.

When the hard mask material layer 706a includes a noble metal such as Pt, Ir, Ru, or an oxide or nitride thereof, plasma using a chlorine-based or fluorine-based gas is used, and in order to control the etching profile, Since high ion energy is required, it is desirable to maintain low pressure and high bias power conditions for this purpose.

As shown in FIG. 7B, a portion of the second insulating layer 705 is etched using the hard mask 706b as an etch mask.

In this case, a plasma etching method is used, and gases such as C _x F _y (x and y are 1 to 10) and C _a H _b F _c (a and b and c are 1 to 10) are used as base gases. And a combination of gases such as N ₂ , O ₂ , and Ar are used here.

C _x F _y is a fluorine-based gas that is usually used for etching when the layer to be etched is an oxide-based layer, and C ₂ F ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₅ F _8, or C ₅ F ₁₀ And C _a H _b F _c is a gas for generating a polymer in the SAC etching process, and includes CH ₂ F ₂ , C ₃ HF _5, or CHF ₃ . N ₂ / O ₂ is used to improve the etching profile, and Ar is used as the carrier gas.

In the etching process of FIG. 7B, gases such as carbon and nitrogen are generated, and these combine to form a polymer.

Therefore, in the present invention, the etching process is stopped after only a part of the second insulating film 705 is etched without performing an etching process such as the second insulating film 705 and the first insulating film 704 at once.

In this case, the etching process may be stopped on a part of the first insulating layer 704.

After stopping the etching process, as shown in FIG. 7C, the pressure of the chamber is lowered compared to the etching process and the polymer residual gas generated during the etching process is discharged as indicated by reference numeral 707. Exhaust of the polymeric residual gas results in a significant reduction in the generation of polymers in subsequent processes.

At this time, the wafer is cooled when the temperature in the chamber is lowered by not operating the plasma generator. Cooling of the wafer contributes to reducing polymer generation in subsequent etching processes.

At this time, it is preferable to maintain the pressure of the chamber at 10 mTrr to 200 mTorr.

As shown in FIG. 7D, a plasma etching process using CxFy and CaHbFc gas is performed to etch the remaining portion of the second insulating layer 705, the first insulating layer 704, and the bit line hard mask 702.

Accordingly, an open portion 708, that is, a deep contact hole, is formed to expose the bit line conductive film 701.

It can be seen that the CD of the open portion 708 is narrowed by the polymer or the contact sickle does not occur in the final cross section of FIG. 7D due to the discharge of the polymer residual gas and the wafer cooling process performed in the process of FIG. 7C.

Meanwhile, in the above-described exemplary embodiment, since the bit line conductive film 701 is exposed, the bit line hard mask 702 is formed on the top of the bit line conductive film 701.

On the other hand, when the portion exposed to connect the metal wiring is a source / drain junction instead of the bit line conductive layer 701, the bit line hard mask 702 may be another etch stop layer based on the nitride layer.

The present invention made as described above, by discharging the polymer residual gas in the intermediate stage of the etching during the deep contact hole formation and cooling the wafer, thereby preventing the phenomenon that the shape of the contact hole due to polymer formation or contact sick opening occurs It can be seen through the examples that it can be done.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment of the present invention, the bit line metal wiring process is taken as an example. However, the present invention may be applied to any process for forming contact holes, such as forming a contact hole with a gate electrode pattern, a contact pad, or a metal wiring.

As described above, the present invention can sufficiently secure the critical dimension at the time of forming the deep contact hole, thereby reducing the occurrence of defects in manufacturing a semiconductor device and improving the yield.

Claims (11)

Forming an insulating film on the conductive layer; Forming a mask pattern on the insulating film; Etching a portion of the insulating layer using the mask pattern as an etching mask; Lowering the pressure of the chamber and evacuating the polymeric residual gas to remove the polymeric residual gas generated during the etching process; And Forming an open portion for exposing the conductive layer by etching another portion of the insulating layer having the mask pattern as an etch mask; Deep contact hole forming method of a semiconductor device comprising a. The method of claim 1, In the exhausting step, the deep contact hole forming method of the semiconductor device, characterized in that for maintaining the pressure of the chamber from 10mTorr to 200mTorr compared to the etching step. The method according to claim 1 or 2, In the exhausting step, stopping the plasma generation to cool the wafer. The method according to claim 1 or 2, The insulating film is a deep contact hole forming method of a semiconductor device, characterized in that the oxide film-based and nitride-based insulating film laminated structure. The method of claim 4, wherein In the etching of the insulating film, C _x F _y (x, y is 1 to 10) and C _a H _b F _c (a, b, c is 1 to 10) as a base gas, the deep contact hole forming method of a semiconductor device. The method according to claim 1 or 2, And the conductive layer comprises any one of a gate electrode pattern, a bit line, a contact pad, and a metal wiring. Forming a bit line having a stacked structure of a bit line hard mask / bit line conductive film; Forming an insulating film on the bit line; Forming a mask pattern on the insulating film; Etching a portion of the insulating layer using the mask pattern as an etching mask; Lowering the pressure of the chamber and evacuating the polymeric residual gas to remove the polymeric residual gas generated during the etching process; And Forming an open portion for exposing the bit line conductive layer by etching the other part of the insulating layer having the mask pattern as an etch mask and the bit line hard mask; Deep contact hole forming method of a semiconductor device comprising a. The method of claim 1, In the exhausting step, the deep contact hole forming method of the semiconductor device, characterized in that for maintaining the pressure of the chamber from 10mTorr to 200mTorr compared to the etching step. The method according to claim 7 or 8, In the exhausting step, stopping the plasma generation to cool the wafer. The method according to claim 7 or 8, The insulating film is a deep contact hole forming method of a semiconductor device, characterized in that the oxide film-based and nitride-based insulating film laminated structure. The method of claim 10, In the etching of the insulating film, C _x F _y (x, y is 1 to 10) and C _a H _b F _c (a, b, c is 1 to 10) as a base gas, the deep contact hole forming method of a semiconductor device.

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