KR20060037745A - Method for contact not open test of semicondutor device - Google Patents

Method for contact not open test of semicondutor device Download PDF

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KR20060037745A
KR20060037745A KR1020040086794A KR20040086794A KR20060037745A KR 20060037745 A KR20060037745 A KR 20060037745A KR 1020040086794 A KR1020040086794 A KR 1020040086794A KR 20040086794 A KR20040086794 A KR 20040086794A KR 20060037745 A KR20060037745 A KR 20060037745A
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South Korea
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contact
open
insulating film
plug
substrate
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KR1020040086794A
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Korean (ko)
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이원욱
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주식회사 하이닉스반도체
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Publication of KR20060037745A publication Critical patent/KR20060037745A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 콘택 낫-오픈 여부를 정확히 판단할 수 있는 반도체 소자의 콘택 낫-오픈 테스트 방법에 관한 것으로, 기판 상에 형성된 절연막을 관통하여 기판에 콘택되는 플러그를 형성하는 단계; 상기 절연막의 90％ 내지 95％가 제거되는 타킷으로 상기 절연막 및 상기 플러그를 평탄화하는 단계; 상기 절연막을 제거하는 단계; 및 상기 기판 상에 플러그의 잔류 여부에 따라 콘택 낫-오픈(Contact Not-Open)을 판단하는 단계를 포함한다.
The present invention relates to a contact sick-open test method for a semiconductor device capable of accurately determining whether a contact sickle-open of a semiconductor device is provided, the method comprising: forming a plug contacting the substrate through an insulating film formed on the substrate; Planarizing the insulating film and the plug with a target from which 90% to 95% of the insulating film is removed; Removing the insulating film; And determining contact not-open according to whether a plug remains on the substrate.

콘택 낫-오픈(Contact Not-Open), 폴리실리콘, 콘택홀Contact Not-Open, Polysilicon, Contact Hole

Description

반도체 소자의 콘택 낫-오픈 테스트 방법{METHOD FOR CONTACT NOT OPEN TEST OF SEMICONDUTOR DEVICE} TECHNICAL FOR CONTACT NOT OPEN TEST OF SEMICONDUTOR DEVICE             

도 1a 는 종래기술에 따른 반도체 소자의 콘택 낫-오픈 테스트 방법을 설명하기 위한 평면도, 1A is a plan view illustrating a contact sick-open test method of a semiconductor device according to the related art;

도 1b는 도 1a의 A-A'선을 따라 절단한 단면도,1B is a cross-sectional view taken along the line AA ′ of FIG. 1A;

도 2a 내지 도 2d는 본 발명의 바람직한 실시예에 따른 반도체 소자의 콘택 낫-오픈 테스트 방법을 설명하기 위한 도면.
2A to 2D are views for explaining a contact sick-open test method of a semiconductor device according to a preferred embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

20 : 기판 21 : 절연막20: substrate 21: insulating film

22 : 플러그 C1, C2 : 콘택홀
22: plug C1, C2: contact hole

본 발명은 콘택 낫-오픈 테스트 방법에 관한 것으로, 특히 반도체 소자의 콘 택 낫-오픈(Contact Not-Open)여부를 정확히 판단할 수 있는 반도체 소자의 콘택 낫-오픈 테스트 방법에 관한 것이다.The present invention relates to a contact not-open test method, and more particularly, to a contact not-open test method of a semiconductor device capable of accurately determining whether a contact not-open (Contact Not-Open) of a semiconductor device.

최근 반도체 소자의 집적도가 증가함에 따라 콘택홀 패턴의 크기가 줄어들게 되어 결과적으로 콘택홀의 종횡비가 커지게 되었다. 높은 종횡비를 가지는 콘택홀의 경우 식각시 식각 부산물(By-Product)이 콘택홀 내에서 제거되지 않아 콘택홀 패턴이 형성되는 과정에서 중간에 막히는 낫-오픈(Not-Open)불량이 발생하기 쉽다.Recently, as the degree of integration of semiconductor devices increases, the size of the contact hole pattern is reduced, resulting in an increase in the aspect ratio of the contact hole. In the case of a contact hole having a high aspect ratio, by-products are not removed from the contact hole during etching, and thus a not-open defect that is blocked in the middle of the contact hole pattern is likely to occur.

도 1a 는 종래기술에 따른 반도체 소자의 콘택 낫-오픈 테스트 방법을 설명하기 위한 평면도이고 , 도 1b는 도 1a의 A-A'선을 따라 절단한 단면도이다.FIG. 1A is a plan view illustrating a contact sick-open test method of a semiconductor device according to the related art, and FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG. 1A.

도 1a 및 도 1b에서 도시한 바와 같이, 기판(10) 상에 절연막(11)을 형성하고 절연막(11) 상에 마스크 패턴(도면에 도시되지 않음)를 형성한다. 이어서, 마스크 패턴을 식각마스크로 절연막(11)을 식각하여 콘택홀(12)을 형성한다.As shown in FIGS. 1A and 1B, an insulating film 11 is formed on the substrate 10 and a mask pattern (not shown) is formed on the insulating film 11. Subsequently, the insulating layer 11 is etched using the mask pattern as an etch mask to form the contact hole 12.

이어서, 불량 검사장비를 이용하여 콘택 낫-오픈(Contact Not-Open) 여부를 판단한다.Subsequently, it is determined whether the contact not-open (Contact Not-Open) using a failure inspection equipment.

상기와 같은 종래기술에 따른 콘택 낫-오픈 테스트 방법은, 종횡비가 큰 콘택홀의 경우, 콘택홀의 바닥이 보이지 않아 콘택홀의 낫-오픈(Not-Open) 여부를 정확하게 판단할 수 없는 문제점이 발생하였다.
In the contact sickle-open test method according to the prior art as described above, in the case of a contact hole having a large aspect ratio, the bottom of the contact hole is not seen, and thus a problem of not being able to accurately determine whether the contact hole is not-opened has occurred.

본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 반도체 소자의 콘택 낫-오픈(Contact Not-Open) 여부 정확히 판단할 수 있는 반도체 소자의 콘택 낫 -오픈 테스트 방법을 제공하는 데 그 목적이 있다.
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a contact sick-open test method of a semiconductor device capable of accurately determining whether the semiconductor device is contact not-open. .

상기한 목적을 달성하기 위한 본 발명은 기판 상에 형성된 절연막을 관통하여 기판에 콘택되는 플러그를 형성하는 단계; 상기 절연막의 90％ 내지 95％가 제거되는 타킷으로 상기 절연막 및 상기 플러그를 평탄화하는 단계; 상기 절연막을 제거하는 단계; 및 상기 기판 상에 플러그의 잔류 여부에 따라 콘택 낫-오픈(Contact Not-Open)을 판단하는 단계를 포함하는 반도체 소자의 콘택 낫-오픈 테스트 방법을 제공한다.
The present invention for achieving the above object comprises the steps of forming a plug in contact with the substrate through the insulating film formed on the substrate; Planarizing the insulating film and the plug with a target from which 90% to 95% of the insulating film is removed; Removing the insulating film; And determining a contact not-open according to whether a plug remains on the substrate.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 2a 내지 도 2d는 본 발명의 바람직한 실시예에 따른 반도체 소자의 콘택 낫-오픈 테스트 방법을 설명하기 위한 도면으로, 각 도면의 (a)는 평면도이고, 각 도면의 (b)는 (a)의 B-B'선을 따라 절단한 단면도이다.2A to 2D are diagrams for describing a contact sick-open test method of a semiconductor device according to a preferred embodiment of the present invention, where (a) of each drawing is a plan view and (b) is (a) Sectional drawing cut along the line B-B 'of the figure.

도 2a를 참조하면, 기판(20) 상에 절연막(21)을 형성하고, 절연막(21) 상에 콘택홀 형성을 위한 마스크 패턴(도면에 도시되지 않음)을 형성한다. 여기서, 절연막(21)은 산화막이다.Referring to FIG. 2A, an insulating film 21 is formed on the substrate 20, and a mask pattern (not shown) for forming contact holes is formed on the insulating film 21. Here, the insulating film 21 is an oxide film.

이어서, 마스크 패턴을 식각마스크로 절연막(21)을 식각하여 콘택홀(C1, C2) 을 형성한다.Subsequently, the insulating layer 21 is etched using the mask pattern as an etch mask to form contact holes C1 and C2.

이어서, 도 2b에 도시된 바와 같이, 마스크 패턴를 제거하고, 폴리실리콘을 포함하는 물질로 콘택홀(C1, C2)의 내부를 모두 채워 플러그(22)를 형성한다. 여기서, 콘택홀의 내부를 충분히 채우기 위해서는 폴리실리콘을 포함하는 물질을 2000Å 내지 4000Å의 두께로 형성한다.Subsequently, as shown in FIG. 2B, the mask pattern is removed, and the plug 22 is formed by filling both of the contact holes C1 and C2 with a material including polysilicon. In order to sufficiently fill the inside of the contact hole, a material including polysilicon is formed to a thickness of 2000 kPa to 4000 kPa.

이어서, 도 2c에 도시된 바와 같이, 절연막(21)의 90％ 내지 95％가 제거되는 타킷으로 절연막(21) 및 플러그(22)를 화학적기계적연마하여 평탄화 시킨다.Subsequently, as illustrated in FIG. 2C, the insulating film 21 and the plug 22 are chemically mechanically polished and planarized with a target from which 90% to 95% of the insulating film 21 is removed.

이어서, 도 2d에 도시된 바와 같이, BOE(Buffered Oxide Etchant)와 같은 습식식각용액을 이용하여 남아 있는 절연막(21)을 제거 한다.Subsequently, as shown in FIG. 2D, the remaining insulating layer 21 is removed using a wet etching solution such as BOE (Buffered Oxide Etchant).

이어서, 도면에 도시되지 않았지만 불량검사 장비를 이용하여 기판(20) 상에 플러그(22)의 잔류여부를 판단하여 콘택홀의 낫-오픈(Not-Open) 불량을 검출한다.Subsequently, although not shown in the drawing, a defect inspection device is used to determine whether the plug 22 remains on the substrate 20 to detect a not-open defect of the contact hole.

상기와 같이 본 발명의 바람직한 실시예에 따른 반도체 소자의 콘택 낫-오픈 테스트 방법은 콘택 낫-오픈(Contact Not-Open)되지 않은 경우는 기판 상에 플러그가 남아 있고, 콘택 낫-오픈(Contact Not-Open)된 경우는 기판 상에 플러그가 남아 있지 않으므로 콘택홀의 낫-오픈(Not-Open) 불량을 쉽게 검출할 수 있다.
As described above, when the contact not-open test method of the semiconductor device according to the preferred embodiment of the present invention is not contact not-opened, the plug remains on the substrate and the contact not-opened. In the case of -Open, since the plug does not remain on the substrate, it is easy to detect a not-open defect of the contact hole.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의해야 한다. 또한, 본 발명의 기술 분야의 통상의 지식을 가진자라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명에 의하면 기판 상에 콘택홀을 채우고 있던 플러그의 잔류여부로 콘택 낫-오픈(Contact Not-Open)을 판단할 수 있으므로, 콘택홀의 낫-오픈(Not-Open) 불량을 쉽게 검출할 수 있다. According to the present invention described above, since contact not-open can be determined based on whether a plug which has filled a contact hole on a substrate can be easily detected, a not-open defect of a contact hole can be easily detected. Can be.

Claims (6)

기판 상에 형성된 절연막을 관통하여 기판에 콘택되는 플러그를 형성하는 단계;Forming a plug penetrating the insulating film formed on the substrate and contacting the substrate; 상기 절연막의 90％ 내지 95％가 제거되는 타킷으로 상기 절연막 및 상기 플러그를 평탄화하는 단계; Planarizing the insulating film and the plug with a target from which 90% to 95% of the insulating film is removed; 상기 절연막을 제거하는 단계; 및Removing the insulating film; And 상기 기판 상에 플러그의 잔류 여부에 따라 콘택 낫-오픈(Contact Not-Open)을 판단하는 단계Determining contact not-open according to whether a plug remains on the substrate; 를 포함하는 반도체 소자의 콘택 낫-오픈 테스트 방법.Contact sick-open test method of a semiconductor device comprising a. 제1항에 있어서, The method of claim 1, 상기 콘택 낫-오픈(Contact Not-Open)을 판단하는 단계에서, In determining the contact not-open (Contact Not-Open), 상기 기판 상에 상기 플러그가 잔류하면 콘택 낫-오픈(Contact Not-Open)이 발생하지 않은 것으로 판단하고, 상기 기판 상에 상기 플러그가 잔류하지 않으면 콘택 낫-오픈(Contact Not-Open)으 발생한 것으로 판단하는 반도체 소자의 콘택 낫-오픈 테스트 방법.If the plug remains on the substrate, it is determined that contact not-open has not occurred. If the plug does not remain on the substrate, contact not-open has occurred. A contact sickle-open test method for determining a semiconductor device. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 플러그는 그 종횡비가 적어도 10:1인 반도체 소자의 콘택 낫-오픈 테스트 방법.And wherein said plug has an aspect ratio of at least 10: 1. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 플러그는 폴리실리콘을 포함하는 반도체 소자의 콘택 낫-오픈 테스트 방법.The plug is a contact sick-open test method of a semiconductor device comprising a polysilicon. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 절연막은 산화막을 포함하는 반도체 소자의 콘택 낫-오픈 테스트 방법.The insulating film is an contact sick-open test method of a semiconductor device comprising an oxide film. 제5항에 있어서,The method of claim 5, 상기 절연막을 제거하는 단계에서, BOE를 이용하는 반도체 소자의 콘택 낫-오픈 테스트 방법.In the step of removing the insulating film, a contact sick-open test method of a semiconductor device using a BOE.
KR1020040086794A 2004-10-28 2004-10-28 Method for contact not open test of semicondutor device KR20060037745A (en)

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