KR20060033959A - Circuit for driving address line of plasma display panel - Google Patents

Abstract

An object of the present invention is to ensure that noise caused by a displacement current generated when an address voltage is applied to an address driving circuit does not affect the driving IC.

In order to achieve the above object, the present invention outputs a display data signal for driving address electrode lines of a plasma display panel by receiving an address voltage, and accumulates charges remaining in a discharge cell to discharge the stored charges. An address driving circuit of a plasma display panel including a regenerative circuit,

An address voltage switching unit including a first switch configured to receive an address voltage, a second switch connected at one end thereof to the first switch, and connected to a ground at the other end thereof;

To operate the first switch and the second switch, a high signal output terminal for outputting a high signal to the first switch, a low signal output terminal for outputting a low signal to the second switch, and a ground terminal connected to ground. A driving IC having a; And

A first transformer connected between the high signal output terminal and the first switch and a second connected between the low signal output terminal and the second switch to separate the ground of the driving IC and the ground of the second switch An address driving circuit of a plasma display panel including a power regenerative circuit is provided.

Description

Circuit for driving address line of plasma display panel

1 is an internal perspective view showing the structure of a conventional three-electrode surface discharge plasma display panel.

FIG. 2 is a block diagram illustrating a conventional driving device of the plasma display panel of FIG. 1.

FIG. 3 is a diagram illustrating a conventional power recovery circuit included in the address driver of FIG. 2.

4 is a circuit diagram illustrating a driving voltage for controlling an address voltage switching unit and an address voltage switching unit included in the power regeneration circuit of FIG. 3.

FIG. 5 is a timing diagram illustrating a power output from the address voltage switching unit of FIG. 4 and applied to an address driving circuit and a current according thereto.

6 is a circuit diagram illustrating an address voltage switching unit, a driving IC, and a transformer included in the address driving circuit of the present invention.

FIG. 7 is a circuit diagram illustrating a power regeneration circuit included in the address driving circuit of the present invention and including the address voltage switching unit of FIG. 6.

FIG. 8 is a circuit diagram illustrating the address driving circuit of FIG. 7.                 

Explanation of symbols on the main parts of the drawings

1 ... plasma display panel, 100 ... front glass substrate,

102, 110, dielectric layer, 104 ... protective layer,

106 ... rear glass substrate, 108 ... discharge space,

112 fluorescent layer, 114 bulkhead,

A ₁ , A ₂ , ..., A _{m ...} address electrode line,

X ₁ , ..., X _n ... X electrode line, Y ₁ , ..., Y _n ... Y electrode line,

X _na , Y _na ... transparent electrode line, X _nb , Y _nb ... metal electrode line,

200 image processing unit, 202 logic control unit,

204 ... Y drive, 206 ... address drive,

208 ... X drive unit, 206a ... address drive circuit,

206b ... power regenerative circuit, SA ... address drive control signal,

      Vpp ... power voltage terminal, Va ... address voltage,

Id ... displacement current, Sh ... high signal,

  Sl ... low signal, Ru ... first resistance,

Rd ... 2nd resistor, S1 ... 1st switch,

S2 ... 2nd switch, GND ... common ground,

Tu ... first transformer, Td ... second transformer,

C1 ... first control signal, C2 ... second control signal,                 

GND1 ... 1st ground, GND2 ... 2nd ground,

401 drive IC, 301 energy storage

     303 ... clamping part, 305 ... address voltage switching part

     307 power regeneration drive unit,

The present invention relates to an address driving circuit of a plasma display panel. More particularly, the present invention relates to a ground and an address voltage switching unit connected to a driving IC in order to prevent noise caused by a displacement current generated when an address voltage is applied to the driving IC. An address driving circuit of a plasma display panel having a transformer separating a ground connected thereto.

1 is a view showing the structure of a conventional three-electrode surface discharge plasma display panel.

Referring to FIG. 1, between the front and rear glass substrates 100 and 106 of a conventional surface discharge plasma display panel 1, the address electrode lines A1, A2,. 110, Y electrode lines Y1, ..., Yn, X electrode lines X1, ..., Xn, fluorescent layer 112, partition wall 114 and a protective layer, for example magnesium monoxide ( MgO) layer 104 is provided.

The address electrode lines A1, A2,..., Am are formed in a predetermined pattern on the front side of the rear glass substrate 106. The lower dielectric layer 110 is applied to the front of the address electrode lines A1, A2, ..., Am. In front of the lower dielectric layer 110, barrier ribs 114 are formed in a direction parallel to the address electrode lines A1, A2,..., Am. The partition walls 114 function to partition a predetermined area of each display cell and to prevent optical interference between each display cell. The fluorescent layer 112 is formed between the partition walls 114.

The X electrode lines (X1, ..., Xn) and the Y electrode lines (Y1, ..., Yn) may be orthogonal to the address electrode lines (A1, A2, ..., Am). 100) is formed in a constant pattern on the back. Each intersection sets a corresponding display cell. Each X electrode line (X1, ..., Xn) and each Y electrode line (Y1, ..., Yn) have conductivity and transparent electrode line (Xna, Yna) of transparent conductive material such as ITO (Indium Tin Oxide) Metal electrode lines (Xnb, Ynb) to increase the can be formed by combining. The front dielectric layer 102 is formed by applying the entire surface to the rear of the X electrode lines X1, ..., Xn and the Y electrode lines Y1, ..., Yn. A protective layer 104 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying a front surface to the back of the front dielectric layer 102. The plasma forming gas is sealed in the discharge space 108.

A driving scheme generally applied to such a plasma display panel is a method in which initialization, address, and display holding steps are sequentially performed in a unit sub-field. In the initialization step, the state of charge of the display cells to be driven becomes uniform. In the address step, the charge state of display cells to be selected and the charge state of display cells not to be selected are set. In the display holding step, display discharge is not performed in display cells that are not selected, and display discharge is performed in selected display cells. At this time, a plasma is formed from the plasma forming gas of the display cells performing display discharge, and the fluorescent layer 112 of the display cells is excited by ultraviolet radiation from the plasma to generate light.

FIG. 2 shows a typical driving device of the plasma display panel of FIG. 1.

Referring to the drawings, a typical driving apparatus of the plasma display panel 1 includes an image processor 200, a logic controller 202, an address driver 206, an X driver 208, and a Y driver. The image processing unit 200 converts an external analog image signal into a digital signal, and internal image signals such as 8-bit red (R), green (G), and blue (B) image data, clock signals, vertical and Generate horizontal sync signals. The address driver 206 processes the address drive control signal SA from the logic controller 202 to generate a display data signal, and applies the generated display data signal to the address electrode lines. The X driver 208 processes the X drive control signal SX from the logic controller 202 and applies it to the X electrode lines. The Y driver 204 processes and applies the Y drive control signal SY from the logic controller 202 to the Y electrode lines.

FIG. 3 is a diagram illustrating a conventional power recovery circuit included in the address driver of FIG. 2.

The address driving circuit 206 processes the address driving control signal SA from the logic controller 202 to generate the display data signals Sd1, Sd2, ..., Sdm, and thus the address electrode lines A1. , A2, ..., Am). The address voltage Va to be applied to the address driving circuit 206 is controlled by the operation of the power regenerative circuit 206b. The reason for this is that, at the time when the application of the display data signals Sd1, Sd2, ..., Sdm ends, the charges that are unnecessarily remaining in the discharge cells of the plasma display panel are collected, and the display data signals Sd1, Sd2, This is to apply the collected charges to the discharge cells at the time when the application of Sdm) starts. In a typical power regenerative circuit, the inductance L _PR of the resonant coil is set to perform resonance with respect to the average operating capacitance of the plasma display panel.

4 is a circuit diagram illustrating a driving IC for controlling an address voltage switching unit and an address voltage switching unit included in the power regeneration circuit of FIG. 3.

Referring to the drawings, in order to apply power by the address voltage to the power supply voltage terminal Vpp of the address driving circuit 206a in the address driver 206, the first switch S1 to which the address voltage Va is applied. ) And a second switch S2 having one end connected to the first switch S1 and the other end connected to the ground, the address voltage switching unit 305 includes the first switch S1 and the second switch S2. Perform turn on / turn off operation. In order to control the switching operation of the first switch S1 and the second switch S2, the high signal output terminal H and the second switch outputting a high signal Sh for operating the first switch S1 ( A driving IC 401 having a low signal output terminal L for outputting a low signal Sl for operating S2 and a ground terminal GND connected to ground is used.                         

FIG. 5 is a timing diagram illustrating a power output from the address voltage switching unit of FIG. 4 and applied to an address driving circuit and a current according thereto.

The first switch S1 and the second switch S2 of the address voltage switching unit of FIG. 5 perform the turn on / off operation to have the address voltage Va at the power supply voltage terminal Vpp of the address driving circuit 206a. Apply power. At an application point t2 of the address voltage Va, a displacement current Id of several tens of amps flows through the address voltage switching unit 305.

In the related art, the ground connected to the address voltage switching unit 305 in the power regeneration circuit 206b and the ground of the driving IC 401 for operating the same are used as the common ground GND. However, as shown in FIG. 5, a displacement current Id of several tens of amperes occurs at the time when the address voltage Va is applied by the switching operation of the address voltage switching unit 305, and the noise is caused by the address voltage switching unit. The inside of the driving IC 401 is affected through the common ground GND connected in common with the ground of the 305 and the ground of the driving IC 401. This affects the display data signals Sd1, Sd2, ..., Sdm applied to the address electrodes A1, A2, ..., Am through the power supply voltage terminal Vpp. , Vertical streak noise, etc. will appear.

In order to solve the above problems, an object of the present invention is to provide an address driving circuit of a plasma display panel having a transformer separating a ground connected to a driving IC and a ground connected to an address voltage switching unit.

An object of the present invention is to prevent noise caused by a displacement current generated when an address voltage is applied to an address driving circuit from affecting the driving IC.

In order to achieve the above object, the present invention, by applying an address voltage outputs a display data signal for driving the address electrode lines of the plasma display panel, accumulates the charges remaining in the discharge cell to discharge the stored charges An address driving circuit of a plasma display panel including a power regenerative circuit,

An address voltage switching unit including a first switch receiving an address voltage, a second switch connected to one end of the first switch, and connected to a ground;

A drive having a high signal output terminal for outputting a high signal to the first switch, a low signal output terminal for outputting a low signal to the second switch, and a ground terminal connected to ground for operating the first switch and the second switch; IC; And

In order to separate the ground of the driving IC and the ground of the second switch, the first transformer is connected between the high signal output terminal and the first switch, and the second transformer is connected between the low signal output terminal and the second switch. An address driver circuit of a plasma display panel including a power regenerative circuit is provided.

According to another aspect of the present invention, the first transformer and the second transformer, the ground connected to the drive IC and the ground connected to the second switch is separated, when the address voltage is applied by the switching of the address voltage switching unit It is possible to prevent the noise caused by the displacement current generated from the influence on the driver IC.

According to another feature of the present invention, the first transformer and the second transformer may be a transformer ratio of 1: 1.

According to another aspect of the present invention, it may further include a first resistor connected between the first switch and the first transformer and a second resistor connected between the second switch and the second transformer.

According to another aspect of the present invention, both the first switch and the second switch are field effect transistors, and an address voltage is applied to the drain terminal of the first field effect transistor, and the gate terminal is connected to the first transformer. The source terminal may be connected to the drain terminal of the second field effect transistor, the gate terminal of the second field effect transistor may be connected to the second transformer, and the source terminal may be connected to ground.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

6 is a circuit diagram illustrating an address voltage switching unit, a driving IC, and a transformer included in the address driving circuit of the present invention.

The address driving circuit of the plasma display panel including the power regenerative circuit of the present invention includes a first voltage switching unit 305, a driving IC 401, a first voltage between the address voltage switching unit 305, and the driving IC 401. A transformer Tu and a second transformer Td are provided.

The address voltage switching unit 305 may include a first switch S1 receiving an address voltage Va and a second switch S2 having one end connected to the first switch S2 and the other end connected to ground. Include. The address voltage Va is a power supply voltage of the address driving circuit 206a between the first switch S1 and the second switch S2 when the first switch S1 is turned on and the second switch S2 is turned off. It is output to the terminal Vpp. In addition, the ground voltage is a power supply voltage terminal of the address driving circuit 206a between the first switch S1 and the second switch S2 when the first switch S1 is turned off and the second switch S1 is turned on. Vpp).

Meanwhile, both the first switch S1 and the second switch S2 may be implemented as field effect transistors (FETs). That is, an address voltage is applied to the drain terminal of the first field effect transistor S1, a first control signal C1 is applied to the gate terminal, and a source terminal is connected to the drain terminal of the second field effect transistor S2. . The source terminal of the second field effect transistor S2 is connected to ground, and the second control signal C2 is applied to the gate terminal. The first field effect transistor S1 and the second field effect transistor S2 are turned on / off by the control signals C1 and C2 applied to the respective gate terminals.

The driving IC 401 has a high signal output terminal H for outputting a high signal Sh to the first field effect transistor S1, and a low signal for outputting a low signal Sl to the second switch S2. An output terminal L and a ground terminal GND connected to the ground are provided. The driving IC 401 is operated by a driving power source Vcc (for example, 15V), and receives the driving control signal Sc output from the image processor 200 (in FIG. 2), and receives the high signal Sh or the low signal ( Outputs Sl).                     

The first transformer Tu is connected between the high signal output terminal H of the driving IC 401 and the gate terminal of the first field effect transistor S1. The second transformer Td is connected between the low signal output terminal of the driving IC 401 and the gate terminal of the second field effect transistor S2. The first transformer Tu and the second transformer Td include a driving IC 401, an address voltage switching unit 305 including the first field effect transistor S1 and the second field effect transistor S2. It serves to separate. Therefore, the ground connected to the driving IC 401 becomes the first ground GND1, and the ground connected to the address voltage switching unit 305 becomes the second ground GND2.

Conventionally, the noise caused by the displacement current (Id in FIG. 5) generated when the address voltage is applied by the switching of the address voltage switching controller affects the driving IC 401 due to the common ground (GND). In the address driving circuit 206 according to the present invention, since the driving IC 401 and the address voltage switching unit 305 are separated by the first transformer Tu and the second transformer Td, the address voltage switching unit ( Noise caused by the displacement current Id generated at the time when the address voltage Va is applied by the switching of the 305 does not affect the driving IC 401.

Meanwhile, the transformer ratio of the first transformer Tu and the second transformer Td may be 1: 1. Since the first transformer Tu and the second transformer Td are used to insulate the driving IC 401 and the address voltage switching unit 305, the high signal Dh output from the driving IC 401 is provided. In order to transfer the low signal S1 to the address voltage switching unit 305 as it is, the transformer ratio of the first transformer Tu and the second transformer Td is preferably 1: 1.

In addition, the first resistor Ru may be further connected between the first transformer Tu and the first field effect transistor S1, and the second resistor Ru may be connected between the second transformer Td and the second field effect transistor S2. The resistor Rd may be further connected. In consideration of the operating voltage of the field effect transistor and the voltage level of the high signal Sh or the low signal Sl output from the driving IC 401, the first resistor Ru and the second resistor for the voltage drop. (Rd) can be used. Therefore, the high signal Sh is input to the gate terminal of the first field effect transistor S1 as the first control signal C1 via the first resistor Ru, and the low signal Sl is the second resistor Rd. Via the second control signal C2 is input to the gate terminal of the second field effect transistor S2.

Referring to the operation of the address driving circuit 206 of the present invention, the driving IC 401 receives the driving control signal Sc and outputs a high signal Sh or a low signal Sl.

First, if the high signal Sh is output from the driving IC 401, the high signal Sh is input to the input terminal of the first transformer Tu and is output at the output terminal with a transformer ratio of 1: 1. The high signal Sh output from the first transformer Tu is input to the gate terminal of the first field effect transistor S1 as the first control signal C1, which has a predetermined voltage drop through the first resistor Ru. do. The first field effect transistor S1 is turned on by the first control signal C1 input to the gate terminal of the first field effect transistor S1, and the address voltage Va applied to the drain terminal is transferred through the source terminal. It is applied to the power supply voltage terminal Vpp of the address driving circuit 206a.                     

Next, when the low signal Sl is output from the driving IC 401, the low signal Sl is input to the input terminal of the second transformer Td and output at the output stage with a transformer ratio of 1: 1. The low signal Sl output from the second transformer Td is input to the gate terminal of the second field effect transistor S2 as the second control signal C2, which has a predetermined voltage drop through the second resistor Rd. do. The second field effect transistor S2 is turned on by the second control signal C2 input to the gate terminal of the second field effect transistor S2, and the ground voltage at ground connected to the source terminal is applied to the address driving circuit 206a. Is applied to the power supply voltage terminal Vpp.

In the present invention, when the address voltage Va is applied, a displacement current of several tens of amps (Id in FIG. 5) flows through the address voltage switching unit 305, and noise caused by the second ground connected to the address voltage switching unit 305 ( GND2). Since the noise due to the displacement current Id does not affect the driving IC 401, the first ground GND1 connected to the driving IC is applied to the address electrodes A1, A2,... The display data signals Sd1, Sd2, ..., Sdm are normally output from the address driving circuit 206a.

FIG. 7 is a circuit diagram of the power regeneration circuit 206b included in the address driving circuit 206 of the present invention and including the address voltage switching unit 305 of FIG.

The power regenerative circuit 206b largely includes an address voltage switching unit 305, a power regenerative driver 307, and an energy storage unit 301.

One end of the address voltage switching unit 305 is connected to the first switch S1 and the first switch S1 to which the address voltage Va is applied, and the other end thereof is connected to the second ground GND2. It is composed of

Both the first switch S1 and the second switch S2 may be implemented as field effect transistors. Therefore, an address voltage Va is applied to the drain terminal of the first field effect transistor S1, and The drain terminal of the second field effect transistor S2 is connected, and the source terminal of the second field effect transistor S2 is connected to the second ground GND2.

Meanwhile, in the present invention, a high signal output stage outputting a high signal Sh to the first field effect transistor S1 in order to operate the first field effect transistor S1 and the second field effect transistor S2. (H), a driving IC having a low signal output terminal L for outputting the low signal Sl to the second field effect transistor S2, and a ground terminal GND connected to the first ground GND1. 401 is provided. In addition, in order to separate the first ground GND1 of the driving IC 401 and the second ground GND2 of the address voltage switching unit 305, the high signal output terminal H and the first field effect transistor ( A first transformer Tu connected between S1 and a second transformer Td connected between the low signal output terminal L and the second field effect transistor S2 is provided.

The power regenerative driver 307 includes a pair of diodes Dp1 and Dp2 and a pair of switches S3 and S4 that are directly connected to the diodes, respectively, and a connection node between the pair of diodes Dp1 and Dp2. Is coupled through the inductor (L _PR ) to determine whether to apply the charges remaining in the discharge cell with a pair of switches (S3, S4). In addition, between the first node S1 and the connection node between the first diode Dp1 and the second diode Dp2 of the power regeneration driver 307, and the first diode Dp1 and the second of the power regeneration driver 307. The clamping part 303 which consists of overvoltage prevention diodes Dc1 and Dc2 is connected between the connection node between diodes Dp2, and 2nd switch S2, respectively. The clamping unit 303 transitions the voltage of the connection node between the first diode Dp1 and the second diode Dp2 of the power regenerative driver 307 to be greater than or equal to the address voltage Va or less than or equal to the ground potential GND. To reduce the voltage stress of the diodes Dp1 and Dp2 and the switches S3 and S4.

The energy storage unit 301 is connected between the third switch S3 and the fourth switch S4 of the power regenerative driving unit 307 to regenerate power according to the switching of the third switch S3 and the fourth switch S4. Charges collected in the driver 307 are accumulated, and the accumulated charges are emitted.

 FIG. 8 is a circuit diagram illustrating the address driving circuit 206a of FIG. 7.

Referring to this, the power of the pulse signal having the address voltage Va supplied from the power regenerative circuit 206b of FIG. 7 is applied to the power supply voltage terminal Vpp.

In the address driving circuit 206a, the number of pairs of switches to which the upper switch Fu1 and the lower switch Fd1 are connected is provided as many as the number of address electrodes A1, A2, ..., Am. The pair of switches are turned on / off by the address driving control signal SA to supply each display data signal Sd1, Sd2, ..., Sdm to each address electrode A1, A2, ..., Am. Output

 According to the present invention as described above, the following effects can be obtained.

In the address driving circuit including the driving IC and the address voltage switching unit, as a buffer for electrical isolation, the noise caused by the displacement current of several tens of amps flowing through the address voltage switching unit does not affect the driving IC through the common ground. By connecting the transformer to the driving IC and the address voltage switching section, a stable display data signal can be applied to the address electrode.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (5)

An address driving circuit of the plasma display panel including a power regenerative circuit configured to receive the address voltage and output a display data signal for driving the address electrode lines of the plasma display panel, and accumulate the remaining charges in the discharge cells to discharge the stored charges; To An address voltage switching unit including a first switch configured to receive an address voltage, a second switch connected at one end thereof to the first switch, and connected to a ground at the other end thereof; To operate the first switch and the second switch, a high signal output terminal for outputting a high signal to the first switch, a low signal output terminal for outputting a low signal to the second switch, and a ground terminal connected to ground. A driving IC having a; And A first transformer connected between the high signal output terminal and the first switch and a second connected between the low signal output terminal and the second switch to separate the ground of the driving IC and the ground of the second switch An address driving circuit of a plasma display panel including a power regenerative circuit, characterized by comprising a transformer. The method of claim 1, wherein the first transformer and the second transformer, By separating the ground connected to the driving IC and the ground connected to the second switch, the noise caused by the displacement current generated when the address voltage is applied by the switching of the address voltage switching unit does not affect the driving IC. An address driving circuit of a plasma display panel comprising a power regenerative circuit. The method of claim 1, wherein the first transformer and the second transformer, An address driving circuit of a plasma display panel including a power regenerative circuit, wherein the transformer ratio is all 1: 1. The method of claim 1, A first resistor connected between the first switch and the first transformer and And a second resistor connected between the second switch and the second transformer. The address driving circuit of claim 1, further comprising a power regenerative circuit. The method of claim 4, wherein the first switch and the second switch, All are field effect transistors, wherein the address voltage is applied to a drain terminal of a first field effect transistor, a gate terminal is connected to the first transformer, a source terminal is connected to a drain terminal of a second field effect transistor, 2. The address driving circuit of claim 2, wherein the gate terminal of the field effect transistor is connected to the second transformer and the source terminal is connected to ground.

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