KR20060028155A - Method for fabricating printed circuit board using hybrid build-up process - Google Patents

Abstract

The present invention relates to a method for manufacturing a printed circuit board using a hybrid build-up method in which a central circuit layer uses a low-cost build-up process and fabricates and stacks external circuit layers in parallel.

Printed circuit board manufacturing method using the hybrid build-up method according to the present invention comprises the steps of (A) providing a central core of at least four-layer structure including a predetermined circuit pattern and a plurality of via holes according to the build-up method; (B) providing at least one outer core having predetermined circuit patterns formed on both surfaces thereof and having via holes corresponding to at least some of the via holes of the central core; (C) at least one unclad insulating layer including a via hole corresponding to the via hole of the outer core and having a conductive paste filled therein to electrically connect the via hole of the center core and the via hole of the outer core; Providing; And (D) arranging the unclad and the outer core alternately on at least one surface of the central core to pre-lay up, and stacking them in a batch.

Printed Circuit Boards, Buildup, Batch Lamination, ALIVH, B²IT

Description

Manufacturing method for fabricated printed circuit board using hybrid build-up process

1 is a flow chart of a printed circuit board manufacturing method using a hybrid build-up method according to an embodiment of the present invention.

2A to 2Q are cross-sectional views illustrating the flow of the center core forming step of FIG. 1.

3A to 3H are cross-sectional views illustrating the flow of the outer core forming step of FIG. 1.

4A to 4E are cross-sectional views illustrating the flow of the unclad forming step of FIG. 1.

5A and 5B are cross-sectional views illustrating the flow of the batch lamination step of FIG. 1.

The present invention relates to a method for manufacturing a printed circuit board using a hybrid build-up method. More specifically, the central circuit layer is a low-cost build-up process, and an external circuit layer is manufactured in parallel to collectively stack. It relates to a printed circuit board manufacturing method.

Recently, due to the rapid digitalization, networking, and cutting-edge of the electronic industry, printed circuit board technology is also rapidly progressing. As the current trend of electronic devices is light and short, the printed circuit board technology, which is a skeleton of electronic devices, is also required to be miniaturized, light weight, thin, high functional and high density. In order to satisfy these requirements, the manufacturing method of the printed circuit board has been changed to the build-up method.

However, as the circuit pattern of the printed circuit board is increased, the build-up method has a difficulty in integrating a fine circuit pattern, and in particular, there is a problem in that a great difficulty occurs in integrating an outer layer circuit pattern at a high density. Therefore, in order to manufacture a denser printed circuit board, various printed circuit board manufacturing methods are required.

Printed circuit board manufacturing methods currently being developed include a batch lamination method, an All Layer Inner Via Hole (ALIVH) method, and a B ² IT (Buried Bump Interconnection Technology) method.

Among them, the batch lamination method has an advantage that the circuit pattern of the entire circuit layer of the printed circuit board can be manufactured with high density. However, since a drilling process having a high process cost must be performed on each circuit layer to be stacked, there is a problem that the process cost greatly increases according to the number of circuit layers.

On the other hand, the ALIVH method has an advantage of improving connection reliability by filling a conductor in the via hole inner wall instead of copper plating. However, there is a problem in that the process time is long because the multilayer printed circuit board is sequentially manufactured by lamination. In addition, similar to the build-up method, since the ALIVH method is sequentially stacked to form a circuit layer, there is a problem in that there is a limit in manufacturing a printed circuit board in which circuit patterns are densely integrated like the build-up method.

On the other hand, since the B ² IT method has many similarities to the above-described ALIVH method, the characteristics of the manufactured printed circuit board are similar. Therefore, like the ALIVH method, the B ² IT method has a long process time and has a problem in manufacturing a high density printed circuit board.

The technical problem of the present invention for solving the above problems is to provide a printed circuit board manufacturing method capable of forming a high-density circuit pattern (in particular, the circuit pattern of the outer layer).

Another technical problem of the present invention is to provide a printed circuit board manufacturing method capable of reducing the number of drilling processes.

Another technical problem of the present invention is to provide a printed circuit board manufacturing method which can shorten the overall process time.

In order to solve the above technical problem, the printed circuit board manufacturing method using the hybrid build-up method according to the present invention (A) according to the build-up method, at least four-layer structure including a predetermined circuit pattern and a plurality of via holes Providing a central core; (B) providing at least one outer core having predetermined circuit patterns formed on both surfaces thereof and having via holes corresponding to at least some of the via holes of the central core; (C) at least one unclad insulating layer including a via hole corresponding to the via hole of the outer core and having a conductive paste filled therein to electrically connect the via hole of the center core and the via hole of the outer core; Providing; And (D) arranging the unclad and the outer core alternately on at least one surface of the central core to pre-lay up, and stacking them in a batch.

Step (A) of the method for manufacturing a printed circuit board using the hybrid build-up method according to the present invention includes: providing a base substrate having predetermined circuit patterns formed on both surfaces of (A-1); (A-2) stacking insulating layers on both sides of the base substrate and forming via holes connecting the insulating layers; (A-3) forming a first copper plating layer on an inner wall of the insulating layer and the via hole, and then filling a conductive or non-conductive paste into the via hole; (A-4) forming a second copper plating layer on the exposed portion of the first copper plating layer and the conductive or non-conductive paste; (A-5) applying an etching resist to the surface of the second copper plating layer, and then exposing and developing the etching resist to form a predetermined etching resist pattern; And (A-6) forming a circuit pattern corresponding to the etching resist pattern by etching the first copper plating layer and the second copper plating layer using the etching resist pattern.

The step (B) of the method for manufacturing a printed circuit board using the hybrid build-up method according to the present invention includes: (B-1) providing at least one base substrate coated with a copper foil layer on both sides of the insulating resin layer; (B-2) forming via holes corresponding to at least some of the via holes of the center core in the base substrate, and then forming the copper foil layer and the inner copper plating layer of the via holes so as to fill the via holes; (B-3) applying an etching resist on the surface of the copper plating layer, and then exposing and developing the etching resist to form predetermined etching resist patterns, respectively; And (B-4) forming the circuit patterns corresponding to the etching resist patterns by etching the copper plating layer using the etching resist patterns.

Step (C) of the method for manufacturing a printed circuit board using the hybrid build-up method according to the present invention includes: (C-1) providing at least one unclad material having a protective film attached to both surfaces of the insulating layer; (C-2) forming via holes corresponding to the via holes of the outer core in the unclad material, and then filling conductive paste into the via holes, respectively; And (C-3) removing the protective films, respectively.

Steps (A), (B) and (C) of the printed circuit board manufacturing method using the hybrid build-up method according to the present invention are preferably performed simultaneously in parallel.

Hereinafter, a method of manufacturing a printed circuit board using the mixed build-up method according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a flow chart of a method for manufacturing a printed circuit board using the mixed build-up method according to an embodiment of the present invention, and FIGS. 2A to 2Q are cross-sectional views illustrating a flow of the core core forming step of FIG. 1. 3H is a cross-sectional view illustrating the flow of the outer core forming step of FIG. 1, and FIGS. 4A to 4E are cross-sectional views showing the flow of the unclad forming step of FIG. 1, and FIGS. 5A and 5B are the flow of the batch laminating step of FIG. 1. It is sectional drawing which shows.

As shown in FIG. 1, the method for manufacturing a printed circuit board using the mixed build-up method according to the present invention includes forming a central core (S110), forming an outer core (S120), and an unclad ( unclad) forming step (S130), and stacking step (S140) of a central core, an outer core, and an unclad.

Here, the center core forming step S110, the outer core forming step S120, and the unclad forming step S130 may be performed sequentially, but in order to shorten the overall process time, it is preferable to simultaneously perform the parallel processing.

First, referring to the center core forming step (S110), as shown in FIG. 2A, the base substrate 110 is a copper clad laminate in which copper foil layers 112 and 112 ′ are coated on both surfaces of the insulating resin layer 111. Prepare.

Here, the copper clad laminate used as the base substrate 110 may be a glass / epoxy copper clad laminate, a heat-resistant resin copper clad laminate, a paper / phenolic copper clad laminate, a high frequency copper clad laminate, a flexible copper clad laminate, or a composite. Copper foil laminated board etc. can be used. However, in the manufacture of the printed circuit board according to the present invention, it is preferable to use a glass / epoxy copper clad laminate using glass fiber and epoxy resin or a heat resistant resin copper clad laminate using glass fiber and BT resin as the base substrate 110.

In FIG. 2A, a base substrate 110 having a two-layer structure is illustrated, but a base having a multi-layer structure such as four, six, and eight layers in which predetermined circuit patterns and via holes are formed in an inner layer according to a purpose or purpose of use. The substrate 110 may be used.

As shown in FIG. 2B, dry films 120a and 120a 'are applied to upper and lower copper foil layers 112 and 112 ′ of the base substrate 110, respectively.

As shown in FIG. 2C, the art work films 130a and 130a 'printed with a predetermined pattern are adhered to the upper and lower dry films 120a and 120a', respectively, and then irradiated with ultraviolet rays. In this case, the black portions 131a and 131a 'on which the predetermined patterns of the artwork films 130a and 130a' are printed do not transmit ultraviolet rays, and the non-printed portions 132a and 132a 'transmit the artwork. The dry films 120a and 120a 'under the films 130a and 130a' are cured.

As shown in FIG. 2D, after removing the artwork films 130a and 130a ', the base substrate 110 is immersed in the developer, and the portion of the uncured dry film 120a and 120a' is removed by the developer and cured. Only portions of the dry films 120a and 120a 'remain to form an etching resist pattern. Here, the developing solution uses an aqueous solution of sodium carbonate (Na ₂ CO ₃ ) or potassium carbonate (K ₂ CO ₃ ).

As shown in FIG. 2E, the dry films 120a and 120a 'having a predetermined pattern are used as etching resists, and the base substrate 110 is immersed in the etching solution, thereby providing a predetermined pattern of the dry films 120a and 120a'. The upper and lower copper foil layers 112 and 112 'of the remaining portions except for the corresponding portions are removed.

As shown in FIG. 2F, the dry films 120a and 120a ′ applied to the upper and lower surfaces of the base substrate 210 and 110 are peeled off and removed. Here, the dry films 120a and 120a 'are removed using a stripping solution containing sodium hydroxide (NaOH) or potassium hydroxide (KOH).

2B to 2F, dry films 120a and 120a ′ are used as etching resists, but a liquid photosensitive material may be used as an etching resist.

In this case, the liquid photosensitive material exposed to ultraviolet rays is applied to the copper foil layers 112 and 112 'of the base substrate 110 and then dried. Next, a predetermined pattern is formed on the photosensitive material by exposing and developing the photosensitive material using the artwork films 130a and 130a 'provided with the predetermined pattern. Next, by using the photosensitive material in which the predetermined pattern was formed as an etching resist, and spraying the etching liquid on the base substrate 110, the upper and lower copper foil layers 112 and 112 of the remaining portions except for the portion corresponding to the predetermined pattern of the photosensitive material. Remove the '). Thereafter, the photosensitive material is removed. The method of coating the photosensitive material in the liquid state may include a dip coating method, a roll coating method, an electro-deposition method, and the like.

The method using the liquid photosensitive material may be applied thinner than the dry films 120a and 120a ', and thus, a finer circuit pattern may be formed. In addition, when the surface of the base substrate 110 has irregularities, there is also an advantage that can form a uniform surface by filling it.

As shown in FIG. 2G, after insulating layers 113 and 113 ′ (eg, prepreg) are laminated on both sides of the base substrate 110, a predetermined temperature and pressure (eg, about Heated and pressurized at 150 ° C. to 200 ° C., 200 ′ ° C. and 30 kg / cm ^{2 to} 40 kg / cm ² ).

In this case, copper foil may be laminated on the insulating layers 113 and 113 'or Resin Coated Copper (RCC) may be laminated instead of the insulating layers 113 and 113'. In this case, since the thickness of the copper plating layer to be formed later can be reduced, there is an advantage of reducing the copper plating process time.

As shown in FIG. 2H, a via hole 140 is formed so that upper and lower surfaces of the base substrate 110 on which the insulating layers 113 and 113 ′ are stacked are conductive.

Here, the via hole 140 may be a method of forming the via hole 140 according to a preset position using a CNC (Computer Numerical Control) drill or a laser drill.

In addition, after the via hole 140 is formed, a deburring process of removing burrs generated during drilling, dust on the inner wall of the via holes 140, dust on the surfaces of the insulating layers 113 and 113 ′, and the like, and The desmear process of removing the smear generated on the inner wall of the via hole 140 by melting the insulating resin layer 111 and the insulating layers 113 and 113 'due to the heat generated when the via hole 140 is formed. It is preferable to carry out more. In the deburring process, a roughness is applied to the surfaces of the insulating layers 113 and 113 ', thereby improving adhesion to copper in the copper plating process.

As shown in FIG. 2I, first copper plating layers 114 and 114 ′ are formed on upper and lower insulating layers 113 and 113 ′ and inner walls of the via holes 140 to electrically connect the formed via holes 140.

Since the inner wall of the via hole 140 includes the insulating resin layer 111 and the insulating layers 113 and 113 ′, the electroless copper plating is performed first, and then the first copper plating layer 114 is performed by performing electrolytic copper plating having good physical properties. , 114 ').

As shown in FIG. 2J, the conductive or non-conductive paste 150 is filled in the copper plated via hole 140.

As shown in FIG. 2K, the conductive or non-conductive paste 150 protruding out of the surfaces of the first copper plating layers 114 and 114 ′ is removed by using a buff or the like.

As shown in FIG. 2L, second copper plating layers 115 and 115 ′ are formed on exposed portions of the first copper plating layers 114 and 114 ′ and the conductive paste 150.

If the conductive paste 150 is filled in the process of FIG. 2J, electrolytic copper plating may be performed directly. However, since the conductive paste 150 includes an insulating material such as an epoxy resin, its electrical conductivity is worse than that of the first copper plating layers 114 and 114 '. Therefore, after the electroless copper plating is performed, it is preferable to form the second copper plating layers 115 and 115 'by performing electrolytic copper plating.

Meanwhile, when the non-conductive paste 150 is filled in the process of FIG. 2J, the second copper plating layers 115 and 115 ′ are formed by performing electroless copper plating and then electrolytic copper plating as in the case of the conductive paste 150. It is desirable to.

As shown in FIG. 2M, dry films 120b and 120b 'are applied to the upper and lower second copper plating layers 115 and 115'.

As shown in FIG. 2N, the artwork films 130b and 130b 'on which the predetermined patterns are printed are brought into close contact with the upper and lower dry films 120b and 120b', respectively, and then irradiated with ultraviolet rays. At this time, the black portions 131b and 131b 'on which the predetermined patterns of the artwork films 130b and 130b' are printed do not transmit ultraviolet rays, and the non-printed portions 132b and 132b 'transmit the artwork. The dry films 120b and 120b 'under the films 130b and 130b' are cured.

As shown in FIG. 2O, after removing the artwork films 130b and 130b ', the predetermined etching resist pattern is immersed in a developer such as an aqueous solution of sodium carbonate (Na ₂ CO ₃ ) or potassium carbonate (K ₂ CO ₃ ). Form.

As shown in FIG. 2P, the dry films 120b and 120b 'are used as etching resists, and the substrate is immersed in the etching liquid, so that the upper and lower portions of the remaining portions except for the portions corresponding to the predetermined patterns of the dry films 120b and 120b' are etched. The first and second copper plating layers 114, 114 ′, 115, and 115 ′ are removed.

As shown in FIG. 2q, the dry films 120b and 120b 'applied to the upper and lower second copper plating layers 115 and 115' are removed using a stripping solution containing sodium hydroxide (NaOH), potassium hydroxide (KOH), or the like. When the center core 100 of the four-layer structure according to the invention is formed.

Similar to the process of FIGS. 2B to 2F described above, the process of FIGS. 2M to 2Q may also use a liquid photosensitive material as an etching resist to form a predetermined circuit pattern.

Next, referring to the external core forming step (S120), as shown in FIG. 3A, a base substrate 210, which is a copper clad laminate plate having copper foil layers 212 and 212 ′ coated on both surfaces of the insulating resin layer 211, is prepared.

As shown in FIG. 3B, the via holes 240 are formed using a CNC drill or a laser drill to connect circuits of the upper and lower copper foil layers 212 and 212 ′ of the base substrate 210.

As shown in FIG. 3C, copper plating layers 213 and 213 ′ are formed in upper and lower copper foil layers 212 and 212 ′ of the base substrate 210 and inside the via holes 240 for electrical connection of the formed via holes 240. do. At this time, the inside of the via hole 240 is filled with copper plating. Since the inner wall of the via hole 240 includes the insulating resin layer 211, it is preferable to perform electroless copper plating first, and then to perform the electrolytic copper plating having good physical properties to form the copper plating layers 213 and 213 ′.

As shown in FIG. 3D, dry films 220 and 220 ′ are applied to the upper and lower copper plating layers 213 and 213 ′.

As shown in FIG. 3E, the artwork films 230 and 230 ′ printed with a predetermined pattern are adhered to the upper and lower dry films 220 and 220 ′, respectively, and then irradiated with ultraviolet rays. In this case, the black portions 231 and 231 'on which the predetermined patterns of the artwork films 230 and 230' are printed do not transmit ultraviolet rays, and the non-printed portions 232 and 232 'transmit the artwork. The dry films 220 and 220 'under the films 230 and 230' are cured.

3F, after removing the artwork films 230 and 230 ′, the predetermined etching resist pattern is immersed in a developer such as an aqueous solution of sodium carbonate (Na ₂ CO ₃ ) or potassium carbonate (K ₂ CO ₃ ). Form.

As shown in FIG. 3G, the dry films 220 and 220 ′ are used as etching resists, and the base substrate 210 is immersed in the etching solution, thereby excluding portions corresponding to predetermined patterns of the dry films 220 and 220 ′. The upper and lower copper foil layers 212 and 212 'and the copper plating layers 213 and 213' of the remaining portions are removed.

As shown in FIG. 3H, when the dry films 220 and 220 ′ applied to the upper and lower copper plating layers 213 and 213 ′ are removed using a stripping solution containing sodium hydroxide (NaOH) or potassium hydroxide (KOH), and the like, An outer core 200 according to the invention is formed.

Similar to the process of forming the circuit pattern of the center core described above, the process of FIGS. 3D to 3H may also use a liquid photosensitive material as an etching resist to form a predetermined circuit pattern.

Next, referring to the unclad forming step S130, as shown in FIG. 4A, protective films 312 and 312 ′ (eg, polyester) are formed on both surfaces of the insulating layer 311 (eg, prepreg). An unclad material 310 having a film) is prepared.

As in FIG. 4B, the via cladding 310 is formed using a CNC drill or a laser drill to form the via holes 320. At this time, it is preferable to form the via hole 320 of the unclad material 310 slightly larger than the via hole diameter formed in the center core and the outer core in consideration of the connection with the circuit layer in the subsequent stacking step.

As shown in FIG. 4C, the conductive paste 330 is filled in the via hole 320 for electrical connection of the formed via hole 320.

As shown in FIG. 4D, the conductive paste 330 protruding out of the surfaces of the protective films 312 and 312 ′ may be removed by using a buff or the like.

As shown in FIG. 4E, when the protective films 312 and 312 ′ are removed on both surfaces of the insulating layer 311, an unclad 300 according to the present invention is formed.

Next, referring to the batch stacking step (S140), as shown in FIG. 5A, the upper part formed by the method illustrated in FIGS. 3A to 3H, centered on the center core 100 formed by the method illustrated in FIGS. 2A to 2Q, is illustrated. And preliminary lay-up of the lower outer cores 200, 200 'and the upper and lower unclads 300, 300' formed by the method shown in FIGS. 4A-4E.

Here, in order to accurately match the via holes of the central core 100, the upper and lower outer cores 200 and 200 ′, and the upper and lower unclad 300 and 300 ′, a targeting method or a pin matching method may be used. It is desirable to perform a preliminary layup.

The targeting method stacks the center core 100, the upper and lower outer cores 200 and 200 ', and the upper and lower uncladding 300 and 300', and then targets holes in the respective target target marks. In the manner of processing, a target drill by X-rays is usually used.

Meanwhile, in the pin matching method, guide holes, which are a reference hole between the center core 100, the upper and lower outer cores 200 and 200 ', and the upper and lower uncladding 300 and 300', respectively, are formed at the same position, The core core 100, the outer cores 200 and 200 'and the uncladding 300 and 300' are accurately matched.

As shown in FIG. 5B, the upper outer core 200, the upper unclad 300, the center core 100, the lower unclad 300 'and the lower outer core 200' which are sequentially laid up from the top are sequentially When the sheets are compressed and stacked in a batch, the printed circuit board 1000 having an eight-layer structure is completed.

Thereafter, a solder resist forming process, a nickel / gold plating process, and an outer forming process are performed.

In a preferred embodiment of the present invention, the number of via holes of the center core, the upper outer core and the lower outer core may be formed differently. For example, 1000 via holes may be formed in the central core, 500 via holes may be formed in the upper outer core, and 600 via holes may be formed in the lower outer core. In this case, since the upper unclad must electrically connect the via hole of the upper outer core and the via hole of the center core, it is preferable to form the same 500 via holes as the upper outer core. Similarly, since the lower unclad must electrically connect the via hole of the lower outer core and the via hole of the center core, it is preferable to form 600 via holes.

In another preferred embodiment of the present invention, a plurality of upper outer cores or a plurality of lower outer cores may be stacked on a center core to manufacture eight or more printed circuit boards.

Although the present invention has been described above, this is only one embodiment, and it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention. . However, it will be confirmed through the claims that such changes and modifications fall within the scope of the present invention.

As described above, the method of manufacturing a printed circuit board using the hybrid build-up method according to the present invention may reduce the cost of manufacturing a high-density printed circuit board since the core core, which is an inner part, is manufactured in a build-up process with less drilling. It has an effect.

In addition, in the method of manufacturing a printed circuit board using the mixed build-up method according to the present invention, since internal bubbles are not generated by pasting the via hole of the inner layer, deadly reliability defects such as hole cracking and hole bursting may be prevented in external environmental tests such as thermal shock. There is also an effect that can be prevented.

In addition, the method of manufacturing a printed circuit board using the mixed build-up method according to the present invention does not generate solder balls on the surface of the entire printed circuit board because the outer layers are manufactured in parallel, so that solder ball voids do not occur. It also has the effect of preventing solder ball cracks during mounting.

In addition, the method of manufacturing a printed circuit board using the mixed build-up method according to the present invention has an effect of forming a fine circuit pattern on the outer layer because the outer layer is separately laminated after the circuit is formed, so that thick copper plating is not required.

In addition, the method of manufacturing a printed circuit board using the hybrid build-up method according to the present invention has the effect of shortening the process time since the core core, the external core, and the unclad fabric are manufactured and stacked in parallel.

Claims (5)

(A) providing a central core of at least a four-layer structure including a predetermined circuit pattern and a plurality of via holes, according to a buildup scheme; (B) providing at least one outer core having predetermined circuit patterns formed on both surfaces thereof and having via holes corresponding to at least some of the via holes of the central core; (C) at least one unclad insulating layer including a via hole corresponding to the via hole of the outer core and having a conductive paste filled therein to electrically connect the via hole of the center core and the via hole of the outer core; Providing; And (D) a preliminary lay-up by alternately arranging the unclad and the outer core on at least one surface of the center core, and then laminating them collectively; a printed circuit using a hybrid build-up method comprising a Substrate manufacturing method. The method of claim 1, wherein step (A) comprises: (A-1) providing a base substrate having predetermined circuit patterns formed on both surfaces thereof; (A-2) stacking insulating layers on both sides of the base substrate and forming via holes connecting the insulating layers; (A-3) forming a first copper plating layer on an inner wall of the insulating layer and the via hole, and then filling a conductive or non-conductive paste into the via hole; (A-4) forming a second copper plating layer on the exposed portion of the first copper plating layer and the conductive or non-conductive paste; (A-5) applying an etching resist to the surface of the second copper plating layer, and then exposing and developing the etching resist to form a predetermined etching resist pattern; And (A-6) forming a circuit pattern corresponding to the etching resist pattern by etching the first copper plating layer and the second copper plating layer using the etching resist pattern. Printed circuit board manufacturing method using the up method. According to claim 1, wherein (B) step, (B-1) providing at least one base substrate coated with a copper foil layer on both sides of the insulating resin layer; (B-2) forming via holes corresponding to at least some of the via holes of the center core in the base substrate, and then forming the copper foil layer and the inner copper plating layer of the via holes so as to fill the via holes; (B-3) applying an etching resist on the surface of the copper plating layer, and then exposing and developing the etching resist to form predetermined etching resist patterns, respectively; And (B-4) forming a circuit pattern corresponding to the etching resist pattern by etching the copper plating layer using the etching resist pattern; a printed circuit board using a mixed buildup method Manufacturing method. The method of claim 1, wherein step (C) comprises: (C-1) providing at least one unclad material having a protective film attached to both sides of the insulating layer; (C-2) forming via holes corresponding to the via holes of the outer core in the unclad material, and then filling conductive paste into the via holes, respectively; And (C-3) removing each of the protective films; a printed circuit board manufacturing method using a mixed build-up method comprising a. The method according to any one of claims 1 to 4, The steps (A), (B) and (C) are performed at the same time in parallel, the printed circuit board manufacturing method using a hybrid build-up method.

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