KR20060002052A - Method for forming transistor of semiconductor devices - Google Patents

Method for forming transistor of semiconductor devices Download PDF

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KR20060002052A
KR20060002052A KR1020040050944A KR20040050944A KR20060002052A KR 20060002052 A KR20060002052 A KR 20060002052A KR 1020040050944 A KR1020040050944 A KR 1020040050944A KR 20040050944 A KR20040050944 A KR 20040050944A KR 20060002052 A KR20060002052 A KR 20060002052A
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layer
forming
gate
mask
semiconductor substrate
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KR1020040050944A
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Korean (ko)
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서문식
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

Abstract

본 발명은 반도체소자의 트랜지스터 형성방법에 관한 것으로, 계단형 게이트 구조에서 게이트 단차나 오정렬에 의하여 문턱전압이 불균일하게 되는 현상을 방지하기 위하여, 반도체기판 상의 비트라인 콘택영역에 희생막 패턴을 형성하고, 상기 희생막 패턴의 측벽에 스페이서를 형성한 다음, 상기 스페이서 및 희생막 패턴을 마스크로 하는 식각공정으로 트렌치를 형성하고 상기 스페이서를 제거한 다음, 상기 반도체기판에 문턱전압용 불순물을 이온주입하고 상기 희생막 패턴 사이의 반도체기판 상부를 매립하는 게이트산화막, 폴리실리콘층 및 게이트용 금속층의 적층구조를 형성한 다음, 상기 구조물 상에 하드마스크층을 패터닝하고 상기 하드마스크층을 마스크로 하여 하부구조물을 식각하여 게이트를 형성함으로써 자기정렬적으로 계단형 게이트를 형성하고 문턱전압을 일정하게 조절할 수 있도록 하여 반도체소자의 특성 및 신뢰성을 향상시키며 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다. The present invention relates to a method for forming a transistor of a semiconductor device, in order to prevent a phenomenon in which the threshold voltage is uneven due to a gate step or misalignment in a stepped gate structure, a sacrificial film pattern is formed in a bit line contact region on a semiconductor substrate. Forming a trench on a sidewall of the sacrificial layer pattern, forming a trench in an etching process using the spacer and the sacrificial layer pattern as a mask, removing the spacer, and ion implanting an impurity for a threshold voltage into the semiconductor substrate; After forming a lamination structure of a gate oxide film, a polysilicon layer, and a gate metal layer that fills the upper surface of the semiconductor substrate between the sacrificial layer patterns, a hard mask layer is patterned on the structure, and the lower structure is formed using the hard mask layer as a mask. Self-aligned stepped crab by etching to form a gate Forming a bit and to improve the characteristics and reliability of the semiconductor device so as to adjust a constant threshold voltage sikimyeo a technique that enables high integration of the semiconductor device thereof.

Description

반도체소자의 트랜지스터 형성방법{Method for forming transistor of semiconductor devices}Method for forming transistor of semiconductor devices

도 1 및 도 2 는 종래기술에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단면도.1 and 2 are cross-sectional views showing a transistor forming method of a semiconductor device according to the prior art.

도 3a 내지 도 3f 는 본 발명에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단면도.3A to 3F are cross-sectional views showing a transistor forming method of a semiconductor device according to the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

11,31 : 반도체기판 13,33 : 소자분리막11,31: semiconductor substrate 13,33: device isolation film

15,43 : 게이트산화막 17,45 : 폴리실리콘층15,43 gate oxide film 17,45 polysilicon layer

19,47 : 게이트용 금속층 21,49 : 하드마스크층19,47 gate metal layer 21,49 hard mask layer

23 : 소오스/드레인 접합영역 25,55 : 절연막 스페이서23 source / drain junction region 25, 55 insulating film spacer

35 : 희생막 패턴 37 : 스페이서35: sacrificial film pattern 37: spacer

39 : 트렌치 41 : 문턱전압용 불순물39: trench 41: impurity for threshold voltage

51 : 게이트 53 : 산화막51 gate 53 oxide film

본 발명은 반도체소자의 트랜지스터 형성방법에 관한 것으로, 특히 게이트의 채널 증가를 위해 게이트의 하부구조를 계단형 형성하는 기술에 관한 것이다. The present invention relates to a method of forming a transistor of a semiconductor device, and more particularly, to a technique of stepwise forming a substructure of a gate for increasing a channel of a gate.

일반적으로, 계단형 게이트 구조는 계단형으로 채널을 형성하여 채널 길이 확보가 용이하지만, 마스크의 오정렬시 트랜지스터의 문턱전압이 불균일하게 되어 소자의 특성이 열화된다. In general, the stepped gate structure is easy to secure the channel length by forming the channel in a stepped shape, but the threshold voltage of the transistor is uneven when the mask is misaligned, deteriorating the characteristics of the device.

도 1 은 종래기술에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단면도로서, 도 2 는 상기 도 1 의 형성공정 중에 마스크 오정렬로 인하여 게이트가 오정렬되어 형성된 것을 도시한 단면도이다. 1 is a cross-sectional view illustrating a transistor forming method of a semiconductor device according to the prior art, and FIG. 2 is a cross-sectional view illustrating a gate misalignment due to mask misalignment during the formation process of FIG. 1.

도 1을 참조하면, 반도체기판(11)에 트렌치형 소자분리막(13)을 형성한다. 이때, 상기 트렌치형 소자분리막(13)은 반도체기판(11) 상에 패드절연막을 형성하고 소자분리 마스크를 이용한 사진식각공정으로 상기 패드절연막 및 일정두께의 반도체기판을 식각한 다음, 이를 매립하는 산화막을 형성하고 상기 패드절연막을 제거함으로써 형성한 것이다. Referring to FIG. 1, a trench type isolation layer 13 is formed on a semiconductor substrate 11. In this case, the trench type isolation layer 13 may form a pad insulating layer on the semiconductor substrate 11 and etch the pad insulating layer and the semiconductor substrate having a predetermined thickness by a photolithography process using an element isolation mask, and then bury the oxide layer. And by removing the pad insulating film.

그 다음, 활성영역에 형성되는 게이트의 하부구조가 계단형으로 형성되도록 형성할 수 있는 별도의 노광마스크를 이용하여 상기 반도체기판(11) 및 소자분리막(13)을 식각한다. Next, the semiconductor substrate 11 and the device isolation layer 13 are etched using a separate exposure mask that can be formed so that the lower structure of the gate formed in the active region has a stepped shape.

전체표면상부에 게이트산화막(15), 폴리실리콘층(17), 게이트용 금속층(19) 및 하드마스크층(21)의 적층구조를 형성한다. A lamination structure of the gate oxide film 15, the polysilicon layer 17, the gate metal layer 19 and the hard mask layer 21 is formed on the entire surface.

그 다음, 게이트 마스크(미도시)를 이용한 사진식각공정으로 상기 적층구조를 식각하여 게이트를 형성한다. Next, the stack structure is etched by a photolithography process using a gate mask (not shown) to form a gate.                         

그리고, 상기 게이트를 마스크로 하여 상기 반도체기판(11)에 불순물을 이온주입하여 소오스/드레인 접합영역(23)을 형성한다. The source / drain junction region 23 is formed by implanting impurities into the semiconductor substrate 11 using the gate as a mask.

상기 게이트 측벽에 절연막 스페이서(25)를 형성한다. 이때, 상기 게이트 패터닝 공정시 남은 게이트산화막(15)이 식각된다. An insulating film spacer 25 is formed on the sidewall of the gate. In this case, the gate oxide layer 15 remaining in the gate patterning process is etched.

도 2 는 상기 도 1 에서 상기 별도의 노광마스크 또는 게이트 마스크의 오정렬로 인하여 계단형 게이트를 형성하지 못하는 경우를 도시한 것이다. FIG. 2 illustrates a case in which a stepped gate cannot be formed due to misalignment of the separate exposure mask or gate mask in FIG. 1.

이상에 설명한 바와 같이 종래기술에 따른 반도체소자의 트랜지스터 형성방법은, 별도의 노광마스크에 의하여 형성된 계단형 활성영역에 게이트를 형성하는 경우 상기 별도의 노광마스크 또는 게이트 마스크의 오정렬로 인하여 계단형의 하부 구조를 갖지 못하는 게이트가 형성되고 상기 게이트를 이용한 이온주입공정으로 완성된 트랜지스터의 특성이 열화되고, 콘택공정시 비트라인 콘택영역과 저장전극 콘택영역의 단차로 인하여 기판이 손상될 수 있어 반도체소자의 특성 및 신뢰성이 저하되고 그에 따른 반도체소자의 고집적화가 어렵게 하는 문제점이 있다. As described above, in the method of forming a transistor of a semiconductor device according to the related art, when a gate is formed in a stepped active region formed by a separate exposure mask, the stepped lower part may be formed due to misalignment of the separate exposure mask or gate mask. A gate having no structure is formed, and characteristics of a transistor completed by an ion implantation process using the gate are deteriorated, and a substrate may be damaged due to a step difference between a bit line contact region and a storage electrode contact region during a contact process. There is a problem in that the characteristics and reliability are degraded, and thus high integration of the semiconductor device is difficult.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 비트라인 콘택영역을 먼저 형성하고 이를 매립하는 절연막을 형성한 다음, 상기 절연막과의 식각선택비 차이를 이용하여 저장전극 콘택영역을 식각하여 기판의 손상을 최소화시킬 수 있도록 자기정렬적으로 게이트를 형성하는 반도체소자의 트랜지스터 형성방법을 제공하는데 그 목적이 있다. In order to solve the above problems of the prior art, the bit line contact region is first formed and an insulating layer filling the gap is formed. Then, the storage electrode contact region is etched using the difference in etching selectivity from the insulating layer. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a transistor of a semiconductor device in which gates are formed in a self-aligned manner so as to minimize damages.

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 트랜지스터 형성방법은, In order to achieve the above object, a method of forming a transistor of a semiconductor device according to the present invention,

반도체기판 상의 비트라인 콘택영역에 희생막 패턴을 형성하는 공정과,Forming a sacrificial film pattern in the bit line contact region on the semiconductor substrate;

상기 희생막 패턴의 측벽에 스페이서를 형성하는 공정과,Forming a spacer on sidewalls of the sacrificial layer pattern;

상기 스페이서 및 희생막 패턴을 마스크로 하는 식각공정으로 트렌치를 형성하는 공정과,Forming a trench by an etching process using the spacer and the sacrificial layer pattern as a mask;

상기 스페이서를 제거하고 상기 반도체기판에 문턱전압용 불순물을 이온주입하는 공정과,Removing the spacers and ion implanting impurities for a threshold voltage into the semiconductor substrate;

상기 희생막 패턴 사이의 반도체기판 상부를 매립하는 게이트산화막, 폴리실리콘층 및 게이트용 금속층의 적층구조를 형성하는 공정과,Forming a lamination structure of a gate oxide film, a polysilicon layer, and a gate metal layer to fill an upper portion of the semiconductor substrate between the sacrificial film patterns;

상기 구조물 상에 하드마스크층을 패터닝하는 공정과,Patterning a hard mask layer on the structure;

상기 하드마스크층을 마스크로 하여 하부구조물을 식각하여 게이트를 형성하는 공정을 포함하는 것과,Etching a lower structure using the hard mask layer as a mask to form a gate;

상기 희생막 패턴은 절연막을 형성하고 그 측벽의 스페이서는 폴리실리콘이나 절연막으로 형성하는 것과,The sacrificial layer pattern forms an insulating layer and the spacers on the sidewalls are formed of polysilicon or an insulating layer;

상기 희생막 패턴은 적어도 비트라인 콘택 영역의 CD와 같거나 크게 디자인된 비트라인 콘택마스크를 이용하여 형성하는 것과,The sacrificial layer pattern may be formed using a bit line contact mask designed to be at least equal to or larger than a CD of the bit line contact region.

상기 게이트산화막, 폴리실리콘층 및 게이트용 금속층의 적층구조는 게이트산화막의 형성 공정후 폴리실리콘층을 증착하고 에치백한 다음, 게이트용 금속층을 증착하고 평탄화식각하여 형성한 것임을 특징으로 한다. The stack structure of the gate oxide layer, the polysilicon layer, and the gate metal layer may be formed by depositing and etching back the polysilicon layer after the gate oxide film forming process, and then depositing and planarizing the gate metal layer.                     

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3f 는 본 발명의 실시예에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단면도이다. 3A to 3F are cross-sectional views illustrating a method of forming a transistor of a semiconductor device according to an embodiment of the present invention.

도 3a를 참조하면, 반도체기판(31)에 트렌치형 소자분리막(33)을 형성한다. 이때, 상기 트렌치형 소자분리막(33)은 반도체기판(31) 상에 패드절연막을 형성하고 소자분리 마스크를 이용한 사진식각공정으로 상기 패드절연막 및 일정두께의 반도체기판을 식각한 다음, 이를 매립하는 산화막을 형성하고 상기 패드절연막을 제거함으로써 형성한 것이다. Referring to FIG. 3A, a trench type isolation layer 33 is formed on the semiconductor substrate 31. In this case, the trench type isolation layer 33 forms a pad insulating layer on the semiconductor substrate 31 and etches the pad insulating layer and the semiconductor substrate having a predetermined thickness by a photolithography process using an element isolation mask, and then embeds the oxide layer to embed the pad insulating layer. And by removing the pad insulating film.

그 다음, 반도체기판(31) 상에 희생막(미도시)을 전체표면상부에 형성하고 이를 비트라인 콘택마스크(미도시)를 이용한 사진식각공정으로 식각하여 희생막 패턴(35)을 형성한다. 이때, 상기 희생막은 절연막으로 형성한다. Next, a sacrificial layer (not shown) is formed on the entire surface of the semiconductor substrate 31, and the sacrificial layer pattern 35 is formed by etching the photolithography process using a bit line contact mask (not shown). In this case, the sacrificial film is formed of an insulating film.

여기서, 상기 비트라인 콘택마스크는 적어도 비트라인 콘택 영역과 같은 CD를 같거나 크게 디자인된 것이다. Here, the bit line contact mask is designed to be at least equal to or larger than the same CD as the bit line contact region.

그 다음, 상기 희생막 패턴(35)의 측벽에 스페이서(37)를 형성한다. 이때, 스페이서(37)는 절연막이나 폴리실리콘으로 형성한다. Next, spacers 37 are formed on sidewalls of the sacrificial layer pattern 35. At this time, the spacer 37 is formed of an insulating film or polysilicon.

그 다음, 상기 희생막패턴(35) 및 스페이서를 마스크로 하여 상기 반도체기판(31)을 식각하여 소정깊이의 트렌치(39)를 형성한다. 이때, 상기 트렌치(39)는 활성영역의 게이트 영역이나 저장전극 콘택영역에 형성된다. Next, the semiconductor substrate 31 is etched using the sacrificial layer pattern 35 and the spacer as a mask to form a trench 39 having a predetermined depth. In this case, the trench 39 is formed in the gate region or the storage electrode contact region of the active region.

도 3b를 참조하면, 상기 스페이서(37)를 제거하고 상기 희생막패턴(35)을 마스크로 하여 상기 반도체기판(31)에 문턱전압 조절용 불순물을 임플란트한다. Referring to FIG. 3B, the spacer 37 is removed and an impurity for adjusting the threshold voltage is implanted into the semiconductor substrate 31 using the sacrificial layer pattern 35 as a mask.                     

도 3c를 참조하면, 상기 반도체기판(31) 표면에 게이트산화막(43)을 형성하고 상기 트렌치(39)를 포함한 전체표면상부에 폴리실리콘층(45)을 증착한다. Referring to FIG. 3C, a gate oxide layer 43 is formed on a surface of the semiconductor substrate 31, and a polysilicon layer 45 is deposited on the entire surface including the trench 39.

그 다음, 상기 폴리실리콘층(45)을 에치백하여 상기 희생막패턴(35)보다 낮게 형성하고 전체표면상부에 게이트 금속층(47)을 증착한다. Next, the polysilicon layer 45 is etched back to be lower than the sacrificial film pattern 35 and the gate metal layer 47 is deposited on the entire surface.

그리고, 상기 게이트 금속층(47)을 평탄화식각하여 상기 희생막 패턴(35)과 같은 높이로 형성한다. 이때, 상기 평탄화식각 공정은 화학기계연마 ( chemical mechanical polishing ) 공정으로 실시한 것이다. The gate metal layer 47 is planarized to be formed at the same height as the sacrificial layer pattern 35. In this case, the planarization etching process is performed by a chemical mechanical polishing process.

도 3d 및 도 3e 를 참조하면, 상기 구조물 상부에 하드마스크용 질화막(미도시)을 형성한다.3D and 3E, a nitride layer for hard mask (not shown) is formed on the structure.

그 다음, 게이트 마스크(미도시)를 이용한 사진식각공정으로 상기 하드마스크용 질화막, 게이트 금속층(47), 폴리실리콘층(45) 및 희생막패턴(35)을 식각하여 상측에 하드마스크층(49)이 형성된 게이트(51)를 형성한다.Next, the hard mask nitride layer, the gate metal layer 47, the polysilicon layer 45, and the sacrificial layer pattern 35 are etched by a photolithography process using a gate mask (not shown). Gate 51 is formed.

이때, 상기 비트라인 콘택 영역에 위치하는 게이트(51)의 측벽에는 상기 희생막패턴(35) 재료인 절연막이 소정두께 남는다. In this case, an insulating layer, which is a material of the sacrificial layer pattern 35, remains on a sidewall of the gate 51 positioned in the bit line contact region.

그 다음, 산화공정으로 상기 게이트(51)의 측벽에 산화막(53)을 형성한다.Next, an oxide film 53 is formed on the sidewall of the gate 51 by an oxidation process.

도 3f를 참조하면, 상기 게이트(51) 측벽에 절연막 스페이서(55)를 형성한다. 이때, 상기 절연막 스페이서(55)는 절연막인 질화막을 소정두께 증착하고 이를 이방성 식각하여 형성한다. 상기 이방성 식각공정은 과도식각을 수반하여 상기 게이트(51) 사이의 반도체기판(31)을 완전히 노출시킨다. Referring to FIG. 3F, an insulating film spacer 55 is formed on sidewalls of the gate 51. In this case, the insulating film spacer 55 is formed by depositing a nitride film, which is an insulating film, by anisotropic etching. The anisotropic etching process involves over-etching to completely expose the semiconductor substrate 31 between the gates 51.

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 트랜지스터 형성방법은, 자기정렬적인 식각공정을 이용하여 트렌치를 형성하고, 비트라인 콘택 영역에 절연막을 형성하고 이를 이용하여 저장전극 콘택 영역 식각시 기판의 손상없이 실시할 수 있으며, 후속 공정으로 형성된 게이트의 하부구조를 계단형으로 형성할 수 있어 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.  As described above, in the method of forming a transistor of the semiconductor device according to the present invention, a trench is formed by using a self-aligned etching process, an insulating film is formed in the bit line contact region, and the substrate is used to etch the storage electrode contact region by using the same. It can be carried out without damage, and the lower structure of the gate formed by the subsequent process can be formed in a step shape, thereby providing an effect of enabling high integration of the semiconductor device.

Claims (4)

반도체기판 상의 비트라인 콘택영역에 희생막 패턴을 형성하는 공정과,Forming a sacrificial film pattern in the bit line contact region on the semiconductor substrate; 상기 희생막 패턴의 측벽에 스페이서를 형성하는 공정과,Forming a spacer on sidewalls of the sacrificial layer pattern; 상기 스페이서 및 희생막 패턴을 마스크로 하는 식각공정으로 트렌치를 형성하는 공정과,Forming a trench by an etching process using the spacer and the sacrificial layer pattern as a mask; 상기 스페이서를 제거하고 상기 반도체기판에 문턱전압용 불순물을 이온주입하는 공정과,Removing the spacers and ion implanting impurities for a threshold voltage into the semiconductor substrate; 상기 희생막 패턴 사이의 반도체기판 상부를 매립하는 게이트산화막, 폴리실리콘층 및 게이트용 금속층의 적층구조를 형성하는 공정과,Forming a lamination structure of a gate oxide film, a polysilicon layer, and a gate metal layer to fill an upper portion of the semiconductor substrate between the sacrificial film patterns; 상기 구조물 상에 하드마스크층을 패터닝하는 공정과,Patterning a hard mask layer on the structure; 상기 하드마스크층을 마스크로 하여 하부구조물을 식각하여 게이트를 형성하는 공정을 포함하는 반도체소자의 트랜지스터 형성방법.And forming a gate by etching a lower structure using the hard mask layer as a mask. 제 1 항에 있어서, The method of claim 1, 상기 희생막 패턴은 절연막을 형성하고 그 측벽의 스페이서는 폴리실리콘이나 절연막으로 형성하는 것을 특징으로 하는 반도체소자의 트랜지스터 형성방법.And wherein the sacrificial film pattern forms an insulating film and the spacers on the sidewalls are formed of polysilicon or an insulating film. 제 1 항에 있어서, The method of claim 1, 상기 희생막 패턴은 적어도 비트라인 콘택 영역의 CD와 같거나 크게 디자인 된 비트라인 콘택마스크를 이용하여 형성한 것임을 특징으로 하는 반도체소자의 트랜지스터 형성방법.And the sacrificial layer pattern is formed using a bit line contact mask designed to be at least equal to or larger than a CD of the bit line contact region. 제 1 항에 있어서, The method of claim 1, 상기 게이트산화막, 폴리실리콘층 및 게이트용 금속층의 적층구조는 게이트산화막의 형성 공정후 폴리실리콘층을 증착하고 에치백한 다음, 게이트용 금속층을 증착하고 평탄화식각하여 형성한 것임을 특징으로 하는 반도체소자의 트랜지스터 형성방법.The stack structure of the gate oxide layer, the polysilicon layer, and the gate metal layer is formed by depositing and etching back the polysilicon layer after forming the gate oxide layer, and then depositing and planarizing the gate metal layer. Transistor Formation Method.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101010482B1 (en) * 2008-06-26 2011-01-21 주식회사 동부하이텍 Semiconductor device and method for fabricating the same
KR20110084727A (en) * 2010-01-18 2011-07-26 삼성전자주식회사 Semiconductor interconnection structure, semiconductor device comprising the semiconductor interconnection structure, and semiconductor module comprising the semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101010482B1 (en) * 2008-06-26 2011-01-21 주식회사 동부하이텍 Semiconductor device and method for fabricating the same
KR20110084727A (en) * 2010-01-18 2011-07-26 삼성전자주식회사 Semiconductor interconnection structure, semiconductor device comprising the semiconductor interconnection structure, and semiconductor module comprising the semiconductor device

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