JP2010021240A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device for reducing an etching amount of a cover film which occurs in the other conductive region at the time of forming a transistor giving stress distortion on a channel region. <P>SOLUTION: In the manufacturing method of the semiconductor device, a semiconductor substrate 1 where a gate insulating film 2, a gate electrode 3 and a sidewall 5 are formed on an upper face is prepared. The cover film 7 is formed on the semiconductor substrate 1 and a photoresist film 8 is formed on the cover film 7 in a first conduction-type transistor forming region. The cover film 7 in a second conduction-type transistor forming region is etching-removed. Then, a first groove 10 is formed in the second conduction-type transistor forming region by the same etching device. The photoresist film 8 is removed, isotropic etching is performed and a second groove 11 is formed. A semiconductor material whose lattice constant differs from that of the semiconductor substrate 1 is buried in the second groove 11, and a source-drain region 6 is formed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a configuration that applies stress strain to a channel region.

  Conventionally, in the development of a system LSI after the 45 nm process, formation of a transistor that applies stress to the channel region has been studied. This utilizes the characteristic that the mobility of carriers changes when the semiconductor substrate receives stress strain. As one technique for applying this stress strain, an e-SiGe (embedded SiGe) technique has been developed by each SoC manufacturer. The e-SiGe technology is a structure in which, after forming a sidewall, the Si substrate is isotropically etched using the sidewall and the gate electrode as a mask, and SiGe is epitaxially grown there. With this configuration, a compressive stress is applied to the channel portion of the transistor from the difference in lattice constant, and the driving capability is improved.

  Generally, it is known that when compressive stress is applied to the channel region of the Pch transistor and tensile stress is applied to the channel region of the Nch transistor, the performance of the MOS transistor is improved. That is, the method of applying compressive stress by embedding SiGe as the source / drain regions is not effective for the Nch transistor and is applied only to the Pch transistor region.

  7 to 10 are views showing a conventional method for manufacturing a semiconductor device having a configuration in which stress strain is applied to a channel region. First, a gate insulating film 2 and a gate electrode 3 using a poly-Si material are formed on a semiconductor substrate 1. Here, when poly-Si of the gate electrode 3 is patterned, etching is performed using the mask 4 of oxide film or nitride film, and a photoresist mask is not used. The reason is that SiGe epitaxial growth, which will be described later, is not generated on the poly-Si that is the gate electrode 3.

  Then, after forming several thin sidewalls (two layers in the example shown in the figure) with a nitride film, an NSG oxide film, etc., a sidewall of the nitride film (SiN film) is formed (FIG. 7). Such multiple layers of sidewalls 5 are used to finely control the profile of the implanted species by performing implantation using each sidewall as a mask.

  Next, a cover film 7 (for example, an oxide film) is formed on the semiconductor substrate, and a photoresist film 8 is formed on the cover film 7 in the Nch transistor formation region. Next, etching is performed using the photoresist film 8 as a mask to remove the cover film 7 in the Pch transistor formation region (FIG. 8). This is because the e-SiGe method is effective only for the Pch transistor, and therefore Nch is desired to be protected by the cover film 7. Next, the photoresist film 8 is removed, and the Si substrate 1 is etched isotropically using the gate after forming the sidewalls as a mask to form grooves (FIG. 9). Thereafter, SiGe is deposited in the trench and epitaxially grown to form a semiconductor device having stress strain (FIG. 10).

  There is a difference in lattice constant between SiGe and Si substrate 1, and since SiGe is slightly larger, distortion occurs, and as a result, stress acts in a compressing direction with respect to the direction from the source to the drain of the channel portion. Here, it is considered that the isotropic etching shape works effectively for applying strain. As a result, the driving capability of the PchMOS transistor is improved. Technologies related to this are disclosed in the following patent documents.

US Pat. No. 6,861,318 US Pat. No. 7,118,952

  However, in the manufacturing method described above, the cover film formed in the Nch transistor region during the isotropic etching process for forming the groove in the Si substrate is also etched. When the cover film disappears by etching, the protective film in the Nch portion disappears, and there is a problem that SiGe is deposited also in the Nch region in the subsequent source / drain region forming step.

  Accordingly, the present invention has been made to solve such a problem, and a cover film generated in another conductivity type region when a transistor having a structure that applies stress strain to the channel region is formed in one conductivity type region. An object of the present invention is to obtain a method of manufacturing a semiconductor device capable of reducing the etching amount.

  A method of manufacturing a semiconductor device according to an embodiment of the present invention first has a first conductivity type transistor formation region and a second conductivity type transistor formation region, and a gate insulating film and a gate are formed on the upper surface of each of these regions. A semiconductor substrate on which electrodes and sidewalls are formed is prepared. Next, a cover film is formed on the semiconductor substrate, and a photoresist film is formed on the cover film in the first conductivity type transistor formation region. Next, using the photoresist film as a mask, the cover film in the second conductivity type transistor formation region is removed by etching, and the photoresist film, the gate electrode and the sidewall in the second conductivity type transistor formation region are further removed with the same etching apparatus. By etching as a mask, a first groove is formed in the semiconductor substrate in the second conductivity type transistor formation region. Next, the photoresist film is removed, and isotropic etching is performed on the region where the first groove is formed using the gate electrode and the side wall of the second conductivity type transistor formation region as a mask to form the second groove. To do. Finally, a semiconductor material having a lattice constant different from that of the semiconductor substrate is embedded in the second groove to form source / drain regions.

  According to an embodiment of the present invention, the etching time in the Si isotropic etching process in which the cover film is etched can be reduced. Can be realized.

  First, as a premise of the embodiment of the present invention, a conventional method for manufacturing a semiconductor device will be described. As described above, when a transistor having a structure that applies stress strain to the channel region is formed in one conductivity type region, the cover film is etched in the other conductivity type region. FIG. 11 is a diagram showing a state in which the cover film 7 has disappeared in the Nch transistor region. As shown in the drawing, after the cover film 7 disappears, the Si etching proceeds, so the Si substrate 1 is also etched to some extent. As a material for the cover film 7, an oxide film is often used. However, since a high temperature cannot be applied to a wafer recently because of device requirements, a non-dense oxide film (NSG: non-dope sillicate) formed at a low temperature. glass)). Such a dense film has a high etching rate and a high risk of disappearance.

  FIG. 12 is a diagram illustrating a configuration of a semiconductor device in which the cover film 7 is formed thick as a countermeasure against disappearance of the cover film 7. However, as shown in the figure, the cover film 7 is buried in the narrow space between the gates as indicated by the double-headed arrow, so that the effective film thickness is increased and it is difficult to remove the cover film 7 during etching. End up. FIG. 13 is a diagram showing a configuration of a semiconductor device in which Si isotropic etching is performed as it is after etching the cover film 7 using the photoresist film 8 as a mask as a countermeasure against disappearance of the cover film 7. However, as shown in the drawing, there is a problem that impurities contained in the resist remain on the Si outermost surface after etching, and there is a concern about adverse effects on the device.

  Therefore, in the embodiment of the present invention, when a transistor having a structure that applies stress strain to the channel region is formed in one conductivity type region, the etching amount of the cover film generated in the other conductivity type region is reduced. A method of manufacturing a semiconductor device that can be used will be described. In each figure, the same code | symbol is abbreviate | omitted description as the same or substantially the same structure.

<Embodiment 1>
1 to 6 are views showing a method of manufacturing a semiconductor device in an embodiment of the present invention. FIG. 6 is a diagram showing a configuration of the semiconductor device after forming a transistor that applies stress strain to the channel region. The semiconductor device according to the present invention is a CMOS transistor configured by combining a Pch transistor region 20 and an Nch transistor region 30 on a silicon substrate 1. In this embodiment mode, a Pch transistor is used as a transistor having a structure in which stress strain is applied to a channel region, and a structure of a semiconductor device is described below with reference to FIGS.

  The semiconductor device in the present embodiment includes a Si substrate 1, a gate insulating film 2 formed on the Si substrate 1, a gate electrode 3 formed on the gate insulating film 2, a mask 4 formed on the gate electrode 3, Sidewalls 5 formed on the side surfaces of the gate insulating film 2 and the gate electrode 3 (in this embodiment, three layers including the first sidewall 5a, the second sidewall 5b, and the third sidewall 5c) A side wall 5 is used), and a source / drain region 6 formed on a surface layer of the Si substrate 1 and adjacent to the side wall 5 is provided.

  Here, the semiconductor material of the source / drain region 6 is distorted by using a material having a lattice constant different from that of Si, and as a result, stress acts on the channel portion. In the Pch transistor in the present embodiment, SiGe is used for the source / drain region 6. In SiGe and Si, since the lattice constant of SiGe is slightly larger, distortion occurs, and as a result, stress acts in a compressing direction with respect to the direction from the source to the drain of the channel portion.

  Next, with reference to FIGS. 1 to 6, a method for manufacturing a semiconductor device in the present embodiment will be described. First, the gate insulating film 2 and the gate electrode 3 are formed on the silicon substrate 1. Next, a mask 4 is formed on the gate electrode 3 and patterned. Next, several thin sidewalls are formed on the side surface of the gate electrode 3 with a nitride film, an NSG oxide film, or the like. In the present embodiment, two layers of sidewalls are formed: a first sidewall 5a made of a nitride film and a second sidewall 5b made of an NSG oxide film. After forming a thin sidewall, a third sidewall 5c made of a nitride film (SiN film) is formed (FIG. 1).

  Next, a cover film 7 (for example, an oxide film such as NSG) is formed on the semiconductor substrate on which the Si substrate 1, the gate electrode 3, and the sidewalls 5 are formed. At this time, the NSG film thickness is 10 nm. Next, a photoresist film 8 is formed on the cover film 7 in the Nch transistor region 30 (FIG. 2). Using this photoresist film 8 as a mask, dry etching is performed to remove the cover film 7 only in the Pch transistor region 20 (FIG. 3). Subsequently, using the same etching apparatus, dry etching is performed using the photoresist film 8, the gate electrode 3 and the sidewalls 5 as a mask to form the first groove 10 in the Pch transistor region 20 (FIG. 4). For example, the following are used as an etching apparatus and etching conditions. In step 1, NSG is etched, and in step 2, Si is etched.

The etching apparatus uses a parallel plate type RIE (Riactive Ion Etcher). The conditions of step 1 are C ₄ F ₈ / O ₂ / Ar = 7/7/500 sccm, RF (top / bottom) = 1500 W / 100 W, 2.7 Pa, 0 ° C., 15 sec. Further, the conditions of step ₂ are CHF ₃ / O ₂ / Ar = 50/20/400 scm, RF (top / bottom) = 1000/100 W, 2.7 Pa, 30 sec.

  The etching rate (E / R) of the NSG film in step 1 is 80 nm / min. Since the above 15 sec is an etching equivalent to 20 nm of the NSG film, 10 nm of NSG disappears. At this time, the Si substrate 1 is hardly etched. The E / R (Si) of step 2 is 45 nm / min. Accordingly, the Si substrate 1 is etched by about 20 nm in 30 seconds. The first groove 10 shown in FIG. 4 shows the state at this time.

  Next, the resist is removed by ashing + wet processing, and thereafter, using the gate electrode 3 and the sidewall 5 as a mask, Si isotropic etching is performed on the region of the first groove 10 to form the second groove 11 (FIG. 5). For example, the following is used as an isotropic etching apparatus and etching conditions.

As the etching apparatus, a remote plasma type isotropic etching apparatus is used. Etching conditions are CF ₄ / O ₂ = 360/40 scm, μ wave = 400 W, 50 Pa, and 20 ° C. The performance under this isotropic etching condition is as follows: E / R (Si) = 150 nm / min, E / R (NSG) = 22 nm / min, selectivity (Si / NSG) = 6.8 (selection ratio = E / R) Ratio).

  This condition is a condition in which a good isotropic etching shape is obtained in Si etching, and the difference between etching depth patterns is small. In calculation, when Si is etched by 60 nm which is the current target value, the NSG film is etched by 9 nm. That is, there is almost no NSG disappearance margin and it disappears depending on the location. On the other hand, the Si etching amount in Si isotropic etching can be reduced to 40 nm by etching the Si substrate 1 by 20 nm in the NSG etching process. Since the NSG film etching amount at this time is 6 nm by calculation, the possibility of disappearance of NSG is almost eliminated even if a margin is considered.

  Thereafter, SiGe is buried in the second trench 11 and epitaxially grown to form the source / drain regions 6, whereby the semiconductor device shown in FIG. 6 is formed. Here, there is a difference in lattice constant between SiGe and Si. Since SiGe is slightly larger, distortion occurs, and as a result, stress acts in a compressing direction with respect to the direction from the source to the drain of the channel portion.

  As described above, according to the manufacturing method of the semiconductor device in the present embodiment, the etching amount in the Si isotropic etching process can be reduced by simultaneously etching the Si substrate 1 when the cover film 7 is etched. The disappearance of the cover film 7 can be prevented. Thereby, the embedded SiGe process can be stably produced.

  The present invention is applicable to system LSI products of the 45-32 nm generation and later.

It is the figure which showed the manufacturing method of the semiconductor device in embodiment of this invention. It is the figure which showed the manufacturing method of the semiconductor device in embodiment of this invention. It is the figure which showed the manufacturing method of the semiconductor device in embodiment of this invention. It is the figure which showed the manufacturing method of the semiconductor device in embodiment of this invention. It is the figure which showed the manufacturing method of the semiconductor device in embodiment of this invention. It is the figure which showed the manufacturing method of the semiconductor device in embodiment of this invention. It is the figure which showed the manufacturing method of the conventional semiconductor device. It is the figure which showed the manufacturing method of the conventional semiconductor device. It is the figure which showed the manufacturing method of the conventional semiconductor device. It is the figure which showed the manufacturing method of the conventional semiconductor device. It is the figure which showed the problem in the manufacturing method of the conventional semiconductor device. It is the figure which showed the problem in the manufacturing method of the conventional semiconductor device. It is the figure which showed the problem in the manufacturing method of the conventional semiconductor device.

Explanation of symbols

  1 Si substrate, 2 gate insulating film, 3 gate electrode, 4 mask, 5 sidewall, 5a first sidewall, 5b second sidewall, 5c third sidewall, 6 source / drain region, 7 cover film 8 photoresist film, 10 first groove, 11 second groove, 20 Pch transistor region, 30 Nch transistor region.

Claims (1)

(A) A semiconductor substrate having a first conductivity type transistor formation region and a second conductivity type transistor formation region and having a gate insulating film, a gate electrode, and a sidewall formed on the upper surface of each region is prepared. Process,
(B) forming a cover film on the semiconductor substrate;
(C) forming a photoresist film on the cover film in the first conductivity type transistor formation region;
(D) Using the photoresist film as a mask, the cover film in the second conductivity type transistor formation region is removed by etching, and the photoresist film and the gate of the second conductivity type transistor formation region are further removed with the same etching apparatus. Forming a first groove in the semiconductor substrate in the second conductivity type transistor formation region by etching using an electrode and a sidewall as a mask;
(E) after the step (d), removing the photoresist film;
(F) After the step (e), isotropic etching is performed on the region where the first groove is formed by using the gate electrode and the side wall of the second conductivity type transistor formation region as a mask. Forming a groove;
(G) A method of manufacturing a semiconductor device comprising: burying a semiconductor material having a lattice constant different from that of the semiconductor substrate in the second groove to form a source / drain region.

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