JP2009026795A - Semiconductor apparatus and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor apparatus which can be more improved in carrier mobility. <P>SOLUTION: The semiconductor apparatus includes a side wall 5b formed in an L shape in side elevation view to cover a flank of a gate 3 and an extension area 6a of a source/drain 6, a silicide layer 7 formed on the gate 3 and on a contact area 6b of the source/drain 6, and a stress liner film 8 formed to cover the side wall 5b and the silicide layer 7, where the contact area 6b of the source/drain 6 is formed of a semiconductor raw material (SiGe) having larger grid intervals than a semiconductor raw material (Si) of a semiconductor substrate 1 and the stress liner film 8 is a compression type, or the contact area 6b of the source/drain 6 is formed of a semiconductor raw material (SiC) having smaller grid intervals than the semiconductor raw material (Si) of the semiconductor substrate 1 and the stress liner film 8 is an extension type. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a technique for improving carrier mobility of a fine MOS transistor.

  In order to improve the carrier mobility of a fine MOS transistor, intentionally applying strain to the channel region is a very effective method, and various types of strain forming methods have been proposed so far. Among the proposed methods, there are the following (1) and (2).

(1) Source / Drain—SiGe selective epi Si in the region where the source / drain is formed in the Si substrate is recessed, and Si _1-x Ge _x having a larger lattice spacing than Si is selectively epitaxially grown there. / Drain is formed, and the uniaxial compressive strain is applied to the channel region by the source / drain. If Si _1-x C _x is applied instead of Si _1-x Ge _x , tensile strain can be applied to the channel region.

(2) Disposable sidewall After siliciding the gate and source / drain and removing the sidewall by dry etching, a highly stressed stress liner film is formed so as to cover the gate and source / drain, By this stress liner film, uniaxial compressive strain is applied to the channel region. At this time, by removing the sidewalls as described above, the stress liner film is further adhered to the gate and the source / drain, and the effect of uniaxial distortion of the channel region by the stress liner film can be enhanced. Incidentally, by changing the material type of the stress liner film, it is possible to add compressive strain and tensile strain to the channel region.

  When the above (1) and (2) are combined, the carrier mobility can be further improved. However, since the following problems actually occur, the above (1) and (2) cannot be combined (that is, the carrier mobility is reduced). It couldn't be improved further).

That is, since the selective epitaxial growth of SiGe in the above (1) needs to occur only at the source / drain, it is necessary to prevent the selective epitaxial growth of SiGe from occurring on the gate. Therefore, during the selective epitaxial growth of SiGe in the above (1), a hard mask (previously, this hard mask is formed of an oxide film (SiO ₂ ) for preventing the selective epitaxial growth of SiGe on the gate. It is necessary to form.

However, in such a case, in the above (2), the hard mask becomes an obstacle and the gate cannot be silicided. Therefore, in order to silicide the gate, it is necessary to remove the hard mask before silicidation. For removing the mask, wet etching using hydrofluoric acid is used. Since the hard mask is the same oxide film as the element isolation film (SiO ₂ ), the element isolation film is melted and dropped when the mask is removed. There was a problem that damage occurred. Further, since the sidewall is completely removed, there is a problem that the extension region of the source / drain is damaged at the time of the removal.

  SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can further improve carrier mobility as compared with the prior art.

  In order to solve the above problems, a first embodiment of the present invention includes a semiconductor substrate, a gate formed on the semiconductor substrate, a source / drain formed on the semiconductor substrate, a side surface of the gate, A sidewall formed in an L-shaped cross-section in a side view so as to cover the extension region of the source / drain; a silicide layer formed on the gate and the contact region of the source / drain; A stress liner film formed so as to cover the gate and the source / drain via the silicide layer, and the contact region of the source / drain has a larger lattice spacing than the semiconductor material of the semiconductor substrate The stress liner film is formed of a first semiconductor material and is a compression type, or the saw / The contact region of the drain is of the than the semiconductor substrate of the semiconductor material is formed by a small second semiconductor material having lattice spacing and the stress liner film is a tension type.

  According to the first aspect of the present invention, the source / drain contact region is formed of the first semiconductor material having a larger lattice spacing than the semiconductor material of the semiconductor substrate, and the stress liner film is formed in a compression type. In this case, it is possible to apply compressive strain to the channel region from both the contact region and the stress liner film, thereby further improving carrier mobility in a P-type semiconductor device such as a P-type MOSFET.

  In addition, when the source / drain contact region is formed of the second semiconductor material having a smaller lattice spacing than the semiconductor material of the semiconductor substrate and the stress liner film is formed in a tension type, the contact region and the stress liner are formed. A tensile strain can be applied to the channel region from both the film and the carrier mobility can be further improved in an N-type semiconductor device such as an N-type MOSFET.

  Further, since the side wall is formed in an L shape in a side view, the stress liner film can be further adhered to the gate and the source / drain, thereby further enhancing the effect of uniaxial distortion of the channel region 9 by the stress liner film. Can do.

  Further, since the side wall is provided, the source / drain extension regions can be protected by the side wall in the manufacturing process.

Embodiment 1 FIG.
As shown in FIG. 1, the semiconductor device according to this embodiment includes a semiconductor substrate 1, a gate 3 formed on the semiconductor substrate 1, a source / drain 6 formed on the surface layer of the semiconductor substrate 1, and a gate 3. Side wall 5a formed in an L-shaped cross section in side view so as to cover the side surface of source and drain / extension region 6a, and silicide formed on gate 3 and contact region 6b of source / drain 6 A layer 7 and a stress liner film 8 formed so as to cover the gate 3 and the source / drain 6 via the sidewall 5a and the silicide layer 7 are provided. The gate 3 is composed of a gate insulating film 3a formed on the semiconductor substrate 1 and a gate electrode 3b formed thereon.

The semiconductor substrate 1 is, for example, a Si (silicon) substrate. The gate electrode 3b is made of, for example, polysilicon. The sidewall 5a is formed of an oxide film (for example, a silicon oxide film (SiO ₂ )).

  The contact region 6b of the source / drain 6 is formed of a semiconductor material (here, SiGe (silicon germanium)) having a larger lattice spacing than the semiconductor material (here, Si) of the semiconductor substrate 1. Thereby, uniaxial compressive strain is applied to the channel region 9 by the contact region 6b. The contact region 6b is formed with a thickness of 20 nm or more, for example.

  The silicide layer 7 is made of, for example, NiSi (nickel silicide).

  The stress liner film 8 is formed of a compression type nitride film (for example, SiN (silicon nitride)) that can apply uniaxial compressive strain to the channel region 9.

  According to the semiconductor device configured as described above, the contact region 6b of the source / drain 6 is formed of a semiconductor material (here, SiGe) having a larger lattice spacing than the semiconductor material (here, Si) of the semiconductor substrate 1. In addition, since the stress liner film 8 is formed of a compression type nitride film (for example, SiN) capable of applying a uniaxial compressive strain to the channel region 9, the contact region 6b and the stress liner film 8 are The compressive strain can be applied to the channel region 9 from both, and thereby carrier mobility can be further improved in a P-type semiconductor device such as a P-type MOSFET.

  Further, since the side wall 5a is formed in an L-shaped cross section when viewed from the side, the stress liner film 8 can be further adhered to the gate 3 and the source / drain 6 and thereby the uniaxial strain of the channel region 9 caused by the stress liner film 8 can be reduced. The effect can be further enhanced.

  Further, since the sidewall 5a is provided, the extension region 6a of the source / drain 6 can be protected by the sidewall 5a in the manufacturing process.

  Further, since the contact region 6b is formed with a thickness of 20 nm or more, for example, sufficient strain can be applied to the channel region 9.

  In this embodiment, the contact region 6b of the source / drain 6 is formed of a semiconductor material (here, SiC (silicon carbide)) having a lattice spacing smaller than that of the semiconductor material (here, Si) of the semiconductor substrate 1. Further, the stress liner film 8 may be formed of a tensile type nitride film (here, SiN) capable of applying a uniaxial tensile strain to the channel region 9. As a result, in an N-type semiconductor device such as an N-type MOSFET, carrier mobility (that is, current driving capability) can be further improved.

Embodiment 2. FIG.
In this embodiment, an outline of a manufacturing method (first manufacturing method) for manufacturing the semiconductor device of the first embodiment will be described.

  First, as shown in FIG. 2, an insulating film 3a for a gate insulating film and a polysilicon layer 3b for a gate electrode are sequentially deposited on a semiconductor substrate (here, Si substrate) 1, and a nitride film (for example, SiN (for example, SiN (for example)) is deposited thereon. The hard mask 14 made of silicon nitride)) is patterned. Then, the portions 3a and 3b are etched using the hard mask 14 as an etching mask, thereby forming the gate 3 as shown in FIG.

  As shown in FIG. 3, extension regions 6a of the source / drain 6 are formed in the surface layer of the semiconductor substrate 1 by ion implantation. The lower layer is made of a silicon oxide film (oxide film) 5a on the surface of the gate 3 so as to cover the side surface of the gate 3 and the upper surface of a necessary portion of the extension region 6a (the vicinity of the gate 3). Sidewalls 5 made of silicon nitride film (nitride film) 5b are formed. In this state, the silicon nitride film 5b has an L-shaped cross section in side view so as to cover the side surface of the gate 3 and the upper surface of the necessary portion of the extension region 6a.

  Then, as shown in FIG. 4, a region to be the contact region 6 b of the source / drain 6 in the semiconductor substrate 1 is recessed (groove) by Si etching, and the lattice is more latticed than the semiconductor material (Si) of the semiconductor substrate 1. A contact material 6b made of SiGe is formed by epitaxially growing a semiconductor material (here, SiGe) having a large interval to a position near the surface of the semiconductor substrate 1, for example. The contact region 6b is formed with a thickness of 20 nm or more, for example. Then, a silicon layer 15 is formed on the contact region 6b by continuously epitaxially growing pure silicon, for example, to a thickness similar to that of the hard mask 14.

  Then, as shown in FIG. 5, the hard mask 14 made of nitride film (SiN) and the silicon nitride film 5b on the sidewall 5 are removed by isotropic nitride film (SiN) dry etching. By this removal, only the lower silicon oxide film 5a remains as a sidewall (hereinafter referred to as sidewall 5a).

  In addition, since the selection ratio between SiN and Si is not so different at the time of removal, the silicon layer 15 is also shaved to a certain extent by the nitride film dry etching so that the silicon layer 15 has an appropriate thickness. It is formed to the same thickness as the hard mask 14). Then, the silicon layer 15 and the upper layer of the polysilicon gate electrode 3b are self-aligned and silicided to form the silicide layers 7 on the contact region 6 and the upper layer of the gate electrode 3b as shown in FIG. .

  Then, as shown in FIG. 6, a compressive stress liner film 8 is formed of, for example, a nitride film so as to cover the gate 3 and the source / drain 6 via the sidewall 5 and the silicide layer 7. In this manner, the semiconductor device of the first embodiment (semiconductor device when compressive strain is applied to the channel region 9) is manufactured.

According to the semiconductor device manufacturing method described above, the semiconductor device having the effects of the first embodiment can be manufactured, and the hard mask 14 is formed of a nitride film (that is, an element isolation film (SiO ₂ ) (FIG. Therefore, when the hard mask 14 is removed by etching, it is possible to prevent the element isolation film from melting and dropping due to the etching.

  Further, since the sidewall 5 is formed as a two-layer structure in which the lower layer is made of the silicon oxide film 5a and the upper layer is made of the silicon nitride film 5b, the lower layer silicon oxide film 5a is left by etching the nitride film, and the upper layer is formed. Only the silicon nitride film 5b can be appropriately removed.

  In addition, SiGe is used for forming the contact region 6b of the source / drain 6. However, since the silicon layer 15 is continuously formed on the contact region (ie, SiGe) 6b, the SiGe is exposed during the manufacturing process. This can prevent the scattering of Ge and prevent contamination of the production line. Further, since SiGe is not directly dry-etched, this can also prevent Ge from being scattered and contamination of the production line.

  Further, since isotropic nitride film dry etching is used, the silicon nitride film 5b and the hard mask 14 in the upper layer of the sidewall 5 can be appropriately removed.

Embodiment 3 FIG.
The manufacturing method of the semiconductor device according to this embodiment mainly uses a nitride film wet etching using phosphoric acid in place of the isotropic nitride film dry etching in the second embodiment. The hard mask 14 made of a film (SiN) and the silicon nitride film 5b in the upper layer of the side wall 5 are removed. Hereinafter, this embodiment will be described.

  First, as shown in FIG. 2, an insulating film 3a to be a gate insulating film and a polysilicon layer 3b to be a gate electrode are sequentially deposited on a semiconductor substrate (here, Si substrate) 1, and a nitride film (for example, SiN (for example, SiN (for example)) is deposited thereon. The hard mask 14 made of silicon nitride)) is patterned. Then, the portions 3a and 3b are etched using the hard mask 14 as a mask to form the gate 3 as shown in FIG.

  As shown in FIG. 3, extension regions 6a of the source / drain 6 are formed in the surface layer of the semiconductor substrate 1 by ion implantation. The lower layer is made of a silicon oxide film (oxide film) 5a on the surface of the gate 3 so as to cover the side surface of the gate 3 and the upper surface of a necessary portion of the extension region 6a (the vicinity of the gate 3). Sidewalls 5 made of silicon nitride film (nitride film) 5b are formed. In this state, the silicon nitride film 5b has an L-shaped cross section in side view so as to cover the side surface of the gate 3 and the upper surface of the necessary portion of the extension region 6a.

  Then, as shown in FIG. 7, a region to be the contact region 6 b of the source / drain 6 in the semiconductor substrate 1 is recessed (digged into a groove shape) by Si etching, and the groove is more than the semiconductor material (Si) of the semiconductor substrate 1. A contact region 6b made of SiGe is formed by epitaxially growing a semiconductor material having a large lattice spacing (here, SiGe) to a position near the surface of the semiconductor substrate 1, for example. Then, the silicon layer 15 is formed on the contact region 6b by continuously epitaxially growing pure silicon, for example, to a position slightly beyond the vicinity of the surface of the semiconductor substrate 1.

  Then, as shown in FIG. 5, the hard mask 14 made of nitride film (SiN) and the silicon nitride film 5b on the upper side of the sidewall 5 are removed by wet etching using phosphoric acid (SiN). By this removal, only the lower silicon oxide film 5a remains as a sidewall (hereinafter referred to as sidewall 5a). Then, the silicon layer 15 and the polysilicon gate electrode 3b are self-aligned and silicided to form silicide layers 7 on the contact regions 6 and on the gate electrode 3b, respectively, as shown in FIG. To do.

  Then, as shown in FIG. 6, a compressive stress liner film 8 is formed of, for example, a nitride film so as to cover the gate 3 and the source / drain 6 via the sidewall 5 and the silicide layer 7. In this manner, the semiconductor device of the first embodiment (semiconductor device when compressive strain is applied to the channel region 9) is manufactured.

  According to the semiconductor device manufacturing method described above, the same effects as those of the second embodiment can be obtained, and phosphoric acid can be used when the hard mask 14 made of nitride film and the silicon nitride film 5b on the sidewall 5 are removed. Since the nitride film wet etching using is used, it is possible to prevent the silicon layer 15 on the extension region 6a from being scraped during the removal. Therefore, it is not necessary to form the silicon layer 15 as thick as the hard mask 14 as in the second embodiment.

  In the second and third embodiments, the case where compressive strain is applied to the channel region 9 has been described. However, when tensile strain is applied to the channel region 9, the semiconductor material (Si) of the semiconductor substrate 1 is formed in the recessed groove 13. A semiconductor material (in this case, SiC) having a smaller lattice spacing than that may be epitaxially grown, and a tensile type may be formed as the stress liner film 8.

Embodiment 4 FIG.
In this embodiment, the semiconductor device manufacturing method of the second embodiment is applied to a logic circuit chip.

First, as shown in FIG. 8, an element isolation film (SiO ₂ ) 17 having a depth of about 300 nm is formed on a semiconductor substrate (here, Si substrate) 1 by a well-known method, and then well implantation is performed. Then, a silicon oxide film for the gate insulating film 3a is deposited on the entire upper surface of the semiconductor substrate 1 with a thickness of about 2 nm, and a polysilicon for the gate electrode 3b is deposited thereon with a thickness of about 100 nm. A silicon nitride film (nitride film) for the hard mask 14 is deposited on the top with a thickness of about 30 nm. Then, the silicon nitride film is patterned by lithography to form a hard mask 14, and the silicon oxide film and the polysilicon are etched using the hard mask 14 as an etching mask, whereby each MOSFET region P, N Then, the gate insulating film 3a and the gate electrode 3b are formed.

  Then, as shown in FIG. 9, BF2 ion implantation is performed only in the P-type MOSFET region P to form a P-type source / drain extension region 6ap. Similarly, As ion implantation is performed only in the N-type MOSFET region N. Then, an N-type source / drain extension region 6an is formed. Then, a silicon oxide film 5a serving as a lower layer of the sidewall 5 is deposited on the entire upper surface of the semiconductor substrate 1 to a thickness of about 100 nm, and a silicon nitride film 5b serving as a top layer of the sidewall 5 is deposited thereon to a thickness of about 300 nm. , Remove those unwanted parts. As a result, silicon oxide whose lower layer is L-shaped in cross section in side view is formed on these surfaces so as to cover the side surface of the gate 3 and the upper surface of the necessary portion of the extension region 6ap (6an) (the vicinity of the gate 3). A sidewall 5 made of the film 5a and having an upper layer made of the silicon nitride film 5b is formed.

Then, a photoresist (not shown) is formed on the semiconductor substrate 1 so as to open only the N-type MOSFET region N, and As is provided at a concentration of about 5E15 / cm ² only in the N-type MOSFET region N through the opening. Ion implantation is performed to form N-type source / drain contact regions 6bn as shown in FIG.

  Then, a silicon oxide film 19 (see FIG. 10) is deposited to a thickness of about 20 nm on the entire top surface of the semiconductor substrate 1, and a photoresist (not shown) is formed thereon so as to open a P-type MOSFET region P. Oxide film wet etching with hydrofluoric acid or the like is performed using the resist as an etching mask to remove only the silicon oxide film 19 on the P-type MOSFET region P as shown in FIG. Further, a region that becomes the source / drain contact region 6 bp in the P-type MOSFET region P is recessed (grooves 13) to a depth of about 80 nm by Si etching. Then, the used photoresist is removed.

Then, as shown in FIG. 11, SiGe (here, SiGe doped with boron at a concentration of about 1E20 / cm ³ ) is placed in the recessed groove 13, for example, at a position near the surface of the semiconductor substrate 1 (for example, the surface is about 10 nm). SiGe contact region 6 bp is formed by epitaxial growth up to (over the position). Then, the silicon layer 15 is formed on the contact region 6 bp by continuously epitaxially growing pure silicon, for example, to the same thickness as the hard mask 14 (for example, about 30 nm). Since SiGe grows only in the portion where silicon is exposed, it does not grow in the N-type MOSFET region N covered with the silicon oxide film 19.

  Then, the silicon oxide film 19 covering the N-type MOSFET region N is removed. Then, as shown in FIG. 12, isotropic nitride film (SiN) dry etching removes the hard mask 14 made of nitride film (SiN) in each MOSFET region P and N and the silicon nitride film 5b on the upper side wall 5. (Hereinafter referred to as sidewall 5a). At this time, since there is not much difference in the selection ratio between Si and SiN, the silicon layer 15 on the source / drain contact region 6 bp is shaved to some extent by the nitride film dry etching to have an appropriate thickness.

  Then, as shown in FIG. 13, the silicon exposed portion (the silicon layer 15, the upper layer of the polysilicon gate electrode 3b and the extension region 6an of the N-type MOSFET region N) is self-aligned and silicided. A silicide layer (here, NiSi layer) 7 is formed on the portion.

  Then, as shown in FIG. 14, a compression type stress liner film (silicon nitride film) is formed on the P-type MOSFET region P (that is, so as to cover the gate 3 and the source / drain 6 via the sidewall 5 and the silicide layer 7). 8p is laminated, and similarly, a tensile stress liner film (silicon nitride film) 8n is laminated in the N-type MOSFET region N. Specifically, for example, a compression type stress liner film 8p is laminated on the entire upper surface of the semiconductor substrate 1, and the laminated portion on the P-type MOSFET region P is masked with a photoresist or the like, and the N-type MOSFET region N is formed. The laminated layer is removed by dry etching. Similarly, a tension type stress liner film 8n is laminated on the entire upper surface of the semiconductor substrate 1, and the laminated portion on the N-type MOSFET region N is masked with a photoresist or the like, and the deposited portion on the P-type MOSFET region P Are removed by dry etching. In this way, a logic circuit chip is manufactured.

  According to the semiconductor device manufacturing method described above, a logic circuit chip having the effects of the second embodiment can be manufactured.

  In this embodiment, in the P-type MOSFET region P, the contact region 6bp of the source / drain 6 is formed of SiGe and the stress liner film 8p is formed in a compression type, so that it is the same as in the second embodiment. The compressive strain is applied to the channel region 9 from both 6 bp and 8 p. However, in the N-type MOSFET region N, the stress liner film 8 n is only formed in a tensile type. Only the tensile strain is applied to the region 9.

  In this embodiment, the extension region 6ap of the source / drain 6 of the P-type MOSFET region P is formed of SiGe, and the extension region 6an of the source / drain 6 of the N-type MOSFET region N is formed as in the conventional case. Instead, the extension region 6ap of the source / drain 6 of the P-type MOSFET region P may be formed in the same manner as in the prior art, and the extension region 6an of the source / drain 6 of the N-type MOSFET region N may be formed of SiC, or The extension region 6ap of the source / drain 6 in the P-type MOSFET region P may be formed of SiGe, and the extension region 6an of the source / drain 6 of the N-type MOSFET region N may be formed of SiC.

  In this embodiment, the manufacturing method of the second embodiment is applied. However, in the case of applying the manufacturing method of the third embodiment, the hard mask by SiGe epitaxial growth → nitride film dry etching in this embodiment is applied. 14 with reference to the third embodiment, the process flow of removal 14 → formation of the silicide layer 7 is referred to the third embodiment, and the process of removal of the hard mask 14 by wet etching of nitride film such as phosphoric acid → formation of the silicide layer 14 is performed. Change to flow.

  The present invention is directed to all semiconductor integrated circuits (especially logic circuits that require high-speed operation) in which improvement in transistor current drive performance is desired.

1 is a schematic configuration diagram of a semiconductor device according to a first embodiment. In the method of manufacturing a semiconductor device according to the second embodiment, a state in which an insulating film 3a for a gate insulating film and a polysilicon layer 3b for a gate electrode are stacked on a semiconductor substrate 1, and a hard mask 14 is patterned thereon FIG. FIG. 10 is a diagram showing a state in which extension regions 6a of source / drains 6 are formed and sidewalls 5 are formed in the method of manufacturing a semiconductor device according to the second embodiment. In the method for manufacturing a semiconductor device according to the second embodiment, the contact region 6b of the source / drain 6 is formed of SiGe and the silicon layer 15 is formed thereon. In the method for manufacturing a semiconductor device according to the second and third embodiments, a state where the silicon nitride film 5b on the upper layer of the hard mask and the sidewalls 5 is removed is shown. In the method for manufacturing a semiconductor device according to the second and third embodiments, a state is shown in which a stress liner film 8 is formed after silicide 7 is formed. In the method for manufacturing a semiconductor device according to the third embodiment, the contact region 6b of the source / drain 6 is formed of SiGe, and the silicon layer 15 is formed thereon. 6 is a diagram showing a state in which an element isolation film 17, a gate 3 and a hard mask 13 are formed on a semiconductor substrate 1 in a method for manufacturing a semiconductor device according to a fourth embodiment. In the method for manufacturing a semiconductor device according to the fourth embodiment, the extension regions 6ap and 6an of the source / drain 6 are formed and the sidewalls 5 are formed. In the method of manufacturing a semiconductor device according to the fourth embodiment, the silicon oxide film 19 is formed on the N-type MOSFET region N after the contact region 6bn of the N-type MOSFET region N is formed by the conventional method, and the P-type MOSFET region It is the figure which showed the state which recessed the area | region used as the contact region of the source / drain of P. In the method for manufacturing a semiconductor device according to the fourth embodiment, the contact region 6 bp is formed by epitaxial growth with SiGe in the recessed groove 13, and the silicon layer 15 is formed thereon. In the method for manufacturing a semiconductor device according to the fourth embodiment, the silicon oxide film 19, the hard mask 14, and the silicon nitride film 15 are removed. FIG. 10 is a diagram showing a state in which a silicide layer 7 is formed in the method for manufacturing a semiconductor device according to the fourth embodiment. In the method of manufacturing a semiconductor device according to the fourth embodiment, a state in which a compression type stress liner film 8p is formed on the P type MOSFET region P and a tensile type stress liner film 8n is formed on the N type MOSFET region N. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 3 gate, 3a gate insulating film, 3b gate electrode, 5 side wall, 5a silicon oxide film, 5b silicon nitride film, 6 source / drain, 6a extension region, 6b contact region, 7 silicide layer, 8 stress liner Film, 9 channel region, 13 groove, 14 hard mask, 15 silicon layer, 17 element isolation film, 19 silicon oxide film.

Claims (11)

A semiconductor substrate;
A gate formed on the semiconductor substrate;
A source / drain formed in the semiconductor substrate;
A sidewall formed in an L-shaped cross section in a side view so as to cover the side surface of the gate and the extension region of the source / drain;
A silicide layer formed on the gate and on the source / drain contact region;
A stress liner film formed so as to cover the gate and the source / drain via the sidewall and the silicide layer,
The contact region of the source / drain is formed of a first semiconductor material having a larger lattice spacing than the semiconductor material of the semiconductor substrate, and the stress liner film is a compression type, or the contact region of the source / drain Is formed of a second semiconductor material having a lattice spacing smaller than that of the semiconductor material of the semiconductor substrate, and the stress liner film is a tensile type. In the case where the semiconductor substrate is a Si (silicon) substrate,
The first semiconductor material is SiGe (silicon germanium);
The semiconductor device according to claim 1, wherein the second semiconductor material is SiC (silicon carbide).   The semiconductor device according to claim 1, wherein the contact region of the source / drain is formed to a thickness of 20 nm or more. (A) An insulating film for a gate insulating film and a polysilicon layer for a gate electrode are sequentially deposited on a semiconductor substrate, a hard mask made of a nitride film is formed thereon, and etching is performed using the hard mask as an etching mask. And forming a gate,
(B) forming a source / drain extension region in the semiconductor substrate;
(C) forming a sidewall by forming an oxide film in a cross-sectional L-shape in a side view so as to cover the side surface of the gate and a necessary portion of the extension region, and forming a nitride film thereon; ,
(C) Recessing a region to be a source / drain contact region in the semiconductor substrate, and in the recessed groove, a first semiconductor material having a lattice spacing larger than that of the semiconductor material of the semiconductor substrate or having a smaller lattice spacing. Epitaxially growing two semiconductor materials to form a source / drain contact region and forming a silicon layer thereon;
(D) removing the nitride film and the hard mask on the sidewall by nitride film etching;
(E) siliciding the upper layer portion of the gate electrode and the silicon layer to form a silicide layer;
(F) forming a compression type or tensile type stress liner film so as to cover the gate and the source / drain via the oxide film and the silicide layer of the sidewall;
A method for manufacturing a semiconductor device, comprising:   5. The method of manufacturing a semiconductor device according to claim 4, wherein an element isolation film made of an oxide film is formed on the semiconductor substrate.   5. The method of manufacturing a semiconductor device according to claim 4, wherein in the step (c), the silicon layer is continuously formed by epitaxial growth after the formation of the contact region.   5. The method of manufacturing a semiconductor device according to claim 4, wherein in the step (d), the nitride film etching is isotropic nitride film dry etching.   8. The method of manufacturing a semiconductor device according to claim 7, wherein in the step (c), the silicon layer is formed to have a thickness comparable to that of the hard mask.   5. The method of manufacturing a semiconductor device according to claim 4, wherein in the step (d), the nitride film etching is a nitride film wet etching using phosphoric acid. In the step (c), when the semiconductor substrate is a Si (silicon) substrate,
The first semiconductor material is SiGe (silicon germanium);
The method of manufacturing a semiconductor device according to claim 4, wherein the second semiconductor material is SiC (silicon carbide).   5. The method of manufacturing a semiconductor device according to claim 4, wherein in the step (c), the contact region is formed to a thickness of 20 nm or more.

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