KR20050117870A - Liquid crystal display device of line on glass type - Google Patents

Abstract

The present invention provides a line on glass type liquid crystal display device which can improve the adhesion between the conductive film and the LOG pad.

A line on glass type liquid crystal display device according to the present invention comprises: integrated circuits for driving a signal line formed on a substrate; A conductive film on which the integrated circuits are mounted and attached to the substrate; Supply lines formed on the substrate to supply driving signals to the integrated circuits; A first pad formed on the substrate to be connected to the supply lines; And a second pad formed on the conductive film and connected to the first pad and having a wider width than the first pad.

Description

Line on glass type liquid crystal display device {LIQUID CRYSTAL DISPLAY DEVICE OF LINE ON GLASS TYPE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a line on glass type liquid crystal display device capable of improving adhesion between a conductive film and a LOG pad.

A typical liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.

In the liquid crystal display panel, the liquid crystal cells display an image by adjusting the light transmittance according to the pixel signal.

The driving circuit includes a gate driver for driving the gate lines of the liquid crystal display panel, a data driver for driving the data lines, a timing controller for controlling the driving timing of the gate driver and the data driver, the liquid crystal display panel and the driving. And a power supply unit supplying power signals necessary for driving the circuits.

The data driver and the gate driver are separated into a plurality of integrated circuits (hereinafter, referred to as ICs) and manufactured in a chip form. Each of the integrated drive ICs is mounted on an open IC area on a tape carrier package (TCP) or mounted on a base film of TCP in a chip on film (COF) method, and a liquid crystal display panel and a tape automated bonding (TAB) method. Electrically connected. In addition, the drive IC may be directly mounted on the liquid crystal panel using a chip on glass (COG) method. The timing control unit and the power supply unit are manufactured in a chip form and mounted on a main printed circuit board (PCB).

The drive ICs connected to the liquid crystal display panel by TCP are connected to the timing control part and the power supply part of the main PCB through the flexible printed circuit (FPC) and the sub PCB. Specifically, the data drive ICs receive data control signals and pixel data from the timing controller mounted on the main PCB through the FPC and the data PCB, and power signals from the power supply. The gate drive ICs receive gate control signals from the timing controller mounted on the main PCB and power signals from the power supply through the gate FPC and the gate PCB.

Drive ICs mounted on a liquid crystal display panel in a COG method control signals from a timing controller mounted on a main PCB through line on glass (LOG) type signal lines formed on the FPC and the liquid crystal display panel. And power signals from the pixel data and the power supply unit.

Recently, even when the drive ICs are connected to the liquid crystal display panel via TCP, the LOG type signal lines are adopted to eliminate the PCB, thereby making the liquid crystal display device even thinner. In particular, signal lines for removing gate PCBs that transmit relatively few signals and supplying gate control signals and power signals to gate drive ICs are formed in a LOG type on the liquid crystal display panel. Accordingly, the gate drive ICs mounted in TCP are gate control signals from the timing controller and power signals from the power supply via the main PCB-> FPC-> data PCB-> data TCP-> LOG signal line-> gate TCP. Will be supplied.

In detail, the LOG type liquid crystal display device in which the gate PCB is removed includes the main PCB 20 including the timing controller 22 and the power supply unit 24 and the main PCB (FPC 18) as shown in FIG. 1. A data PCB 16 connected to the 20, a data driver IC 14 mounted thereon, a data TCP 12 connected between the data PCB 16 and the liquid crystal display panel 6, and a gate driver IC 10; And a gate TCP 8 connected to the liquid crystal display panel 6.

The liquid crystal display panel 6 is formed by bonding the lower array substrate 2 and the upper array substrate 4 with the liquid crystal interposed therebetween. The liquid crystal display panel 6 includes liquid crystal cells independently driven by thin film transistors in regions defined by intersections of the gate lines GL and the data lines DL. The thin film transistor supplies the pixel signal from the data line DL to the liquid crystal cell in response to the scan signal from the gate line GL.

The data drive ICs 14 are connected to the data lines DL via the data TCP 12 and the data pad of the liquid crystal display panel 6. The data drive ICs 14 convert the pixel data into analog pixel signals and supply them to the data lines DL. To this end, the data drive ICs 14 transmit data control signals, pixel data, and power signals from the timing control unit 22 and the power supply unit 24 on the main PCB 20 via the data PCB 16 and the FPC 18. Will be supplied.

The gate drive ICs 10 are connected to the gate lines GL via the gate TCP 8 and the gate pad of the liquid crystal display panel 6. The gate drive ICs 10 sequentially supply scan signals of the gate high voltage VGH to the gate lines GL. In addition, the gate drive ICs 10 supply the gate low voltage VGL to the gate lines GL in a period other than the period in which the gate high voltage VGH is supplied.

To this end, gate control signals and power signals from the timing control unit 22 and the power supply unit 24 on the main PCB 20 are supplied to the data TCP 12 via the FPC 18 and the data PCB 16. . Gate control signals and power signals supplied through the data TCP 12 are supplied to the gate TCP 8 via a LOG signal line 26 formed in the edge region of the lower array substrate 2. Gate control signals and power signals supplied to the gate TCP 8 are input into the gate drive IC 10 through the input terminals of the gate drive IC 10 and used. The gate control signals and the power signals are output through the output terminals of the gate drive IC 10 so as to be mounted on the next gate TCP 8 via the gate TCP 8 and the LOG signal line 26. It is supplied to the IC 10.

The LOG signal line 26 is normally supplied from the power supply unit 24 such as a gate low voltage VGL, a gate high voltage VGH, a common voltage VCOM, a ground voltage GND, and a base driving voltage VCC. DC drive voltages; It is composed of signal lines that supply each of the gate control signals supplied from the timing controller 22, such as the gate start pulse GSP, the gate shift clock signal GSC, and the gate enable signal GOE.

The LOG pad 60 connected to the LOG signal line 26 is formed on the lower substrate 1 as illustrated in FIGS. 2A and 2B, and the LOG pad lower electrode connected to the LOG signal line 26. And a LOG pad upper electrode 66 connected to the LOG pad lower electrode 62 through a first contact hole 64 penetrating through the gate insulating film 52 and the protective film 58.

The data pad 70 adjacent to the LOG pad 60 has a data pad lower electrode 72 formed on the gate insulating film 52 and a second penetrating through the passivation film 58 as shown in FIGS. 2A and 2B. The data pad upper electrode 76 is connected to the data pad lower electrode 72 through the contact hole 74.

Adjacent data pads 70 and LOG pads 60 are supplied with drive signals through the same TCP 12 as shown in FIG. 2A. That is, the data pad 60 is connected to the first supply pad 54 formed on the data TCP 12 to supply the pixel signal generated by the data drive IC 14 to the data line DL. The LOG pad 60 is connected to the second supply pad 56 formed on the data TCP 12 so that the gate control signal and the power signal generated by the timing control unit 22 and the power supply unit 24 are connected to the LOG type signal line. 26).

However, when the pad lower electrodes 72 and 62 and the pad upper electrodes 76 and 66 included in the data pad 70 and the LOG pad 60 are located on different planes, the data pad 70 and the LOG pad ( 60, a step h is generated as shown in FIG. 2B. This step h is noticeable when the active layer 78 is positioned below the data pad lower electrode 72. For example, when the active layer 78 and the data pad lower electrode 72 are simultaneously formed with the same mask in order to reduce the number of mask processes, the step between the data pad 70 and the LOG pad 60 appears seriously. Due to this step, when the same data TCP 12 is attached to the data pad 70 and the LOG pad 60, the adhesion area between the LOG pad 60 and the data TCP 12 is relatively relatively high. There is a problem that less than that between 12) the data TCP (12) is lifted on the LOG pad 60 side, the driving failure occurs.

Accordingly, an object of the present invention is to provide a line on glass type liquid crystal display device which can improve the adhesion between the conductive film and the LOG pad.

In order to achieve the above object, the line-on-glass type liquid crystal display device according to the present invention comprises: integrated circuits for driving a signal line formed on a substrate; A conductive film on which the integrated circuits are mounted and attached to the substrate; Supply lines formed on the substrate to supply driving signals to the integrated circuits; A first pad formed on the substrate to be connected to the supply lines; And a second pad formed on the conductive film and connected to the first pad and having a wider width than the first pad.

The line on glass type liquid crystal display may further include a dummy pad formed on the substrate between the first pads and connected to the second pad.

The second pad may include a first supply pad connected to the first pad; And a second supply pad connected to the first supply pad and connected to the dummy pad.

The integrated circuit may be an integrated circuit for driving at least one of a data line and a gate line intersected on the substrate.

The first pad may be connected to the same conductive film as the data pad connected to the data line.

The conductive film is a tape carrier package mounted with a data integrated circuit for driving the data line.

The supply line may supply a driving signal to a gate integrated circuit for driving the gate line.

The supply line may include a gate power signal or a gate start pulse, a gate shift clock signal, and a gate enable signal including at least one of a gate low voltage, a gate high voltage, a common voltage, a ground voltage, and a power supply voltage in the gate integrated circuit. It is characterized in that for supplying a gate control signal including at least one.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 5.

3 is a perspective view showing a LOG type liquid crystal display device according to the present invention.

Referring to FIG. 3, a LOG type liquid crystal display device according to the present invention includes a liquid crystal display panel 106 having a liquid crystal cell matrix, a data drive IC 114, and data TCP (connected to the liquid crystal display panel 106). 112 and a gate TCP 108 mounted on the gate drive IC 110 and connected to the liquid crystal display panel 106.

The data drive ICs 114 are connected to the data lines DL via the data TCP 112 and the data pad 160 of the liquid crystal display panel 106. The data drive ICs 114 convert pixel data into analog pixel signals and supply them to the data lines DL.

The gate drive ICs 110 are connected to the gate lines GL via the gate TCP 108 and the gate pad of the liquid crystal display panel 106. The gate drive ICs 110 sequentially supply a scan signal of the gate high voltage VGH to the gate lines GL. In addition, the gate drive ICs 110 supply the gate low voltage VGL to the gate lines GL in a period other than the period in which the gate high voltage VGH is supplied.

The liquid crystal display panel 106 includes an image display portion having a liquid crystal cell matrix and a pad portion positioned at an outer portion of the image display portion.

The image display unit is composed of liquid crystal cells for each intersection area of the gate lines GL and the data lines DL to display an image. The image display part is injected between the lower substrate 102 having the thin film transistor array together with the gate line and the data line, the upper substrate 104 having the color filter array formed therebetween, and the lower substrate 102 and the upper substrate 104. Liquid crystals.

The pad portion is an outer region of the lower substrate 102 that does not overlap the upper substrate 104, and includes data pads 170 extending from the data line DL, gate pads extending from the gate line GL, and a LOG. LOG pads 160 extending from the signal line 126 are positioned. In addition, a plurality of LOG signal lines 126 are disposed in the outer region of the lower substrate 102 to transmit gate driving signals supplied to the gate drive IC 110. The LOG signal line 126 is supplied from a power supply such as a gate high voltage signal VGH, a gate low voltage signal VGL, a common voltage signal VCOM, a ground voltage signal GND, and a power supply voltage signal VCC. And DC line signals, gate start pulses GSP, gate shift clock signals GSC, and gate enable signals GOE, respectively.

At least one dummy line 188 connected to the dummy pad 180 formed to improve adhesion to the TCP 108 and 112 is disposed between the LOG signal line 126 as shown in FIGS. 4 and 5. do.

Meanwhile, the LOG pad 160 connected to the LOG signal line 126 is formed on the lower substrate 102 and is connected to the LOG signal line 126 and the LOG pad lower electrode 162 and the gate insulating film 152. ) And a LOG pad upper electrode 166 connected to the LOG pad lower electrode 162 through the first contact hole 164 penetrating through the passivation layer 158.

The dummy pad 180 connected to the dummy line 188 is formed on the lower substrate 102, and the dummy pad lower electrode 182 connected to the dummy line 188, the gate insulating layer 152, and the passivation layer 158 are connected to the dummy line 188. The dummy pad upper electrode 186 is connected to the dummy pad lower electrode 182 through a dummy contact hole 184 penetrating through the dummy contact hole 184.

The data pad 170 adjacent to the LOG pad 160 and the dummy pad 180 may have a data pad lower electrode 172 formed on the gate insulating layer 152 and a second contact hole 174 penetrating through the passivation layer 158. And a data pad upper electrode 176 connected to the data pad lower electrode 172 through the.

Adjacent data pads 170, LOG pads 160, and dummy pads 180 are connected to the same data TCP 112. The data TCP 112 corresponds to the first supply pad 154 one-to-one corresponding to each of the data pads 170, the second supply pad 156 corresponding to the LOG pad 160, and the dummy pad 180. And a third supply pad 168 connected to the second supply pad 156.

The data pad 170, which is connected to the first supply pad 154 of the data TCP 112 through the anisotropic conductive film 190 having the conductive balls 192, receives the pixel signal generated by the data drive IC 114. Supply to the line DL. The LOG pad 160, which is connected to the second and third supply pads 156 and 168 of the data TCP 112 through the anisotropic conductive film 190 having the conductive balls 192, has a gate control signal generated by a timing controller and a power supply unit. And a power signal to the LOG signal line 126.

As described above, since the LOG pad 160 is connected to the data TCP 112 through the second and third supply pads 156 and 168 having a larger area than the conventional one, the contact area with the data TCP 112 is increased to improve the adhesive force. In addition, it is possible to prevent the lifting of the TCP due to the step between the data pad 170 and the LOG pad 160 due to the improved adhesion can reduce the drive failure.

On the other hand, the LOG-type liquid crystal display according to the present invention has been described taking the LOG pad adjacent to the data pad as an example, but may be applied to the LOG pad adjacent to the gate pad. In particular, the present invention can be applied when a step occurs between a LOG pad and a signal pad adjacent to the LOG pad (for example, a gate pad connected to a gate line and a common pad connected to a common line).

As described above, the LOG type liquid crystal display device according to the present invention widens the area of the TCP supply pad connected to the LOG pad. As a result, the contact area between the LOG pad and the supply pad is increased, thereby improving adhesion between the LOG pads and preventing the lifting of TCP.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a view showing a conventional line-on glass liquid crystal display device.

FIG. 2A is a plan view illustrating a LOG pad and a data pad connected to the data TCP illustrated in FIG. 1, and FIG. 2B is a cross-sectional view illustrating the LOG pad and a data pad illustrated in FIG. 2A.

3 is a view showing a line-on-glass type liquid crystal display device according to the present invention.

FIG. 4 is a plan view showing the data TCP shown in FIG. 3, a LOG pad and a data pad connected to the data TCP.

FIG. 5 is a cross-sectional view illustrating the liquid crystal display taken along the line “VV ′” in FIG. 4.

<Description of Symbols for Main Parts of Drawings>

2,102: lower array substrate 4: upper array substrate

6 LCD panel 8,108 gate TCP

10110: Gate Drive IC 12112: Data TCP

14,114: Data Drive IC 16,20: PCB

18: FPC 22: timing control

24: power supply 26,126: LOG signal line

Claims (8)

Integrated circuits for driving signal lines formed on the substrate; A conductive film on which the integrated circuits are mounted and attached to the substrate; Supply lines formed on the substrate to supply driving signals to the integrated circuits; A first pad formed on the substrate to be connected to the supply lines; And a second pad formed on the conductive film and connected to the first pad and having a wider width than the first pad. The method of claim 1, And a dummy pad formed on the substrate between the first pads and connected to the second pad. The method of claim 2, The second pad is A first supply pad connected to the first pad; And a second supply pad connected to the first supply pad and connected to the dummy pad. The method of claim 1, The integrated circuit And an integrated circuit for driving any one of a data line and a gate line intersected on the substrate. The method of claim 4, wherein The first pad is And a data pad connected to the same data pad as the data pad connected to the data line. The method of claim 4, wherein And the conductive film is a tape carrier package mounted with a data integrated circuit for driving the data line. The method of claim 4, wherein And the supply line supplies a drive signal to a gate integrated circuit for driving the gate line. The method of claim 7, wherein The supply line may include a gate power signal or a gate start pulse, a gate shift clock signal, and a gate enable signal including at least one of a gate low voltage, a gate high voltage, a common voltage, a ground voltage, and a power supply voltage. And a gate control signal including at least one of the gate control signals.