KR20050116307A - In plane switching mode liquid crystal display device and method of fabricating thereof - Google Patents

Abstract

In the method of manufacturing a transverse electric field mode liquid crystal display device according to the present invention, forming a gate electrode and a plurality of metal layers on a first substrate, forming a gate insulating layer on the first substrate, and forming a semiconductor on the gate insulating layer Forming a layer, a source electrode and a drain electrode, forming a protective layer on the first substrate, and at least one transparent common electrode and pixel electrode disposed substantially parallel on the metal layer to form a transverse electric field. Forming step. The metal layer has a width smaller than that of the common electrode and the pixel electrode to prevent light leakage through the common electrode and the pixel electrode.

Description

Transverse electric field mode liquid crystal display device and manufacturing method therefor {IN PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THEREOF}

The present invention relates to a transverse electric field mode liquid crystal display device, and more particularly, to a transverse electric field mode liquid crystal display device and a method of manufacturing the same, which can simplify the process and reduce manufacturing costs, and can prevent image quality defects caused by light leakage. .

Recently, with the development of various portable electronic devices such as mobile phones, PDAs, and notebook computers, there is a growing demand for flat panel display devices for light and thin applications. Such flat panel displays are being actively researched, such as LCD (Liquid Crystal Display), PDP (Plasma Display Panel), FED (Field Emission Display), VFD (Vacuum Fluorescent Display), but mass production technology, ease of driving means, Liquid crystal display devices (LCDs) are in the spotlight for reasons of implementation.

The liquid crystal display device has various display modes according to the arrangement of the liquid crystal molecules. However, the liquid crystal display device of the TN mode is mainly used because of the advantages of easy monochrome display, fast response speed, and low driving voltage. In such a TN mode liquid crystal display device, liquid crystal molecules aligned horizontally with the substrate are almost perpendicular to the substrate when a voltage is applied. Therefore, there is a problem that the viewing angle is narrowed upon application of voltage due to the refractive anisotropy of the liquid crystal molecules.

In order to solve this viewing angle problem, liquid crystal display devices of various modes having wide viewing angle characteristics have recently been proposed, but among them, the liquid crystal display device of the lateral field mode (In Plane Switching Mode) is applied to actual production. It is produced. The IPS mode liquid crystal display device aligns liquid crystal molecules in a plane by forming at least one pair of electrodes arranged in parallel in a pixel to form a transverse electric field substantially parallel to the substrate.

1 is a view showing the structure of a conventional IPS mode liquid crystal display device, in which FIG. 1 (a) is a plan view and FIG. 1 (b) is a sectional view taken along the line II ′ of FIG. As shown in FIG. 1A, the pixels of the liquid crystal panel 1 are defined by gate lines 3 and data lines 4 arranged vertically and horizontally. Although only the (n, m) th pixels are shown in the drawing, in the liquid crystal panel 1, n and m gate lines 3 and data lines 4 are disposed, respectively, and thus the liquid crystal panel 1 is disposed. N x m pixels are formed throughout. The thin film transistor 10 is formed at the intersection of the gate line 3 and the data line 4 in the pixel.

The thin film transistor 10 includes a gate electrode 11 to which a scan signal is applied from the gate line 3, and a semiconductor layer formed on the gate electrode 11 and activated as a scan signal is applied to form a channel layer. 12 and a source electrode 13 and a drain electrode 14 formed on the semiconductor layer 12 and to which an image signal is applied through the data line 4. The image signal input from the outside is applied to the liquid crystal layer. do.

In the pixel, a plurality of common electrodes 5 and a pixel electrode 7 are arranged substantially parallel to the data line 4. In addition, a common line 16 connected to the common electrode 5 is disposed in an upper region of the pixel, and a pixel electrode line 18 connected to the pixel electrode 7 is disposed on the common line 16. It overlaps with the common line 16. Storage capacitance is formed in the transverse electric field mode liquid crystal display by overlapping the common line 16 and the pixel electrode line 18.

In the IPS mode liquid crystal display device configured as described above, the liquid crystal molecules are aligned substantially in parallel with the common electrode 5 and the pixel electrode 7. When the thin film transistor 10 is operated to apply a signal to the pixel electrode 7, a transverse electric field substantially parallel to the liquid crystal panel 1 is generated between the common electrode 5 and the pixel electrode 7. Since the liquid crystal molecules rotate on the same plane along the transverse electric field, gray level inversion due to the refractive anisotropy of the liquid crystal molecules can be prevented.

The conventional IPS mode liquid crystal display device having the above structure will be described in more detail with reference to the cross-sectional view of FIG.

As shown in FIG. 1B, a gate electrode 11 is formed on the first substrate 20, and a gate insulating layer 22 is stacked over the entire first substrate 20. The semiconductor layer 12 is formed on the gate insulating layer 22, and the source electrode 13 and the drain electrode 14 are formed thereon. In addition, a passivation layer 24 is formed on the entire first substrate 20.

In addition, a plurality of common electrodes 5 are formed on the first substrate 20, and a pixel electrode 7 and a data line 4 are formed on the gate insulating layer 22 to form the common electrode 5. The transverse electric field E is generated between the pixel electrodes 7.

The black matrix 32 and the color filter layer 34 are formed on the second substrate 30. The black matrix 32 is to prevent light leakage into an area where the liquid crystal molecules do not operate. As shown in the drawing, the black matrix 32 is formed between the region of the thin film transistor 10 and between the pixel and the pixel (ie, the gate line and the data line). Area). The color filter layer 34 is composed of R (Red), B (Blue), and G (Green) to realize actual colors.

The liquid crystal layer 40 is formed between the first substrate 20 and the second substrate 30 to complete the liquid crystal panel 1.

As described above, in the IPS mode liquid crystal display device, the transverse electric field E is formed inside the liquid crystal layer 40 by the common electrode 5 and the pixel electrode 7 formed on the substrate 20 and the gate insulating layer 22, respectively. Is generated to drive the liquid crystal molecules inside the liquid crystal layer 40.

2 (a) to 2 (e) show a method of manufacturing a conventional IPS mode liquid crystal display device having the above structure. In this case, in order to specifically explain the manufacturing method of the IPS mode liquid crystal display device, the substrate is divided into a display area in which pixels are formed to form an actual image, and a pad area in which pads and driving elements are formed to apply a signal to the display area. .

First, as shown in FIG. 2A, after the metal is stacked on the first substrate 20, the gate electrode 11 and the common electrode 5 are formed in the display area using the first mask, and then the pad area. The gate pad 52 is formed in this. Subsequently, as shown in FIG. 2B, after the gate insulating layer 22 is formed over the entire first substrate 20, semiconductors are stacked and the semiconductors are patterned by using a second mask. The semiconductor layer 12 is formed on the gate insulating layer 22. Although not shown in the drawing, an ohmic contact layer is formed on the semiconductor layer 12.

After that, as shown in FIG. 2C, the metals are stacked and the metals are etched using the third mask to form the source electrode 13 and the drain electrode 14 on the semiconductor layer 12, and the gate insulating layer. The pixel electrode 7 is formed over the 22. Subsequently, as shown in FIG. 2 (d), a passivation layer 24 is formed over the entire first substrate 20 and then the passivation layer 24 and the gate of the pad region are formed using the fourth mask. The insulating layer 22 is etched to expose the gate pad 52. In addition, a transparent conductive material such as indium tin oxide (ITO) is stacked on the protective layer 24 and then etched using a fifth mask to form a transparent conductive layer 54 on the gate pad 52. The reason for forming the transparent conductive layer 54 is to prevent the gate pad 52 from being oxidized by being exposed to oxygen during the process.

Subsequently, as shown in FIG. 2E, the black matrix 32 for blocking light transmitted to the image non-display area on the second substrate 30 and the color filter layer 34 for realizing color are provided. After forming the first substrate 20 and the second substrate 30, the liquid crystal layer 40 is formed between the first substrate 20 and the second substrate 30 to form an IPS mode liquid crystal display device. To complete.

As described above, in the conventional IPS mode liquid crystal display device manufacturing method, a mask for forming a gate electrode and a common electrode, a mask for forming a semiconductor layer, a mask for forming a source / drain electrode and a pixel electrode, a mask for forming a protective layer, and a layer for forming a transparent conductive layer. A total of five masks, such as a mask, are required. Therefore, in the conventional IPS mode liquid crystal display device manufacturing process, the process is complicated, the manufacturing cost increases, and there is a problem that requires a large installation cost.

The present invention has been made in view of the above, and an object thereof is to provide a transverse electric field mode liquid crystal display device having a simplified process and a reduced manufacturing cost, and a method of manufacturing the same.

Another object of the present invention is to provide a transverse field mode liquid crystal display device capable of preventing light leakage by forming an opaque metal layer under the transparent common electrode and the pixel electrode.

In order to achieve the above object, the transverse electric field mode liquid crystal display device according to the present invention comprises a plurality of gate lines and data lines defining a plurality of pixels, a thin film transistor disposed in each pixel, and arranged horizontally in the pixel. At least one pair of transparent common and pixel electrodes forming an electric field, and arranged along the data line and the common electrode and a metal layer blocking light passing through the common electrode and the pixel electrode.

In addition, the method of manufacturing a transverse electric field mode liquid crystal display device according to the present invention comprises the steps of forming a gate electrode and a plurality of metal layers on a first substrate, forming a gate insulating layer on the first substrate, and the gate insulating layer Forming a semiconductor layer, a source electrode and a drain electrode thereon; forming a protective layer on the first substrate; and at least one transparent common electrode and a pixel disposed substantially parallel to the metal layer to form a transverse electric field. Forming an electrode.

In the present invention, the number of masks used in the manufacture of the IPS mode liquid crystal display device is minimized, thereby simplifying the manufacturing process and reducing the manufacturing cost. While five masks are required to fabricate a conventional IPS mode liquid crystal display device, the present invention requires only three masks, thereby reducing the photolithography process and significantly reducing manufacturing costs.

Meanwhile, in the present invention, since the common electrode and the pixel electrode are made of a transparent conductive material, not only the luminance of the IPS mode liquid crystal display device is improved but also the aperture ratio is improved. In addition, an opaque metal layer is formed below the common electrode and the pixel electrode to block light leaking to the transparent common electrode and the pixel electrode, thereby effectively improving image quality. In this case, the metal layer is formed to have a width smaller than that of the common electrode and the pixel electrode, thereby preventing light leakage into an area where no transverse electric field is formed.

Hereinafter, an IPS mode liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

3 (a) to 3 (g) are views showing a manufacturing method of an IPS mode liquid crystal display device according to the present invention.

First, as shown in FIG. 3A, a metal layer is laminated on a first substrate 120 made of a transparent material such as glass and including a display area and a pad area, and then etching the metal layer using a first mask. The gate electrode 111 and the plurality of metal layers 170 are formed in the display area, and the gate pad 152 is formed in the pad area. The metal layer 170 is disposed in a region where the common electrode and the pixel electrode are to be formed to block light from being transmitted to the region. The gate electrode 111, the metal layer 170, and the gate pad 152 are formed by evaporation or sputtering Cu, Cu alloy, Al, Al alloy, Cr, Mo, Ag, Ta, Ti, MoW, or the like. By lamination and etching.

Thereafter, as shown in FIG. 3B, the gate insulating layer 122 such as SiNx or SiOx, silicon (Si), etc. are formed over the entire first substrate 120 by CVD (Chemical Vapor Deposition). After sequentially stacking the semiconductor layer 112a, Ti, Mo, Ta, Cr, Ag, MoW, Al, Al alloy, Cu, Cu alloy, and the like are deposited on the semiconductor layer 112a by vapor deposition or sputtering to form a metal layer ( 113a). In this case, although not shown, an impurity semiconductor layer doped with impurities is formed on the semiconductor layer 112. Thereafter, a photoresist is applied on the metal layer 113a and developed by a second mask to form a first photoresist pattern 162.

In this case, the second mask is a diffraction mask. That is, it is a diffraction mask which consists of a transmission area which permeate | transmits light (for example, an ultraviolet-ray) incident to a photoresist layer, the blocking area which blocks | blocks light, and the diffraction area | region (or semi-transmissive area | region) which transmits only a part of light. . Therefore, when developing the photoresist layer, part of the photoresist layer on the gate electrode 111 is removed (this region is a region where the channel layer of the thin film transistor is formed).

Subsequently, as illustrated in FIG. 3C, the metal layer 113a and the semiconductor layer 112 are etched using the first photoresist patterns 162a and 162b to form a semiconductor layer (on the gate insulating layer 122). 112 and metal layer 114a and data line 104 are formed. The first photoresist pattern 162a is ashed to expose a portion of the metal layer 114a (ie, a region corresponding to the channel region of the thin film transistor) to the outside.

When the exposed metal layer 114a is etched using the aced first photoresist pattern 162, as shown in FIG. 3 (d), the source electrode 113 and the drain electrode on the semiconductor layer 112 are etched. 114 is formed. In this case, a portion of the impurity semiconductor layer formed on the semiconductor layer 112 is also etched to form an ohmic contact layer.

 Thereafter, an inorganic material such as SiNx or SiOx or an organic material such as BCB (Benzo Cyclo Butene) or photoacryl is laminated on the first substrate 120 to form a protective layer 124, and then the protective layer 124. A photoresist is applied thereon and developed using a third mask to form a second photoresist pattern 164.

Thereafter, as shown in FIG. 3E, the protective layer 124 and the gate insulating layer 122 are etched using the second photoresist pattern 164 to form a hole 172. In this case, the protective layer 124 is over-etched so that a part of the second photoresist pattern 164 is undercut. In addition, the metal layer 170 is exposed to the outside by the etching, the width of the hole 172 is formed larger than the metal layer 170 to expose the metal layer 170 completely to the outside. Subsequently, a transparent conductive layer 174 made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or tin oxide (TO) in the upper portion of the second photoresist pattern 164 and in the hole 172. )). In this case, since the protective layer 124 is undercut, the transparent conductive layer 174 is formed only on a portion of the upper portion of the second photoresist pattern 164 and inside the hole 172.

Subsequently, as shown in FIG. 3F, the second photoresist pattern 164 is removed to lift-off the transparent conductive layer 174, thereby forming a hole 172 in the display area. ) A transparent common electrode 105 and a pixel electrode are formed inside the conductive layer, and a conductive layer 176 is formed in the hole of the pad region. As described above, since the transparent conductive layer 176 is formed on the pad 152, it is possible to prevent the pad from being exposed to the outside during the process and being oxidized. In other words, it is not necessary to form the antioxidant conductive layer of the pad by a separate process.

Thereafter, as shown in FIG. 3 (g), after removing the second photoresist pattern 164, the black matrix 132 formed of Cr / CrOx, black resin, or the like on the second substrate 130. ). After the color filter layer 134 is formed, the first substrate 120 and the second substrate 130 are bonded to each other, and the liquid crystal layer 140 is formed between the first substrate 120 and the second substrate 130. To complete the IPS mode liquid crystal display device. Although not shown in the drawing, an overcoat layer may be formed on the color filter layer 134 to protect the color filter layer 134 and planarize the second substrate 130.

The liquid crystal layer 140 is typically formed by bonding the first substrate 120 and the second substrate 130 and then vacuum injecting liquid crystal therebetween. However, the liquid crystal layer 140 may be a liquid crystal dropping method. It may be formed by a dispensing process. That is, after directly dropping the liquid crystal onto the first substrate 120 or the second substrate 130, the first substrate 120 and the second substrate 130 are bonded to each other to form the liquid crystal by pressure. ), The liquid crystal layer 140 may be formed by uniformly distributing the same.

Although not shown in the drawing, not only the gate pad 152a for applying the signal to the gate line 103 but also the data pad for applying the signal to the data line 104a may be formed in the pad region. In this case, the data pad is formed on the same layer as the data line 104a by the same process, and a transparent conductive layer will be formed thereon by lift-off.

As described above, in the IPS mode liquid crystal display device manufacturing method according to the present invention, a first mask for forming a gate electrode and a metal layer, a second mask for forming a source electrode and a drain electrode, a common electrode and a pixel electrode for forming (lift-off) For) a third mask is required. That is, in order to manufacture a conventional IPS mode liquid crystal display device, a total of five masks are required, whereas a total of three masks are required in the present invention. Accordingly, it can be seen that the manufacturing method of the IPS mode liquid crystal display device according to the present invention is greatly simplified as compared to the conventional method of manufacturing the IPS mode liquid crystal display device. As a result, the manufacturing cost of the IPS mode liquid crystal display device can be greatly reduced. do.

On the other hand, referring to Figure 3 (g) looks at the structure of the IPS mode liquid crystal display device according to the present invention.

As shown in FIG. 3 (g), in the IPS mode LCD according to the present invention, the common electrode 105 and the pixel electrode 107 are transparent conductive materials such as ITO, IZO, or TO on the first substrate 120. Consists of As such, since the common electrode 105 and the pixel electrode 107 are formed on the first substrate 120 and the same layer, a uniform transverse electric field is applied to the liquid crystal layer 140. In addition, since the common electrode 105 and the pixel electrode 107 are made of a transparent conductive layer such as ITO and IZO or TO, the common electrode 105 and the pixel electrode 107 are made of opaque metal, compared to the conventional IPS mode liquid crystal display device in which the common electrode and the pixel electrode are formed. The luminance (white luminance) and the aperture ratio are improved.

Meanwhile, a metal layer 170 made of an opaque metal is formed under the common electrode 105 and the pixel electrode 107. The metal layer 170 is to block light from being transmitted through the common electrode 105 and the pixel electrode 107 made of a transparent conductive material, and have a width smaller than that of the common electrode 105 and the pixel electrode 107. Is formed.

The transverse electric field E between the common electrode 105 and the pixel electrode 107 arranged in parallel is not only formed between the common electrode 105 and the pixel electrode 107. As shown in FIG. 4A, the transverse electric field E is also formed on a part of the common electrode 105 and the partial region S1 of the pixel electrode 107, and the liquid crystal molecules are transversely formed by application of a signal. It is an area where an image is displayed as an area arranged along the electric field E. FIG. On the other hand, the central region S2 of the common electrode 105 and the pixel electrode 107 except for the region S1 is a region in which the transverse electric field E is not formed. This is a non-display area in which no image is displayed in the area.

The area where light leakage occurs is the central area S2, and the area S2 on both sides thereof is an area where no light leakage occurs. Therefore, as shown in FIG. 4B, the width b of the metal layer 170 is formed to have the same width as the center region S2 to block only the corresponding region and not block the side region S2. This effectively prevents light leakage while maximizing the aperture ratio. In this case, the width b of the metal layer 170 is preferably about 65 to 75% of the width a of the common electrode 105. For example, when the width a of the common electrode 105 is 7 μm, the width b of the metal layer 170 may be set to about 5 μm (that is, both side regions S1 of the center region S2). Can be set to about 1 μm).

The structure of the IPS mode liquid crystal display device 101 configured as described above will be described in more detail with reference to the plan view shown in FIG. 4.

As illustrated in FIG. 5, the common electrode 105 and the pixel electrode formed with the thin film transistor 110 and formed of a transparent conductive material are formed at the intersection of the gate line 103 and the data line 104 defining the pixel. 107 is disposed substantially parallel in the pixel to form a transverse electric field.

The metal layer 170 is disposed below the common electrode 105 and the pixel electrode 107 to block light leakage through the common electrode 105 and the pixel electrode 107. The common line 116 and the pixel electrode line 118 are disposed in an upper region (or may be formed in the center region) of the pixel. The common line 116 is formed of the same metal as the gate electrode 111 and the metal layer 170 of the thin film transistor 110, and the pixel electrode line 118 is the source electrode 113 and the drain electrode of the thin film transistor 110. The common line 116 and the pixel electrode line 118 are formed of the same metal as the 114, and are disposed with the gate insulating layer 122 interposed therebetween to form a storage capacitor. In this case, the metal layer 170 is formed on the same layer as the common line 116. In this case, the common line 116 and the pixel electrode line 118 are respectively connected to the common electrode 105 and the pixel electrode 107 by a lift-off process.

In addition, the common line 116 or the pixel electrode line 118 may be formed of a transparent conductive layer such as ITO, IZO, or TO. That is, it may be formed when the common electrode 105 and the pixel electrode 107 are formed.

On the other hand, in the above drawings, the IPS mode liquid crystal display device having a specific structure is disclosed, but the present invention is not limited to the IPS mode liquid crystal display device having such a structure. For example, although a certain number of common electrodes 105 and pixel electrodes 107 are disposed in the pixel, the number of common electrodes 105 and pixel electrodes 107 need not be limited. In addition, the structures of the common electrode 105 and the pixel electrode 107 disposed in the pixel need not be limited.

6 is a plan view showing another structure of the IPS mode liquid crystal display device according to the present invention. The IPS mode liquid crystal display device 201 having the structure shown in FIG. 6 has a structure similar to that of the IPS mode liquid crystal display device having the structure shown in FIGS. 3 (g) and 4, and has only a common electrode 205 and a pixel electrode. Only the structure of 207 is different. That is, in the IPS mode liquid crystal display device having this structure, the common electrode 205 and the pixel electrode 207 are formed on the substrate as a transparent conductive layer, and light leakage phenomenon is applied to the lower portion of the common electrode 205 and the pixel electrode 207. The metal layer 270 for preventing is formed.

On the other hand, in the IPS mode liquid crystal display device having this structure, the common electrode 205 and the pixel electrode 207 are bent in the pixel (the metal layer 270 disposed along the common electrode 205 and the pixel electrode 207). Is of course bent). This bending is for dividing the pixel into a plurality of domains. That is, the liquid crystal molecules of each domain are arranged symmetrically with the adjacent domains to compensate for the field of view, thereby improving the viewing angle characteristic. In the drawing, the common electrode 205 and the pixel electrode 207 are bent once to form two domains in the pixel, but the common electrode 205 and the pixel electrode 207 are bent a plurality of times to form three or more domains. It may be formed.

In addition, in FIG. 6, the data line 204 is bent in addition to the common electrode 205 and the pixel electrode 207 to form a plurality of domains. However, only the common electrode 205 and the pixel electrode 207 are bent and the data line ( 204 may also be an unbent structure.

As described above, in the present invention, an IPS mode liquid crystal display device is manufactured using three masks. Thus, the number of masks used by the conventional manufacturing method is reduced, resulting in a simplified manufacturing process and a significant reduction in manufacturing cost. In addition, in the present invention, since the light blocking metal layer is disposed under the common electrode and the pixel electrode formed of the transparent conductive layer to prevent light leakage from occurring through the common electrode and the pixel electrode, the image quality of the liquid crystal display device can be effectively prevented. It becomes possible.

Figure 1 (a) is a plan view of a conventional transverse electric field mode liquid crystal display device.

(B) is sectional drawing along the II 'line | wire of (a).

2 (a) to 2 (e) show a method of manufacturing a conventional IPS mode liquid crystal display device.

3 (a) to 3 (g) show a method of manufacturing an IPS mode liquid crystal display device according to the present invention.

4A is a diagram showing a transverse electric field formed between a common electrode and a pixel electrode.

Fig. 4B is an enlarged view of area A in Fig. 3G.

5 is a plan view showing the structure of an IPS mode liquid crystal display device according to the present invention;

6 is a plan view showing another structure of the IPS mode liquid crystal display device according to the present invention.

Explanation of symbols on the main parts of the drawings

103: gate line 104: data line

105: common electrode 107: pixel electrode

110: thin film transistor 111: gate electrode

112: semiconductor layer 113: source electrode

114: drain electrode 120,130: substrate

122: gate insulating layer 124: protective layer

170: metal layer

Claims (17)

A plurality of gate lines and data lines defining a plurality of pixels; A thin film transistor disposed in each pixel; At least one pair of transparent common and pixel electrodes disposed in the pixel to form a transverse electric field; And And a metal layer arranged along the data line and the common electrode to block light passing through the common electrode and the pixel electrode. The transverse electric field mode liquid crystal display device of claim 1, wherein the metal layer has a width smaller than that of the common electrode and the pixel electrode. The transverse electric field mode liquid crystal display device of claim 2, wherein the metal layer has a width of 65 to 75% of a width of the common electrode and the pixel electrode. The transverse electric field mode liquid crystal display device of claim 1, wherein the common electrode and the pixel electrode are made of a material selected from a group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), and tin oxide (TO). . The method of claim 1, wherein the thin film transistor, A gate electrode formed on the first substrate; A gate insulating layer formed on the gate electrode; A semiconductor layer formed on the gate insulating layer; And The transverse electric field mode liquid crystal display device comprising a source electrode and a drain electrode formed on the semiconductor layer. The method of claim 1, A common line disposed in the pixel and electrically connected to a common electrode; And And a pixel electrode line electrically connected to the pixel electrode, the pixel electrode line being disposed with the common line interposed therebetween to form a storage capacitor. The method of claim 1, Second substrate; A black matrix formed on the second substrate to block light from being transmitted to the image non-display area; And The transverse electric field mode liquid crystal display device further comprising a color filter layer for realizing color. The transverse electric field mode liquid crystal display device of claim 1, wherein the common electrode and the pixel electrode are bent at least once in a pixel to divide the pixel into a plurality of regions. Forming a gate electrode and a plurality of metal layers on the first substrate using the first mask; Forming a gate insulating layer on the first substrate; Forming a semiconductor layer, a source electrode, and a drain electrode on the gate insulating layer using a second mask; Forming a protective layer on the first substrate; And And forming at least one transparent common electrode and a pixel electrode disposed substantially parallel on the metal layer using a third mask to form a transverse electric field. The method of claim 9, wherein the forming of the gate electrode and the metal layer comprises: Laminating a metal over the first substrate; And Etching the metal to form a gate electrode and a metal layer. The method of claim 9, wherein the forming of the semiconductor layer, the source electrode, and the drain electrode includes: Stacking a semiconductor on the gate insulating layer; Depositing a metal on the semiconductor; And Etching the semiconductor and the metal. The method of claim 11, wherein etching the semiconductor and the metal comprises: Applying a photoresist on the metal layer; Developing the photoresist using a diffraction mask to form a first photoresist pattern; Etching metals and semiconductors using the first photoresist pattern; Ashing the first photoresist pattern to expose a portion of the etched metal layer; And Etching the exposed metal layer. The method of claim 9, wherein the forming of the common electrode and the pixel electrode comprises: Forming a second photoresist pattern on the protective layer; Etching the passivation layer and the gate insulating layer using the second photoresist pattern to form holes in the region where the metal layer is disposed; And Forming a transparent conductive layer on the upper portion and in the hole of the second photoresist pattern; And Lift-off the transparent conductive layer. The method of claim 13, wherein the transparent conductive layer is made of indium tin oxide (ITO) or indium zinc oxide (IZO). The method of claim 13, wherein the hole is formed wider than the width of the metal layer. The method of claim 15, wherein the common electrode and the pixel electrode are formed to have a wider width than the metal layer. The method of claim 9, Forming a black matrix and a color filter layer on the second substrate; Forming a liquid crystal layer on the first substrate and the second substrate; And And bonding the first substrate and the second substrate together.