KR20050111272A - Device of plasma display panel - Google Patents

Abstract

The present invention relates to a driving apparatus of a plasma display panel.

The present invention provides an integrated circuit unit for supplying a driving voltage to scan electrodes, a sustain pulse supply unit for supplying a sustain voltage to the integrated circuit unit, a setup supply unit for supplying a rising ramp waveform to the integrated circuit unit during a setup period, and the A set down supply for supplying a falling ramp waveform to the integrated circuit during the set down period, the setup supply including a setup switch for supplying a setup voltage and a ramp waveform supply for causing the setup voltage to rise with a constant slope; .

Description

Plasma Display Panel Driving Device {Device of Plasma Display Panel}

The present invention relates to a driving apparatus for a plasma display panel, and more particularly, to a driving apparatus for a plasma display panel having different switching elements operated in a reset period during driving of the plasma display panel.

In general, a plasma display panel (hereinafter referred to as "PDP") displays an image including a character or a graphic by emitting phosphors by 147 nm ultraviolet rays generated when a He + Xe or Ne + Xe inert mixed gas is discharged. Done. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

1 is a perspective view showing the structure of a conventional three-electrode AC surface discharge type PDP. Referring to FIG. 1, the three-electrode AC surface discharge type PDP includes a scan / sustain electrode 11a and a common sustain electrode 12a formed on the upper substrate 10, and an address electrode formed on the lower substrate 20. 22). Each of the scan / sustain electrode 11a and the common sustain electrode 12a is formed of a transparent electrode, for example, Indium-Tin-Oxide (ITO). Metal bus electrodes 11b and 12b for reducing resistance are formed in the scan / sustain electrode 11a and the common sustain electrode 12a, respectively. An upper dielectric layer 13a and a passivation layer 14 are stacked on the upper substrate 10 on which the scan / sustain electrode 11a and the common sustain electrode 12a are formed. Wall charges generated during plasma discharge are accumulated in the upper dielectric layer 13a. The protective layer 14 prevents damage to the upper dielectric layer 13a due to sputtering generated during plasma discharge, and increases emission efficiency of secondary electrons. As the protective film 14, magnesium oxide (MgO) is usually used.

Meanwhile, the lower dielectric layer 13b and the partition wall 21 are formed on the lower substrate 20 on which the address electrode 22 is formed, and the phosphor layer 23 is formed on the surfaces of the lower dielectric layer 13b and the partition wall 21. Is applied. The address electrode 22 is formed in the direction crossing the scan / sustain electrode 11a and the common sustain electrode 12a. The partition wall 21 is formed in parallel with the address electrode 22 to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 23 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe or Ne + Xe for discharging is injected into the discharge space of the discharge cells provided between the upper and lower substrates 10 and 20 and the partition wall 21. Looking at the driving method of the conventional PDP having such a structure as shown in FIG.

2 shows a method of driving a conventional PDP. Referring to FIG. 2, the PDP is driven by being divided into an initialization period for initializing all screens, an address period for selecting cells, and a sustain period for maintaining discharge of the selected cells.

In the initialization period (reset period), the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y in the setup period SU. This rising ramp waveform causes discharge to occur in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y. During the set down period SD, after the rising ramp waveform is supplied, the rising ramp waveform starts to drop at the positive voltage lower than the peak voltage of the rising ramp waveform and then falls to the base voltage GND or a specific voltage level of the negative ramp ramp. -down causes a slight erase discharge in the cells, thereby partially erasing the excessively formed wall charge. By this set down discharge, the wall charges such that the address discharge can stably occur remain uniformly in the cells.

In the address period, the negative scan pulse Scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X in synchronization with the scan pulse. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when a sustain voltage is applied. The sustain electrode Z is supplied with a positive polarity DC voltage Zdc during the set down period and the address period so as to reduce the voltage difference with the scan electrode Y so that an erroneous discharge with the scan electrode Y does not occur.

In the sustain period, a sustain pulse Su is applied to the scan electrodes Y and the sustain electrodes Z alternately. In the cell selected by the address discharge, as the wall voltage and the sustain pulse in the cell are added, a sustain discharge, that is, a display discharge occurs between the scan electrode Y and the sustain electrode Z every time the sustain pulse is applied.

After the sustain discharge is completed, a ramp waveform (Ramp-ers) having a small pulse width and a low voltage level is supplied to the sustain electrode Z to erase the wall charge remaining in the cells of the full screen.

Looking at the scan driving device for supplying a predetermined driving waveform in the conventional PDP is driven as shown in FIG.

3 is a view showing a Y electrode driving apparatus of a conventional PDP. As shown, the conventional Y electrode driving apparatus of the PDP includes a sustain pulse supply unit 40, a drive integrated circuit 48, a setup supply unit 42, a set-down supply unit 44, a negative scan voltage supply unit 46, and a scan. A reference voltage supply unit 50 and a seventh switch Q7 connected between the setup supply unit 42 and the drive integrated circuit 48 are provided.

The conventional PDP scan driving apparatus having such a structure generates a rising ramp waveform and a falling ramp waveform during a reset period. In this case, the operation exaggeration of each switch is as follows.

4 is a timing diagram illustrating a switching operation process in a conventional scan driving apparatus for generating a rising ramp waveform and a falling ramp waveform in the reset period of FIG. 3. A process of generating the setup and setdown voltages during the reset period will be described in detail with reference to FIG. 4. In FIG. 3, it is assumed that the second capacitor C2 is charged with the voltage of the setup voltage source Vst. It is assumed that the sustain voltage Vs is supplied from the sustain pulse supply unit 40 to the first node point n1 at the turn-on time of the fifth switch Q5.

Referring to FIG. 4, first, the fifth switch Q5 and the seventh switch Q7 are turned on during the setup period. At this time, the sustain voltage Vs is supplied from the sustain pulse supply unit 40. The sustain voltage Vs supplied from the sustain pulse supply unit 40 is connected to the scan electrode lines Y1 to Ym through the internal diode of the sixth switch Q6, the seventh switch Q7, and the drive integrated circuit 48. Is supplied. Therefore, the voltages of the scan electrode lines Y1 to Ym rise rapidly to Vs.

At this time, since the voltage of Vs is supplied to the negative terminal of the second capacitor C2, the second capacitor C2 supplies the voltage of Vs + Vst to the fifth switch Q5. The fifth switch Q5 supplies the voltage supplied from the second capacitor C2 to the first node point n1 with a predetermined slope while the channel width is adjusted by the first variable resistor VR1 installed at the front end thereof. do. The voltage applied with the predetermined slope to the first node point n1 is supplied to the scan electrode lines Y1 to Ym via the seventh switch Q7 and the drive integrated circuit 48. Therefore, the rising ramp waveform Ramp-up is supplied to the scan electrode lines Y1 to Ym.

The fifth switch Q5 is turned off after the rising ramp waveform Ramp-up is supplied to the scan electrode lines Y1 to Ym. When the fifth switch Q5 is turned off, only the voltage of Vs supplied from the sustain pulse supply unit 40 is applied to the first node point n1, so that the voltages of the scan electrode lines Y1 to Ym are changed to Vs. Descends sharply

Thereafter, the seventh switch Q7 is turned off and the tenth switch Q10 is turned on in the set down period. The tenth switch Q10 adjusts the channel width by the second variable resistor VR2 provided at the front end thereof, and writes the voltage of the second node n2 as a write scan voltage (-Vw) (or a setdown voltage source). Descend with a slope. At this time, the ramp ramp down (Ramp-down) is supplied to the scan electrode lines (Y1 to Ym).

The setup supply unit 42 and the set-down supply unit 44 supply the rising ramp waveforms Ramp-up and falling ramp waveforms to the scan electrode lines Y1 to Ym during the reset period while repeating the above process. do.

On the other hand, in order to supply the rising ramp waveform (Ramp-up) as the high voltage of Vs + Vst is gradually supplied to the fifth switch for a long time, heat due to the resistance is generated. This cause of heat generation appears as the fifth switch is operated in an active region in which the ramp waveform is raised. Therefore, in order to solve such a heat generation problem, an expensive switching device having high withstand voltage characteristics is used, which has a problem of increasing manufacturing cost in manufacturing a plasma display panel.

Accordingly, an object of the present invention is to provide a driving apparatus of a plasma display panel which can solve a heat generation problem and reduce a manufacturing cost by changing a circuit structure of a switching element operated during a reset period of a plasma display panel.

The driving apparatus of the plasma display panel of the present invention for achieving the above object is an integrated circuit unit for supplying a driving voltage to the scan electrodes, a sustain pulse supply unit for supplying a sustain voltage to the integrated circuit unit, during the setup period A setup supply for supplying a rising ramp waveform, and a set-down supply for supplying a falling ramp waveform to the integrated circuit for a set down period, wherein the setup supply comprises a setup switch for supplying a setup voltage and a slope at which the setup voltage is constant. And a ramp waveform supply for rising.

The ramp waveform supply unit includes a variable resistor and a capacitor, one end of which is connected to the source end of the setup switch, the other end of the variable resistor is connected to one end of the capacitor, and the other end of the capacitor is sus And a common terminal to which the other end of the variable resistor and one end of the capacitor are connected to the Y electrode terminal.

The setup switch is characterized in that the operation in the saturation region.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

5 is a view showing a Y electrode driving apparatus of the PDP according to the present invention. Prior to the description of the present invention, if each functional part of the Y electrode driving device is the same as each functional part of the conventional Y electrode driving device, the conventional reference numerals will be given. As shown, the Y electrode driving unit of the PDP of the present invention is a sustain pulse supply unit 40, a drive integrated circuit unit 48, a setup supply unit 42, a set down supply unit 44, a negative scan voltage supply unit 46, a scan A reference voltage supply unit 50 and a seventh switch Q7 connected between the setup supply unit 42 and the drive integrated circuit unit 48 are provided.

The drive integrated circuit unit 48 is connected in the form of a push-pull and has a voltage from the sustain pulse supply unit 40, the setup supply unit 42, the setdown supply unit 44, the negative scan voltage supply unit 46, and the scan reference voltage supply unit 50. The fourteenth and fifteenth switches Q14 and Q15 to which a signal is input are configured. The output line between the fourteenth and fifteenth switches Q14 and Q15 is connected to one of the scan electrode lines.

The sustain pulse supply unit 40 includes an external capacitor C1 for charging energy recovered from the scan electrode lines Y1 to Ym, and an inductor L1 connected between the external capacitor C1 and the drive integrated circuit 48. ) And a first switch Q1, a first diode D1, a second diode D2, and a second switch Q2 connected in parallel between the inductor L1 and the external capacitor C1. .

Referring to the operation process of the sustain pulse supply unit 40 as follows. First, it is assumed that the external capacitor C1 is charged with the voltage Vs / 2. When the first switch Q1 is turned on, the voltage charged in the external capacitor C1 is divided into the internal diodes of the first switch Q1, the first diode D1, the inductor L1, and the sixth switch Q6, and The drive integrated circuit 48 is supplied to the drive integrated circuit 48 via the seventh switch Q7, and the drive integrated circuit 48 supplies the voltage supplied thereto to the scan electrode lines Y1 to Ym.

At this time, since the inductor L1 constitutes a series LC resonant circuit together with the capacitance C of the PDP discharge cell, a voltage of Vs is supplied to the scan electrode lines Y1 to Ym. Thereafter, the third switch Q3 is turned on. When the third switch Q3 is turned on, the sustain voltage Vs is supplied to the drive integrated circuit 48 through the internal diode of the sixth switch Q6 and the seventh switch Q7. The drive integrated circuit 48 supplies the sustain voltage supplied thereto to the scan electrode lines Y1 to Ym. Due to the sustain voltage Vs, the voltage level on the scan electrode lines Y1 to Ym maintains the sustain voltage Vs, thereby causing sustain discharge in the discharge cells. After the sustain discharge occurs in the discharge cells, the second switch Q2 is turned on. When the second switch Q2 is turned on, the scan electrode lines Y1 to Ym, the drive integrated circuit 48, the internal diodes of the seventh switch Q7, the sixth switch Q6, the inductor L1, The second capacitor D2 and the second switch Q2 are recovered to the external capacitor C1 in addition to the reactive power. That is, energy from the PDP is recovered to the external capacitor C1. Subsequently, the fourth switch Q4 is turned on to maintain the voltage on the scan electrode lines Y1 to Ym at the ground potential GND.

In this way, the sustain pulse supply unit 40 recovers energy from the PDP, and then supplies voltage to the scan electrode lines Y1 to Ym using the recovered energy to reduce excessive power consumption during discharge during the setup period and the sustain period. do.

The negative scan voltage supply unit 46 includes an eleventh switch Q11 connected between the third node n3 and the write scan voltage source -Vw. The eleventh switch Q11 is switched in response to a control signal supplied from a timing controller not shown during the address period of the selective write subfield WSF to supply the write scan voltage -Vw to the drive integrated circuit 48. .

The scan reference voltage supply unit 50 is a third capacitor C3 connected between the reference voltage source Vsc and the second node n2, and an eighth connected between the reference voltage source Vsc and the second node n2. A switch Q8 and a ninth switch Q9 are provided. The eighth switch Q8 and the ninth switch Q9 are supplied by the control signal supplied from the timing controller during the selective write address period to supply the voltage of the reference voltage source Vsc to the drive integrated circuit 52. The third capacitor C3 adds the voltage applied to the second node n2 and the voltage value of the reference voltage source Vsc to the eighth switch Q8.

The set-down supply unit 44 includes a tenth switch Q10 connected between the second node n2 and the write scan voltage -Vw. The set-down supply unit 44 gradually lowers the voltage supplied to the drive integrated circuit 48 with the slope to the write scan voltage (-Vw) during the set-down period included in the reset period of the selective write subfield. Here, the write scan voltage (-Vw) is used as the set down voltage source.

The setup supply 42 is a setup switch Q5 for supplying a setup voltage between the setup voltage source Vst and the sustain pulse supply 40, and the setup voltage rises at a constant slope to supply the scan Y electrode. The ramp waveform supply part 42a is provided.

The setup switch Q5 is turned on according to a timing signal to operate in a saturation region, and supplies a setup voltage to the ramp waveform supply 42a. This setup voltage is applied to a capacitor C2 'installed in the ramp waveform supply 42a.

On the other hand, the capacitor C2 forms a rising ramp waveform that gradually increases together with the variable resistor VR1 'connected between the setup switch Q5 and the capacitor C2'. That is, the ramp waveform supply 42a includes the variable resistor VR1 'and the capacitor C2' to supply the rising ramp waveform to the scan Y electrode during the setup period.

One end of the variable resistor VR1 'is connected to the source terminal of the setup switch Q5, and the other end of the variable resistor VR1' is connected to one end of the capacitor C2 '.

In addition, the other end of the capacitor C2 'is connected to the sustain pulse supply unit 40, and the common end connected to the other end of the variable resistor VR1' and one end of the capacitor C2 'is a scan (Y) electrode end. Is connected to.

In this way, the setup switch Q5 formed in the setup supply part 42 of the present invention is operated in a saturation region rather than an active region during the conventional setup period, so that no heat is generated. This makes it possible to use a low current set-up switching element under the same voltage, resulting in lower manufacturing costs.

As described above, it will be understood by those skilled in the art that the above-described technical configuration may be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, the above-described embodiments are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

As described above, the present invention has the effect of solving the heat generation problem of the switching element according to the rising ramp waveform of the plasma display panel in the scan driving device, and also reduce the manufacturing cost.

1 is a perspective view showing the structure of a conventional three-electrode AC surface discharge type PDP.

2 is a view showing a driving method of a conventional PDP.

3 is a view showing a Y electrode driving device of a conventional PDP.

4 is a timing diagram illustrating a switching operation process in a conventional scan driving apparatus for generating a rising ramp waveform and a falling ramp waveform in the reset period of FIG.

5 is a view showing a Y electrode driving apparatus of the PDP according to the present invention;

***** Explanation of symbols for the main parts of the drawing *****

40: sustain pulse supply 42: setup supply

44: set down supply 46: scan voltage supply

48: drive integrated circuit 50: scan reference voltage supply

Claims (3)

An integrated circuit unit supplying a driving voltage to the scan electrodes; A sustain pulse supply unit for supplying a sustain voltage to the integrated circuit unit; A setup supply unit for supplying a rising ramp waveform to the integrated circuit during a setup period; And A set down supply for supplying a falling ramp waveform to the integrated circuit for a set down period; And the setup supply unit comprises a setup switch for supplying a setup voltage and a ramp waveform supply unit for causing the setup voltage to rise with a constant slope. The method of claim 1, The ramp waveform supply unit includes a variable resistor and a capacitor, One end of the variable resistor is connected to the source end of the setup switch, the other end of the variable resistor is connected to one end of the capacitor, The other end of the capacitor is connected to a sus end, And a common end to which the other end of the variable resistor and one end of the capacitor are connected to a scan electrode end. The method of claim 1, And the setup switch is operated in a saturation region.