KR20050105835A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20050105835A KR20050105835A KR1020040031107A KR20040031107A KR20050105835A KR 20050105835 A KR20050105835 A KR 20050105835A KR 1020040031107 A KR1020040031107 A KR 1020040031107A KR 20040031107 A KR20040031107 A KR 20040031107A KR 20050105835 A KR20050105835 A KR 20050105835A
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000005468 ion implantation Methods 0.000 claims abstract description 27
- 150000002500 ions Chemical class 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0405—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising semiconducting carbon, e.g. diamond, diamond-like carbon
- H01L21/041—Making n- or p-doped regions
- H01L21/0415—Making n- or p-doped regions using ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 소자의 크기를 감소시킬 수 있는 반도체 소자의 제조방법을 개시한다. 개시된 본 발명의 방법은, 고전압 영역과 저전압 영역으로 구성되는 반도체 기판을 제공하는 단계; 상기 기판의 고전압 영역에 N웰 및 P웰 영역 형성하는 단계; 상기 기판 내에 소자분리막을 형성하는 단계; 상기 기판의 고전압 영역 및 저전압 영역에 고전압용 게이트 산화막을 형성하는 단계; 상기 고전압 영역의 문턱전압을 조절하기 위해 이온주입 공정을 실시하는 단계; 상기 기판의 저전압 영역에 형성된 고전압용 게이트 산화막을 제거하는 단계; 상기 기판의 고전압 영역에 N형 불순물 이온을 주입하여 드리프트 영역을 형성하는 단계; 상기 기판의 저전압 영역에 N웰 영역을 형성하고, 문턱전압을 조절하기 위해 1차 이온주입 공정을 실시하는 단계; 상기 기판의 저전압 영역에 P웰 영역을 형성하고, 문턱전압을 조절하기 위해 2차 이온주입 공정을 실시하는 단계; 상기 기판의 저전압 영역 상에 저전압용 게이트 산화막을 증착하여 저전압용 게이트를 형성하는 단계; 상기 기판의 고전압 영역에 고전압용 게이트를 형성하는 단계; 상기 저전압용 게이트 양측 기판 상에 이온주입 공정을 실시하여 LDD 영역을 형성하는 단계; 및 상기 저전압용 게이트 양측 기판 상에 이온주입 공정을 실시하여 소오스/드레인 영역을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention discloses a method for manufacturing a semiconductor device capable of reducing the size of the device. The disclosed method includes providing a semiconductor substrate comprised of a high voltage region and a low voltage region; Forming N well and P well regions in the high voltage region of the substrate; Forming an isolation layer in the substrate; Forming a high voltage gate oxide film in a high voltage region and a low voltage region of the substrate; Performing an ion implantation process to adjust the threshold voltage of the high voltage region; Removing the high voltage gate oxide film formed in the low voltage region of the substrate; Implanting N-type impurity ions into the high voltage region of the substrate to form a drift region; Forming an N well region in a low voltage region of the substrate and performing a primary ion implantation process to adjust a threshold voltage; Forming a P well region in the low voltage region of the substrate and performing a secondary ion implantation process to adjust a threshold voltage; Depositing a low voltage gate oxide layer on the low voltage region of the substrate to form a low voltage gate; Forming a high voltage gate in a high voltage region of the substrate; Forming an LDD region by performing an ion implantation process on both substrates of the low voltage gate; And forming a source / drain region by performing an ion implantation process on both substrates of the low voltage gate.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 소자의 크기를 감소시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of reducing the size of the device.
씨모스 로직(CMOS Logic) 소자 제조기술은 LCD 드라이버 칩과 같이 많은 분야에 적용되는 기술이며, 머지드 로직 회로(Merged Logic Circuit)와 함께 칩 제조에 사용된다. 따라서, 칩 크기를 감소시키기 위해 로직 제조 기술의 선폭이 지속적으로 미세화 되고 있다.CMOS logic device manufacturing technology is applied to many fields such as LCD driver chip, and is used in chip manufacturing together with merged logic circuit. As a result, the line width of logic fabrication techniques continues to be miniaturized to reduce chip size.
종래 30V용 이하 및 이상의 고전압 소자 제조기술은 고전압 영역(High Voltage Region : HVR)의 웰형성과 소오스/드레인 형성에서 내압특성을 확보하기 위해 고온 및 장시간의 어닐링 공정을 실시하게 되는데, 이때에 소오스/드레인 영역에 측면확산이 발생되며, 단채널 특성을 확보하기 위해 채널 길이(Channel Length)를 확대해야 했다. 이로 인해 소자의 크기가 커지는 단점이 있다.Conventional high voltage device manufacturing technology for 30V and above uses high temperature and long time annealing process to secure breakdown voltage characteristics in well voltage and source / drain formation of high voltage region (HVR). Side diffusion occurs in the drain region, and the channel length has to be enlarged to secure short channel characteristics. This has the disadvantage of increasing the size of the device.
또한, 고전압 소자 제조시 고전압 영역와 저전압 영역(Low Voltage Region : LVR)의 게이트 절연막 두께 차이로 인해 고전압 및 저전압 영역에 소오스/드레인 이온주입시 이온주입 깊이가 저전압 영역에 맞춰져 있으므로, 고전압 영역은 이미 증착된 두꺼운 산화막으로 인하여 도펀트(Dopant)가 차단되어 오믹 콘택(Ohmic Contact) 형성이 어려웠다.Also, due to the difference in gate insulating film thickness between the high voltage region and the low voltage region (LVR), the ion implantation depth is set to the low voltage region when source / drain ions are implanted in the high voltage region and the low voltage region. Due to the thick oxide film, dopants were blocked, making it difficult to form ohmic contacts.
그리고, 기존 공정에서는 LDD 스페이서 식각시 고전압 영역에 잔류된 게이트 산화막을 조절하여 소오스/드레인 이온주입을 실시하였으나, 소자 선폭의 감소 및 저전압 영역의 게이트 산화막이 얇게 증착됨으로 인해 LDD 스페이서 식각 조건을 조절하기가 어렵다.In the conventional process, the source / drain ion implantation was performed by controlling the gate oxide film remaining in the high voltage region during LDD spacer etching, but the LDD spacer etching condition was controlled due to the reduction of the device line width and the thin deposition of the gate oxide film in the low voltage region. Is difficult.
따라서, 본 발명은 상기와 같은 종래 문제점을 해결하기 위해 안출된 것으로서, 소자의 크기를 감소시킬 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of reducing the size of the device, which is devised to solve the conventional problems as described above.
상기와 같은 목적을 달성하기 위한 본 발명의 방법은, 고전압 영역과 저전압 영역으로 구성되는 반도체 기판을 제공하는 단계; 상기 기판의 고전압 영역에 N웰 및 P웰 영역 형성하는 단계; 상기 기판 내에 소자분리막을 형성하는 단계; 상기 기판의 고전압 영역 및 저전압 영역에 고전압용 게이트 산화막을 형성하는 단계; 상기 고전압 영역의 문턱전압을 조절하기 위해 이온주입 공정을 실시하는 단계; 상기 기판의 저전압 영역에 형성된 고전압용 게이트 산화막을 제거하는 단계; 상기 기판의 고전압 영역에 N형 불순물 이온을 주입하여 드리프트 영역을 형성하는 단계; 상기 기판의 저전압 영역에 N웰 영역을 형성하고, 문턱전압을 조절하기 위해 1차 이온주입 공정을 실시하는 단계; 상기 기판의 저전압 영역에 P웰 영역을 형성하고, 문턱전압을 조절하기 위해 2차 이온주입 공정을 실시하는 단계; 상기 기판의 저전압 영역 상에 저전압용 게이트 산화막을 증착하여 저전압용 게이트를 형성하는 단계; 상기 기판의 고전압 영역에 고전압용 게이트를 형성하는 단계; 상기 저전압용 게이트 양측 기판 상에 이온주입 공정을 실시하여 LDD 영역을 형성하는 단계; 및 상기 저전압용 게이트 양측 기판 상에 이온주입 공정을 실시하여 소오스/드레인 영역을 형성하는 단계를 포함하는 것을 특징으로 한다.The method of the present invention for achieving the above object comprises the steps of providing a semiconductor substrate consisting of a high voltage region and a low voltage region; Forming N well and P well regions in the high voltage region of the substrate; Forming an isolation layer in the substrate; Forming a high voltage gate oxide film in a high voltage region and a low voltage region of the substrate; Performing an ion implantation process to adjust the threshold voltage of the high voltage region; Removing the high voltage gate oxide film formed in the low voltage region of the substrate; Implanting N-type impurity ions into the high voltage region of the substrate to form a drift region; Forming an N well region in a low voltage region of the substrate and performing a primary ion implantation process to adjust a threshold voltage; Forming a P well region in the low voltage region of the substrate and performing a secondary ion implantation process to adjust a threshold voltage; Depositing a low voltage gate oxide layer on the low voltage region of the substrate to form a low voltage gate; Forming a high voltage gate in a high voltage region of the substrate; Forming an LDD region by performing an ion implantation process on both substrates of the low voltage gate; And forming a source / drain region by performing an ion implantation process on both substrates of the low voltage gate.
여기에서, 상기 기판의 저전압 영역에 P웰 영역을 형성하는 단계는 상기 기판의 저전압 영역에 P웰 영역을 형성함과 동시에 고전압 영역에 PMOS 트랜지스터를 형성하기 위해 불순물 이온을 주입하여 소오스/드레인 영역을 형성하는 것을 특징으로 한다. The forming of the P well region in the low voltage region of the substrate may include forming a P well region in the low voltage region of the substrate and implanting impurity ions to form a PMOS transistor in the high voltage region to form a source / drain region. It is characterized by forming.
(실시예)(Example)
이하, 본 발명의 바람직한 실시예에 대해 첨부된 도면을 참조하여 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도이다.1A to 1D are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
도 1a에 도시된 바와 같이, 고전압 영역(HVR)과 저전압 영역(LVR)으로 구성되는 반도체 기판(21)을 마련한다. 그 다음, 상기 기판(21) 상의 고전압 영역(HVR)에 이온주입 공정을 진행하여 N웰 및 P웰 영역(22a, 22b)을 형성한 후에 상기 기판(21) 내에 STI 공정을 진행하여 소자분리막(23)을 형성한다.As shown in FIG. 1A, a semiconductor substrate 21 including a high voltage region HVR and a low voltage region LVR is provided. Next, an ion implantation process is performed in the high voltage region HVR on the substrate 21 to form N wells and P well regions 22a and 22b, and then an STI process is performed in the substrate 21 to form an element isolation film ( 23).
이어서, 상기 기판(21)의 고전압 영역(HVR) 및 저전압 영역(LVR) 상에 고전압용 게이트 산화막(24)을 형성한 다음, 고전압 영역(HVR)의 트랜지스터 문턱전압을 조절하기 위해 이온주입 공정을 실시한다.Subsequently, a high voltage gate oxide layer 24 is formed on the high voltage region HVR and the low voltage region LVR of the substrate 21, and then an ion implantation process is performed to adjust the transistor threshold voltage of the high voltage region HVR. Conduct.
도 1b에 도시된 바와 같이, 상기 기판(21)의 저전압 영역(LVR)에 형성된 고전압용 게이트 산화막(24)을 제거한 다음, 기판 상의 고전압 영역(HVR)에 N형 불순물 이온을 주입하여 드리프트 영역(Drift : 25a, 25b)을 형성한다. 그 다음, 저전압 영역(LVR)에 N웰 영역(26a)을 형성하고, 트랜지스터의 문턱전압을 조절하기 위해 1차 이온주입 공정을 실시한다. As shown in FIG. 1B, the high voltage gate oxide layer 24 formed in the low voltage region LVR of the substrate 21 is removed, and then N-type impurity ions are implanted into the high voltage region HVR on the substrate to drift the region. Drift: 25a, 25b). Next, the N well region 26a is formed in the low voltage region LVR, and a primary ion implantation process is performed to adjust the threshold voltage of the transistor.
이어서, 저전압 영역(LVR)에 P웰 영역(26b)을 형성한 후에 저전압 영역(LVR)에 트랜지스터의 문턱전압을 조절하기 위해 2차 이온주입 공정을 실시한다. 이때, 저전압 영역(LVR)에 P웰 영역을 형성함과 동시에 고전압 영역(HVR)에 PMOS 트랜지스터를 형성하기 위한 불순물 이온을 주입하여 소오스/드레인 영역(27a, 27b)을 형성한다. Subsequently, after forming the P well region 26b in the low voltage region LVR, a secondary ion implantation process is performed to adjust the threshold voltage of the transistor in the low voltage region LVR. At this time, the P well region is formed in the low voltage region LVR, and the source / drain regions 27a and 27b are formed by implanting impurity ions for forming the PMOS transistor in the high voltage region HVR.
여기에서, 소오스/드레인 형성시 비확산형 이온주입 공정을 실시하게 되면 종래 소오스/드레인 형성시 확산형 이온주입 공정으로 인해 발생하는 단채널 현상 방지 및 반도체 소자의 내압 특성을 확보할 수 있으므로, 반도체 소자의 크기를 감소시킬 수 있다.Here, if the non-diffusion ion implantation process is performed at the time of source / drain formation, it is possible to prevent short channel phenomenon caused by the diffusion type ion implantation process at the time of source / drain formation and to ensure the breakdown voltage characteristics of the semiconductor device. Can reduce the size.
도 1c에 도시된 바와 같이, 상기 기판(21)의 저전압 영역(LVR) 상에 저전압용 게이트 산화막(28) 및 폴리실리콘막(29)을 형성한다. 이어서, 상기 폴리실리콘막(29) 및 게이트 산화막(28)을 식각하여 하여 저전압 영역(LVR) 영역 상에 저전압용 게이트(30a)를 형성한다.As shown in FIG. 1C, a low voltage gate oxide layer 28 and a polysilicon layer 29 are formed on the low voltage region LVR of the substrate 21. Subsequently, the polysilicon layer 29 and the gate oxide layer 28 are etched to form the low voltage gate 30a on the low voltage region LVR region.
그 다음, 상기 기판(21) 상의 고전압 영역(HVR)에 형성된 폴리실리콘막(29) 및 게이트 산화막(24)을 식각하여 고전압 영역(HVR) 상에 고전압용 게이트(30b)를 형성하고, 저전압 게이트(30a) 및 고전압용 게이트(30b) 양측벽에 스페이서(31)를 형성한다.Next, the polysilicon layer 29 and the gate oxide layer 24 formed in the high voltage region HVR on the substrate 21 are etched to form the high voltage gate 30b on the high voltage region HVR, and the low voltage gate Spacers 31 are formed on both side walls 30a and the high voltage gate 30b.
이때, 0.18um 로직 공정(Logic Process) 진행시 상대적으로 저전압 영역(LVR) 영역의 게이트 산화막이 현저히 낮아졌으므로, 저전압용 게이트와 고전압용 게이트를 분리하여 형성함으로써 스페이서 식각공정에 의한 저전압 영역(LVR)의 과다 식각을 방지할 수 있다.At this time, since the gate oxide layer of the low voltage region (LVR) region is significantly lowered during the 0.18um logic process, the low voltage region (LVR) by the spacer etching process is formed by separating the low voltage gate and the high voltage gate. It can prevent the excessive etching.
도 1d에 도시된 바와 같이, 상기 저전압용 게이트(30a) 양측 기판 상에 이온주입 공정을 실시하여 LDD 영역(32a, 32b)을 형성한다. 이어서, 상기 저전압용 게이트(30a) 양측의 기판 상에 이온주입 공정을 실시하여 소오스/드레인 영역(33a, 33b)을 형성한다.As illustrated in FIG. 1D, the LDD regions 32a and 32b are formed by performing an ion implantation process on both substrates of the low voltage gate 30a. Subsequently, an ion implantation process is performed on the substrates on both sides of the low voltage gate 30a to form source / drain regions 33a and 33b.
이후, 공지의 후속 공정을 진행하여 반도체 소자를 완성한다.Thereafter, a known subsequent process is performed to complete the semiconductor device.
이상, 본 발명을 몇 가지 예를 들어 설명하였으나, 본 발명은 이에 한정되는 것은 아니며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 본 발명의 사상에서 벗어나지 않으면서 많은 수정과 변형을 가할 수 있음을 이해할 것이다.In the above, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and a person of ordinary skill in the art may make many modifications and variations without departing from the spirit of the present invention. I will understand.
이상에서와 같이, 본 발명은 고전압 영역(HVR)에 드리프트 형성 및 PMOS 트랜지스터를 형성하기 위한 이온주입 공정에서 비확산형 이온주입 공정을 실시하여 단채널 현상 방지 및 반도체 소자의 내압 특성을 확보할 수 있으므로, 반도체 소자의 크기를 감소시킬 수 있다.As described above, the present invention can prevent the short-channel phenomenon and the breakdown voltage characteristics of the semiconductor device by performing a non-diffusion ion implantation process in the ion implantation process for forming drift and PMOS transistor in the high voltage region (HVR). The size of the semiconductor device can be reduced.
또한, 본 발명은 0.18um 로직 공정(Logic Process) 진행시 저전압용 게이트와 고전압용 게이트를 분리하여 형성함으로써 스페이서 식각공정에 의한 저전압 영역(LVR)의 과다 식각을 방지할 수 있다.In addition, the present invention can prevent the over-etching of the low voltage region (LVR) by the spacer etching process by separating and forming the low voltage gate and the high voltage gate during the 0.18um logic process.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.1A to 1D are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 * Explanation of symbols on the main parts of the drawings
21 : 반도체 기판 22a, 22b : N웰 및 P웰 영역21: semiconductor substrate 22a, 22b: N well and P well region
23 : 소자분리막 24 : 고전압용 게이트 산화막23 device isolation layer 24 high-voltage gate oxide film
25a, 25b : 드리프트 영역 28 : 저전압용 게이트 산화막25a, 25b: Drift region 28: Low-gate gate oxide film
29 : 폴리실리콘막 30a : 저전압용 게이트 29: polysilicon film 30a: low voltage gate
30b : 고전압용 게이트 31 : 스페이서30b: high voltage gate 31 spacer
32a, 32b : LDD 영역 33a, 33b : 소오스/드레인 영역32a, 32b: LDD region 33a, 33b: source / drain region
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