KR20050104962A - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention discloses a semiconductor device manufacturing method for controlling short channel effects. The disclosed semiconductor device manufacturing method includes forming a gate electrode on a semiconductor substrate; Tilting nitrogen in the substrate on both sides of the gate electrode; Pocket ion implantation with an n-type dopant in the nitrogen-implanted substrate; Forming an LDD region by implanting ions into the surface of the substrate on both sides of the gate electrode; Forming spacers on both sidewalls of the gate electrode; Implanting ions into the surface of the substrate on both sides of the gate electrode to form a deep source / drain region; And heat treating the resultant substrate.

Description

Semiconductor device manufacturing method {Method For Manufacturing Semiconductor Device}

The present invention relates to a semiconductor device manufacturing method, and more particularly, to a semiconductor device manufacturing method for controlling the short channel effect.

Recently, MOSFETs have been rapidly developed to enable miniaturization and high performance. However, as device integration increases, the reverse short channel effect (RSCE) and short channel effect, which are a phenomenon in which the threshold voltage increases as the gate length becomes shorter, are increasing.

In order to overcome this problem, the currently used technique is a method of pocket ion implantation of counter dopant, LDD (Lightly Doped Drain) or the opposite type of dopant, and thermal budget The trend is decreasing. However, even with all these methods, it is not easy to control short channel effects at present.

In addition, in order to miniaturize the MOS transistor to 0.18 μm or less in accordance with the trend of miniaturization of semiconductor device design rules, thinning of the gate insulating film thickness, the relationship between the circuit and the device, and source / drain and channel stabilization are necessary. This is described in more detail with respect to the stabilization of the channel as follows.

As the device becomes smaller, shallow junctions must be formed in order to reduce short channel effects caused by shorter channel lengths. Accordingly, the external resistance increases due to source / drain expansion and overlapping gate electrodes. Will deteriorate the saturation current value.

As described above, in order to compensate for the short channel effect caused by the extension of the source / drain and the overlap of the gate electrode, the doping profile of the channel region should be improved. Super Steep Retrograde Well and Halo Implant.

SSRW is a method of changing the one-dimensional doping profile by increasing the concentration of the well profile inside the substrate rather than the substrate surface, and halo implant is a method of forming a two-dimensional doping profile near the source / drain.

Due to the horizontal diffusion of B (boron) in the conventional halo implant, it is difficult to control the short channel effect.

Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device that can control a short channel effect using nitrogen tilt ion implantation and a low temperature thermal process.

The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a gate electrode on a semiconductor substrate; Tilting nitrogen into a substrate using the gate electrode as a mask; Pocket ion implantation with an n-type dopant in the nitrogen-implanted substrate; Forming an LDD region in the substrate surface on both sides of the gate electrode; Forming spacers on both sidewalls of the gate electrode; And forming deep source / drain regions in the substrate surface on both sides of the gate electrode.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1A, after the gate electrode 12 is formed on the silicon substrate 11, nitrogen tilt ion implantation is performed. Reference numeral 13 denotes a portion where nitrogen tilt ion implantation is performed. In this case, nitrogen is injected in the form of N + or N2 +, and injected by rotating two times in a direction perpendicular to the gate direction in the state of 5 to 60 ° tilt, or by rotating four times in a vertical direction or in a parallel direction. Can be. At this time, the ion implantation energy used is deeper than the B profile of the deep source / drain ion implantation when viewed only by the implantation profile, and the energy of 5 to 80 keV is located between the depths of the n-type dopants implanted during the pocket ion implantation. Add 1E14-1E16 / cm2 dose by adding

Next, pocket ion implantation is performed with an n-type dopant. Reference numeral 14 denotes a portion where the forge ion implantation is performed. In this case, P (phosphorus), As (arsenic), Sb (antimony), etc. may be used as the pocket ion implantation dopant. However, since the pocket ion implantation profile is not preferable to be spread by the thermal process, the atomic weight is preferably as high as possible to minimize diffusion. Use dopants. In addition, when a dopant having a large atomic weight is used, the B profile can be more easily controlled by N being distributed here by the fine defects generated at this time. The pocket ion implantation also proceeds with a tilt angle of 5 to 60 °.

Referring to FIG. 1B, an LDD region 15 is formed in the substrate 21, and spacers 16 are formed on both sidewalls of the gate electrode 12. In order to prevent the change of the N profile when forming the spacer, the spacer film is deposited at a low temperature as much as possible. Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD) is used to achieve a total thermal budget of less than one hour at temperatures below 750 ° C. The structure of the nitride film / oxide film or the oxide film / nitride film / oxide film is made.

Referring to FIG. 1C, ion implantation is performed in both substrates of the gate electrode 12 to form a deep source / drain region 17, and then rapid heat treatment is performed on the resultant of the substrate. At this time, during the rapid heat treatment, a normal rapid heat treatment method that proceeds within 1 minute in an N 2 atmosphere at a temperature of 950 to 1100 ° C. may be used, and a spike spike heat treatment method where the thermal budget is as small as possible may be used. The spike rapid heat treatment is carried out in an N2 atmosphere in which N2 or 1% or less of O2 is mixed at a temperature of 950 to 1150 ° C, and the temperature increase rate is 100 ° C / sec or more and the temperature reduction rate is 50 ° C / sec or more.

In addition, in order to prevent outgassing of the dopant, a rapid heat treatment may be performed on the substrate result after deposition of an inter layer dielectric (ILD) material. Alternatively, the rapid heat treatment may be carried out in rapid annealing process at a low temperature of 600 ~ 750 ° C followed by an annealing process for activation.

Thereafter, a known subsequent process is performed to complete the semiconductor device.

As described above, the present invention can control the short channel effect of the PMOS transistor by suppressing the side diffusion of boron by using nitrogen tilt ion implantation and low temperature heat process in addition to the pocket ion implantation in manufacturing a semiconductor device.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

11 substrate 12 gate electrode

13: portion injected with nitrogen tilt ion 14: portion injected with pocket ion with n-type dopant

15, 15a: LDD region 16: spacer

17: deep source / drain regions

Claims (6)

Forming a gate electrode on the semiconductor substrate; Tilting nitrogen in the substrate on both sides of the gate electrode; Pocket ion implantation with an n-type dopant in the nitrogen-implanted substrate; Forming an LDD region by implanting ions into the surface of the substrate on both sides of the gate electrode; Forming spacers on both sidewalls of the gate electrode; Implanting ions into the surface of the substrate on both sides of the gate electrode to form a deep source / drain region; And A semiconductor device manufacturing method comprising the step of heat treatment for the substrate product. According to claim 1, wherein the tilt ion implantation in the tilting state 5 to 60 ° tilting two times in the direction perpendicular to the gate direction, the tilt ion implantation, or rotated four times in the direction perpendicular to or parallel to the gate direction tilt ion Injecting a semiconductor device manufacturing method characterized in that. The semiconductor device manufacturing method of claim 1, wherein the ion implantation is performed by applying an energy of 5 to 80 keV to the pocket ion implantation. The method of claim 1. The method of manufacturing a semiconductor device, characterized in that the tilt ion implantation at a dose of 1E14 ~ 1E16 / ㎠ at the time of the pocket ion implantation. The method of claim 1, wherein a low pressure chemical vapor deposition method or a plasma chemical vapor deposition method is used to form a thermal budget of less than 1 hour at a temperature of 750 ° C. or lower. Method of manufacturing a semiconductor device characterized in that the structure of. The method of claim 1, wherein the heat treatment is performed at a ramp-up rate of 100 ° C./sec or higher and a ramp-down rate of 50 ° C./sec or higher and a temperature of 950-1150 ° C. and N 2 or 1%. The semiconductor device manufacturing method characterized by performing in the N2 atmosphere which mixed the following O2.