KR20050104088A - Method for forming contact hole in semiconductor device - Google Patents
Method for forming contact hole in semiconductor device Download PDFInfo
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- KR20050104088A KR20050104088A KR1020040029322A KR20040029322A KR20050104088A KR 20050104088 A KR20050104088 A KR 20050104088A KR 1020040029322 A KR1020040029322 A KR 1020040029322A KR 20040029322 A KR20040029322 A KR 20040029322A KR 20050104088 A KR20050104088 A KR 20050104088A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Abstract
본 발명은 키오픈 식각공정없이도 하부막과의 정렬이 가능한 반도체소자의 콘택홀 형성 방법을 제공하기 위한 것으로, 정렬키지역과 콘택지역이 정의된 반도체 기판의 콘택지역 상부에 하부막을 형성하는 단계, 상기 하부막을 포함한 전면에 층간절연막을 형성하는 단계, 상기 층간절연막을 일부 식각하여 상기 정렬키지역에 정렬키를 형성하는 단계, 상기 정렬키가 형성된 층간절연막 상에 질화막과 산화막을 차례로 형성하는 단계, 상기 산화막을 선택적으로 식각하여 상기 정렬키지역을 모두 덮는 제1부분과 콘택홀 예정지역을 덮고 나머지 상기 콘택지역을 오픈시키는 제2부분으로 이루어진 산화막패턴을 형성하는 단계, 상기 산화막패턴의 제2부분에 의해 오픈된 지역을 채우는 금속하드마스크패턴을 형성하는 단계, 상기 금속하드마스크패턴을 식각마스크로 상기 산화막패턴을 모두 제거하는 단계, 상기 금속하드마스크패턴을 식각마스크로 질화막과 층간절연막을 식각하여 상기 하부막의 표면을 오픈시키는 콘택홀을 형성하는 단계, 및 상기 금속하드마스크패턴을 제거하는 단계를 포함한다.The present invention provides a method for forming a contact hole in a semiconductor device that can be aligned with a lower layer without a key open etching process, the method comprising: forming a lower layer on an upper contact region of a semiconductor substrate in which an alignment key region and a contact region are defined; Forming an interlayer insulating film on the entire surface including the lower layer, forming an alignment key in the alignment key region by partially etching the interlayer insulating film, and sequentially forming a nitride film and an oxide film on the interlayer insulating film on which the alignment key is formed; Selectively etching the oxide layer to form an oxide pattern including a first portion covering all of the alignment key regions and a second portion covering a contact hole planned region and opening the remaining contact region, the second portion of the oxide pattern Forming a metal hard mask pattern that fills the open area by the metal hard mask pattern; Removing all of the oxide layer pattern with each mask, forming a contact hole to open the surface of the lower layer by etching the nitride layer and the interlayer insulating layer with the metal hard mask pattern as an etch mask, and removing the metal hard mask pattern It includes a step.
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체소자의 콘택홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for forming contact holes in a semiconductor device.
반도체 소자의 제조 공정이 복잡해지고 집적도가 증가함에 따라서 기판 상에 형성되는 개별 반도체소자들이 더욱 미세한 패턴으로 형성되어야 한다. 노광기술의 한계로 인하여 포토레지스트의 높이를 낮추어야 이러한 미세패턴을 형성할 수 있다. 그러나, 반도체소자의 집적도가 증가할수록 매우 작은 선폭을 유지하면서도 높은 종횡비(Aspect raion)를 가지는 콘택홀을 형성해야 하는데, 산화막 대 포토레지스트막의 식각선택비는 한정적이므로 높은 종횡비의 콘택홀 식각을 위하여는 두꺼운 포토레지스트막을 필요로 하므로 원하는 선폭을 유지할 수 없게 되는 결과를 초래한다. 따라서 이러한 포토레지스트막은 집적도가 높은 반도체 소자의 제조시 마스크의 역할을 수행하는 데 한계가 있게 된다. As the manufacturing process of semiconductor devices becomes complicated and the degree of integration increases, individual semiconductor devices formed on a substrate must be formed in a finer pattern. Due to the limitation of the exposure technique, the height of the photoresist must be lowered to form such a fine pattern. However, as the degree of integration of semiconductor devices increases, contact holes having high aspect ratios should be formed while maintaining very small line widths. Since a thick photoresist film is required, the result is that the desired line width cannot be maintained. Therefore, such a photoresist film has a limitation in performing a role of a mask in manufacturing a semiconductor device having a high degree of integration.
이와 같이, 포토레지스트의 마스크 한계를 극복하기 위해 콘택홀 식각시 산화막에 대한 선택비가 높은 금속하드마스크(Metal Hard mask)를 사용하는 방법이 제안되었다.As such, a method of using a metal hard mask having a high selectivity to an oxide layer during contact hole etching has been proposed to overcome the mask limitation of the photoresist.
도 1a 내지 도 1d는 종래기술에 따른 반도체소자의 콘택홀 형성 방법을 도시한 공정 단면도이다.1A to 1D are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to the prior art.
도 1a에 도시된 바와 같이, 정렬키 지역과 콘택 지역이 정의된 반도체 기판(11)의 콘택지역에 콘택홀이 오픈될 하부막(12)을 형성한 후, 하부막을 포함한 반도체 기판의 전면에 층간절연막(13)을 형성한다.As shown in FIG. 1A, after forming a lower layer 12 for opening a contact hole in a contact region of a semiconductor substrate 11 in which an alignment key region and a contact region are defined, an interlayer is formed on the entire surface of the semiconductor substrate including the lower layer. The insulating film 13 is formed.
다음으로, 층간절연막(13)을 선택적으로 식각하여 정렬키지역에 다수의 정렬키(Alignment key, 14)를 형성한 후, 정렬키(14)를 포함한 층간절연막(13) 상에 금속하드마스크(15)를 형성한다.Next, after the interlayer insulating layer 13 is selectively etched to form a plurality of alignment keys 14 in the alignment key region, the metal hard mask 13 may be formed on the interlayer insulating layer 13 including the alignment keys 14. 15).
도 1b에 도시된 바와 같이, 금속하드마스크(15) 상에 포토레지스트를 도포한 후 노광 및 현상으로 패터닝하여 콘택지역을 덮고 정렬키지역을 오픈시키는 키오픈마스크(Key open mask, 16)를 형성한다.As shown in FIG. 1B, a photoresist is applied on the metal hard mask 15 and then patterned by exposure and development to form a key open mask 16 covering the contact area and opening the alignment key area. do.
다음으로, 키오픈마스크(16)를 식각마스크로 하여 노출된 정렬키지역의 금속하드마스크를 제거하는 키오픈 식각 공정을 진행한다.Next, a key open etching process is performed to remove the metal hard mask of the exposed alignment key region by using the key open mask 16 as an etching mask.
도 1c에 도시된 바와 같이, 키오픈마스크(16)를 제거한 후, 전면에 포토레지스트를 도포한 후 노광 및 현상으로 패터닝하여 콘택마스크(17)를 형성한다. 이어서, 콘택마스크(17)를 식각마스크로 금속하드마스크(16)를 콘택마스크 형태로 패터닝한다.As shown in FIG. 1C, after removing the open mask 16, a photoresist is applied to the entire surface, and then patterned by exposure and development to form a contact mask 17. Subsequently, the metal hard mask 16 is patterned into a contact mask form using the contact mask 17 as an etch mask.
도 1d에 도시된 바와 같이, 콘택마스크(17)를 제거한 후, 콘택마스크로 형태로 식각된 금속하드마스크(15)를 식각마스크로 층간절연막(13)을 식각하여 하부막(12)의 표면을 오픈시키는 콘택홀(18)을 형성한다.As shown in FIG. 1D, after removing the contact mask 17, the interlayer insulating layer 13 is etched using the metal hard mask 15 etched into the contact mask as an etch mask to etch the surface of the lower layer 12. A contact hole 18 for opening is formed.
다음으로, 금속하드마스크(15)를 제거한다.Next, the metal hard mask 15 is removed.
상술한 종래기술에서는 종횡비가 큰 콘택홀(18)을 형성하기 위해 콘택마스크 (17) 및 금속하드마스크(15)를 도입하였다.In the above-described prior art, the contact mask 17 and the metal hard mask 15 are introduced to form the contact holes 18 having a large aspect ratio.
그러나, 종래기술에서 도입한 금속하드마스크(15)는 반사도가 매우 크므로 콘택 마스크(17) 노광시 정렬빔이 반사되어 하부막(12)과의 정렬이 불가능해지므로 하부막(12)과의 중첩도(overlay)를 맞출수 없는 단점이 있다. However, since the metal hard mask 15 introduced in the related art has a very large reflectivity, when the contact mask 17 is exposed, the alignment beam is reflected, so that alignment with the lower layer 12 is impossible. There is a drawback in not being able to match the overlay.
따라서, 정렬키의 금속하드마스크를 제거해주는 키오픈 식각 공정이 반드시 필요하게 되어 공정단순화 및 원가측면에서 불리하다. Therefore, a key open etching process for removing the metal hard mask of the alignment key is necessary, which is disadvantageous in terms of process simplicity and cost.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로, 키오픈 식각공정없이도 하부막과의 정렬이 가능한 반도체소자의 콘택홀 형성 방법을 제공하는데 그 목적이 있다. The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for forming a contact hole in a semiconductor device which can be aligned with a lower layer without a key open etching process.
상기 목적을 달성하기 위한 본 발명의 콘택홀 형성 방법은 정렬키지역과 콘택지역이 정의된 반도체 기판의 콘택지역 상부에 하부막을 형성하는 단계, 상기 하부막을 포함한 전면에 층간절연막을 형성하는 단계, 상기 층간절연막을 일부 식각하여 상기 정렬키지역에 정렬키를 형성하는 단계, 상기 정렬키가 형성된 층간절연막 상에 질화막과 산화막을 차례로 형성하는 단계, 상기 산화막을 선택적으로 식각하여 상기 정렬키지역을 모두 덮는 제1부분과 콘택홀 예정지역을 덮고 나머지 상기 콘택지역을 오픈시키는 제2부분으로 이루어진 산화막패턴을 형성하는 단계, 상기 산화막패턴의 제2부분에 의해 오픈된 지역을 채우는 금속하드마스크패턴을 형성하는 단계, 상기 금속하드마스크패턴을 식각마스크로 상기 산화막패턴을 모두 제거하는 단계, 상기 금속하드마스크패턴을 식각마스크로 질화막과 층간절연막을 식각하여 상기 하부막의 표면을 오픈시키는 콘택홀을 형성하는 단계, 및 상기 금속하드마스크패턴을 제거하는 단계를 포함하는 것을 특징으로 하고, 상기 산화막패턴을 형성하는 단계는 상기 산화막 상에 상기 정렬키지역을 모두 덮는 제1부분과 콘택홀 예정지역을 덮고 나머지 상기 콘택지역을 오픈시키는 제2부분으로 이루어진 콘택마스크를 형성하는 단계, 상기 콘택마스크를 식각마스크로 산화막을 식각하는 단계, 및 상기 콘택마스크를 제거하는 단계를 포함하는 것을 특징으로 한다. According to an aspect of the present invention, there is provided a method of forming a contact hole, forming a lower layer on an upper portion of a contact region of a semiconductor substrate in which an alignment key region and a contact region are defined, and forming an interlayer insulating layer on the entire surface including the lower layer. Forming an alignment key in the alignment key region by partially etching the interlayer dielectric layer, sequentially forming a nitride film and an oxide layer on the interlayer dielectric layer on which the alignment key is formed, and selectively etching the oxide layer to cover all of the alignment key regions Forming an oxide layer pattern including a first portion and a second portion covering the contact hole region and opening the remaining region, and forming a metal hard mask pattern filling the region opened by the second portion of the oxide layer pattern; Removing all of the oxide layer pattern using the metal hard mask pattern as an etch mask; Forming a contact hole to open the surface of the lower layer by etching the nitride layer and the interlayer insulating layer using an inner hard mask pattern as an etch mask, and removing the metal hard mask pattern. The forming of the contact mask may include forming a contact mask on the oxide layer, the contact mask including a first part covering all of the alignment key areas and a second part covering a contact hole planned area and opening the remaining contact areas, and etching the contact mask. Etching the oxide film with a mask, and removing the contact mask.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2h는 본 발명의 실시예에 따른 반도체소자의 콘택홀 형성 방법을 도시한 공정 단면도이다.2A to 2H are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.
도 2a에 도시된 바와 같이, 정렬키 지역과 콘택 지역이 정의된 반도체 기판(21)의 콘택지역에 콘택홀이 오픈될 하부막(22)을 형성한 후, 하부막을 포함한 반도체 기판(21)의 전면에 층간절연막(23)을 형성한다.As shown in FIG. 2A, after forming the lower layer 22 to open the contact hole in the contact region of the semiconductor substrate 21 in which the alignment key region and the contact region are defined, the semiconductor substrate 21 including the lower layer is formed. An interlayer insulating film 23 is formed on the entire surface.
다음으로, 층간절연막(23)을 선택적으로 식각하여 정렬키지역에 정렬키(Alignment key, 24)를 형성한 후, 정렬키(24)가 형성된 층간절연막(23) 상에 질화막(25)을 증착한다. 이때, 질화막(25)은 50Å∼100Å 두께로 증착한다.Next, by selectively etching the interlayer insulating film 23 to form an alignment key 24 in the alignment key region, the nitride film 25 is deposited on the interlayer insulating film 23 on which the alignment key 24 is formed. do. At this time, the nitride film 25 is deposited to a thickness of 50 kPa to 100 kPa.
다음으로, 질화막(25) 상에 산화막(26)을 증착한다.Next, an oxide film 26 is deposited on the nitride film 25.
도 2b에 도시된 바와 같이, 산화막(26) 상에 포토레지스트를 도포한 후 노광 및 현상으로 패터닝하여 콘택마스크(27)를 형성한다. 여기서, 콘택마스크(27)는 정렬키지역을 모두 덮고, 콘택지역에서는 콘택홀이 형성될 부분을 덮는 형태로 형성된다. 즉, 콘택지역에서 콘택홀이 형성될 부분은 덮고 콘택홀이 형성되지 않는 부분(27a)은 오픈시키는 형태이다. 여기서, 콘택마스크(27)의 콘택홀이 형성될 부분을 덮는 폭은 후속 콘택홀의 폭과 동일하다.As shown in FIG. 2B, a photoresist is applied on the oxide film 26 and then patterned by exposure and development to form a contact mask 27. Here, the contact mask 27 covers all of the alignment key region, and the contact mask 27 is formed to cover a portion where the contact hole is to be formed. That is, in the contact region, the portion where the contact hole is to be formed is covered, and the portion 27a where the contact hole is not formed is opened. Here, the width covering the portion where the contact hole of the contact mask 27 is to be formed is equal to the width of the subsequent contact hole.
한편, 콘택마스크(27)를 형성하기 위한 포토리소그래피 공정시 노광원으로는 DUV, ArF, KrF, EUV, E빔, X선 및 이온빔으로 이루어진 그룹으로부터 선택된 하나를 이용한다.In the photolithography process for forming the contact mask 27, one selected from the group consisting of DUV, ArF, KrF, EUV, E-beam, X-ray and ion beam is used.
도 2c에 도시된 바와 같이, 콘택마스크(27)를 식각마스크로 산화막(26)을 식각한 후, 콘택마스크(27)를 제거한다.As illustrated in FIG. 2C, after the oxide layer 26 is etched using the contact mask 27 as an etch mask, the contact mask 27 is removed.
상기한 산화막(26) 식각후 정렬키지역 상부에는 콘택마스크(27)에 의해 보호되므로 최초 증착된 산화막(26a)의 형태를 그대로 유지하고, 콘택지역에서는 콘택마스크(27)에 의해 일부가 식각되어 콘택홀이 형성될 부분을 덮는 형태의 산화막(26b)이 잔류한다. 여기서, 산화막(26b)의 폭은 콘택홀의 폭과 동일하다.Since the oxide film 26 is protected by the contact mask 27 on the alignment key region after etching, the shape of the first deposited oxide layer 26a is maintained as it is, and a portion of the contact region is etched by the contact mask 27 in the contact region. The oxide film 26b covering the portion where the contact hole is to be formed remains. Here, the width of the oxide film 26b is equal to the width of the contact hole.
도 2d에 도시된 바와 같이, 식각된 산화막(26a, 26b)을 포함한 전면에 금속하드마스크(28)를 증착한다. 여기서, 금속하드마스크(28)는 텅스텐 또는 알루미늄을 이용하며, 콘택지역에 잔류하는 산화막(26b) 사이를 충분히 채울때까지 증착한다.As shown in FIG. 2D, a metal hard mask 28 is deposited on the entire surface including the etched oxide layers 26a and 26b. Here, the metal hard mask 28 is made of tungsten or aluminum, and is deposited until the gap between the oxide film 26b remaining in the contact region is sufficiently filled.
도 2e에 도시된 바와 같이, 금속하드마스크(28)를 에치백한다. 이때, 금속하드마스크(28)의 에치백 공정은 정렬키지역의 금속하드마스크(28)를 모두 제거할때까지 진행하며, 이로써 콘택지역의 산화막(26b) 사이에 매립되는 형태의 금속하드마스크(28a)만 잔류한다.As shown in FIG. 2E, the metal hard mask 28 is etched back. At this time, the etch back process of the metal hard mask 28 proceeds until all of the metal hard mask 28 of the alignment key region is removed, thereby filling the metal hard mask having a form of being buried between the oxide layer 26b of the contact region. Only 28a) remains.
도 2f에 도시된 바와 같이, 산화막(26a, 26b)을 습식식각공정을 이용하여 제거한다. 이로써, 금속하드마스크(28a)만 콘택지역 상부에 잔류한다.As shown in FIG. 2F, the oxide films 26a and 26b are removed using a wet etching process. As a result, only the metal hard mask 28a remains on the contact region.
도 2g에 도시된 바와 같이, 잔류하는 금속하드마스크(28a)를 식각마스크로 이용하여 질화막(25)과 층간절연막(23)을 식각하므로써 하부막(22)의 표면을 오픈시키는 콘택홀(29)을 형성한다.As shown in FIG. 2G, the contact hole 29 which opens the surface of the lower layer 22 by etching the nitride layer 25 and the interlayer insulating layer 23 using the remaining metal hard mask 28a as an etching mask. To form.
상기 콘택홀(29) 형성을 위한 식각공정은 건식식각공정을 이용하며, 이때, 질화막(25)을 먼저 식각하고나서 층간절연막(23)을 식각한다. 따라서, 정렬키지역에 형성된 질화막(25)이 모두 제거된다.The etching process for forming the contact hole 29 uses a dry etching process, in which the nitride film 25 is first etched and then the interlayer insulating film 23 is etched. Therefore, all of the nitride films 25 formed in the alignment key region are removed.
도 2h에 도시된 바와 같이, 금속하드마스크(28a)를 에치백 공정으로 제거한다. 이때, 금속하드마스크 아래에 잔류하는 질화막(25)도 금속하드마스크(28a)의 에치백 공정시 동시에 제거된다.As shown in FIG. 2H, the metal hard mask 28a is removed by an etch back process. At this time, the nitride film 25 remaining under the metal hard mask is also simultaneously removed during the etch back process of the metal hard mask 28a.
상술한 바에 따르면 본 발명은 산화막 형성, 금속하드마스크 형성, 산화막 제거로 이루어지는 일련의 상감법(Damascene)을 이용하므로써 키오픈식각과 같은 추가의 공정없이 금속하드마스크 형성과 정렬키지역의 금속하드마스크 제거를 같이 할 수 있다.As described above, the present invention utilizes a series of damascenes consisting of oxide film formation, metal hard mask formation, and oxide film removal, thereby eliminating metal hard mask formation and metal hard masks in alignment key regions without additional processes such as key open etching. You can do this together.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은 키오픈 식각공정없이도 정렬키지역의 금속하드마스크를 제거할 수 있어 공정단순화 및 원가절감을 구현할 수 있는 효과가 있다.The present invention described above can remove the metal hard mask of the alignment key region without the key open etching process, thereby reducing the process simplicity and cost.
또한, 상감법을 이용하므로써 금속하드마스크 구현과 정렬키지역의 금속하드마스크의 제거를 동시에 할 수 있어 추가 공정이 필요없는 효과가 있다. In addition, by using the inlay method, it is possible to simultaneously implement the metal hard mask and to remove the metal hard mask in the alignment key region, thereby eliminating the need for an additional process.
도 1a 내지 도 1d는 종래기술에 따른 반도체소자의 콘택홀 형성 방법을 도시한 공정 단면도,1A to 1D are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to the prior art;
도 2a 내지 도 2h는 본 발명의 실시예에 따른 반도체소자의 콘택홀 형성 방법을 도시한 공정 단면도.2A to 2H are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 하부막21 semiconductor substrate 22 lower film
23 : 층간절연막 24 : 정렬키23: interlayer insulating film 24: alignment key
25 : 질화막 26 : 산화막25 nitride film 26 oxide film
27 : 콘택마스크 28 : 금속하드마스크27: contact mask 28: metal hard mask
29 : 콘택홀 29 contact hole
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| KR1020040029322A KR20050104088A (en) | 2004-04-28 | 2004-04-28 | Method for forming contact hole in semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9123657B2 (en) | 2013-09-16 | 2015-09-01 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor devices |
| US10074707B2 (en) | 2015-11-03 | 2018-09-11 | Samsung Display Co. Ltd. | Thin film transistor array for organic light-emitting display |
| CN112119512A (en) * | 2018-05-11 | 2020-12-22 | 株式会社村田制作所 | Porous region structure and method for producing same |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9123657B2 (en) | 2013-09-16 | 2015-09-01 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor devices |
| US10074707B2 (en) | 2015-11-03 | 2018-09-11 | Samsung Display Co. Ltd. | Thin film transistor array for organic light-emitting display |
| CN112119512A (en) * | 2018-05-11 | 2020-12-22 | 株式会社村田制作所 | Porous region structure and method for producing same |
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