KR20050098749A - Methods of fabricating a semiconductor integrated circuit with thin film transistors using a damascene technique and a selective epitaxial growth technique and semiconductor integrated circuits fabricated thereby - Google Patents

Abstract

Methods of manufacturing semiconductor integrated circuits with thin film transistors using damascene techniques and selective epitaxial growth techniques, and semiconductor integrated circuits produced thereby are provided. The methods include forming a single crystal semiconductor plug penetrating the interlayer insulating layer and forming a molding layer pattern exposing the single crystal semiconductor plug on the interlayer insulating layer. Subsequently, a single crystal semiconductor epitaxial pattern is grown on the interlayer insulating layer using the single crystal semiconductor plug as a seed layer. The single crystal semiconductor epitaxial pattern is planarized to form a single crystal semiconductor body having a uniform thickness in the molding layer pattern. As a result, sidewalls of the single crystal semiconductor body are surrounded by the molding layer pattern, and the single crystal semiconductor body has an excellent single crystalline structure.

Description

Methods of fabricating a semiconductor integrated circuit with thin film transistors using a damascene technique using methods for fabricating semiconductor integrated circuits with thin film transistors using damascene technology and selective epitaxial growth techniques and a selective epitaxial growth technique and semiconductor integrated circuits fabricated thereby}

The present invention relates to methods of fabricating semiconductor integrated circuits and semiconductor integrated circuits produced thereby, in particular methods of fabricating semiconductor integrated circuits with thin film transistors using damascene and selective epitaxial growth techniques; A semiconductor integrated circuit manufactured thereby.

Semiconductor integrated circuits have widely adopted individual devices such as MOS transistors as switching devices. Most of the MOS transistors are formed directly on the semiconductor substrate. That is, the MOS transistors are formed to have channel regions and source / drain regions in the semiconductor substrate. In this case, the MOS transistors may be referred to as bulk MOS transistors.

In the case where the semiconductor integrated circuits employ the bulk MOS transistors, there is a limit to improving the integration degree of the semiconductor integrated circuits. In particular, if the semiconductor integrated circuits are complementary metal-oxide-semiconductor circuits (CMOS circuits) consisting of N-channel bulk MOS transistors and P-channel bulk MOS transistors, improving the integration of the semiconductor integrated circuits. Is even more difficult. This is because of the latch-up phenomenon occurring in the CMOS circuit.

Recently, thin film transistors stacked on the semiconductor substrate have been widely adopted to solve the latchup phenomenon as well as the integration degree of the semiconductor integrated circuits. For example, the thin film transistors are used in unit cells of an SRAM. The SRAM has advantages of low power consumption and fast operation speed compared to DRAM. Therefore, the SRAM is widely used as a cache memory device or a portable appliance of a computer.

The SRAM cell is classified into two types. One is a high load resistor SRAM cell that adopts high resistance as a load device, and the other is a CMOS SRAM cell which employs a PMOS transistor as a load device. The CMOS SRAM cell is further classified into two types. One is a thin film transistor SRAM cell employing the thin film transistor (TFT) as a load element, and the other is a bulk CMOS SRAM cell employing the bulk MOS transistor as a load element. (bulk CMOS SRAM cell).

The bulk CMOS SRAM cell exhibits high cell stability compared to the thin film transistor SRAM cell and the high resistance SRAM cell. In other words, the bulk CMOS SRAM cell exhibits an excellent low voltage characteristic and a low stand-by current. This is because the thin film transistor is generally fabricated using a polysilicon layer as a body layer, while all the transistors constituting the bulk CMOS SRAM cell are formed on a single crystal silicon substrate. However, as described above, the bulk CMOS SRAM cell exhibits low integration density and weak latch-up immunity compared to the thin film transistor SRAM cell. Therefore, in order to implement a highly integrated SRAM having high reliability, it is required to continuously improve the characteristics of the load transistor adopted in the thin film transistor SRAM cell.

Meanwhile, semiconductor devices having thin film transistors stacked on a semiconductor substrate are described in US Patent No. 6,022,766 entitled "Semiconductor structure incorporating thin film transistors and methods for its manufacture." It has been disclosed by Chen et al. According to Chen et al., A conventional bulk MOS transistor is formed on a single crystal silicon substrate, and a thin film transistor is stacked on top of the bulk MOS transistor. One of the source / drain regions of the bulk MOS transistor is electrically connected to one of the source / drain regions of the thin film transistor through a metal plug such as a tungsten plug. Thus, when the bulk MOS transistor and the thin film transistor are NMOS transistors and PMOS transistors, respectively, the bulk MOS transistor has an ohmic contact with the thin film transistor through the metal plug.

In addition, the body layer of the thin film transistor is formed by forming an amorphous silicon layer on the entire surface of the semiconductor substrate having the metal plug and crystallizing the amorphous silicon layer through a heat treatment process. In this case, the body layer corresponds to a polysilicon layer with large grains. That is, it is difficult to transform the body layer into a complete single crystal silicon layer. As a result, it is difficult to form the thin film transistor to have electrical characteristics corresponding to that of the bulk MOS transistor. Thus, there is a continuous need for methods for improving the characteristics of thin film transistors stacked on top of semiconductor substrates.

An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit capable of forming a uniform single crystal semiconductor body on a semiconductor substrate.

Another object of the present invention is to provide methods for manufacturing a thin film transistor SRAM cell capable of improving reliability and integration.

Another object of the present invention is to provide semiconductor integrated circuits suitable for forming a uniform single crystal semiconductor body.

Another object of the present invention is to provide thin film transistor SRAM cells suitable for improving reliability and integration.

According to one aspect of the present invention, there are provided methods of fabricating a semiconductor integrated circuit using damascene technology and selective epitaxial growth technology. Methods of manufacturing the semiconductor integrated circuit include forming an interlayer insulating layer on a single crystal semiconductor substrate, and forming a single crystal semiconductor plug penetrating the interlayer insulating layer. A molding layer pattern is formed on a substrate having the single crystal semiconductor plug. The molding layer pattern is formed to have an opening exposing the single crystal semiconductor plug. A single crystal semiconductor epitaxial pattern is formed on the exposed single crystal semiconductor plug. The single crystal semiconductor epitaxial pattern is formed using a selective epitaxial growth technique employing the exposed single crystal semiconductor plug as a seed layer. A single crystal semiconductor body having a portion of the single crystal semiconductor epitaxial pattern is formed in the opening.

In some embodiments of the present invention, forming the single crystal semiconductor plug is optional to pattern the interlayer insulating layer to form a contact hole exposing the single crystal semiconductor substrate and to employ the exposed single crystal semiconductor substrate as a seed layer. And growing a single crystal semiconductor epitaxial layer filling the contact hole using an epitaxial growth technique. The single crystal epitaxial layer may be further planarized.

In other embodiments, the forming of the molding layer pattern may include forming a molding layer on the substrate having the single crystal semiconductor plug and patterning the molding layer to expose the single crystal semiconductor plug. The molding layer may be formed of a silicon oxide layer.

In still other embodiments, forming the molding layer pattern may include sequentially forming a lower molding layer and an upper molding layer on the substrate having the single crystal semiconductor plug, and patterning the upper molding layer and the lower molding layer to form the single crystal semiconductor. And exposing the plug. The lower molding layer may be formed of an insulating layer having an etch selectivity with respect to the interlayer insulating layer, and the upper molding layer may be formed of an insulating layer having an etch selectivity with respect to the lower molding layer. For example, the lower molding layer may be formed of a silicon nitride layer, and the upper molding layer may be formed of a silicon oxide layer.

In still other embodiments, the forming of the molding layer pattern may include forming a sacrificial layer pattern covering the single crystal semiconductor plug on the substrate having the single crystal semiconductor plug, and molding covering the sacrificial layer pattern and the interlayer insulating layer. The method may include forming a layer, planarizing the molding layer to expose an upper surface of the sacrificial layer pattern, and selectively removing the sacrificial layer pattern to expose the single crystal semiconductor plug. The sacrificial layer pattern may be formed of a material layer having an etch selectivity with respect to the interlayer insulating layer and the molding layer. For example, the sacrificial layer pattern may be formed of a silicon nitride layer, and the molding layer may be formed of a silicon oxide layer.

In other embodiments, the single crystal semiconductor body may be formed by planarizing the single crystal semiconductor epitaxial pattern until the upper surface of the molding layer pattern is exposed.

In still other embodiments, the forming of the single crystal semiconductor body may include forming an amorphous semiconductor layer or a polycrystalline semiconductor layer on a substrate having the single crystal semiconductor epitaxial pattern, and solidifying the amorphous semiconductor layer or the polycrystalline semiconductor layer. Crystallization using an epitaxial technique, and planarizing the crystallized semiconductor layer and the single crystal semiconductor epitaxial pattern until the top surface of the molding layer pattern is exposed.

In still other embodiments, the forming of the single crystal semiconductor body may include forming an amorphous semiconductor layer or a polycrystalline semiconductor layer on a substrate having the single crystal semiconductor epitaxial pattern, and when the top surface of the molding layer pattern is exposed. Continuously planarizing the single crystal semiconductor epitaxial pattern together with the amorphous semiconductor layer or the polycrystalline semiconductor layer, and crystallizing the planarized amorphous semiconductor layer or the planarized polycrystalline semiconductor layer using a solid state epitaxial process. It may include.

In other embodiments, a thin film transistor may be further formed in the single crystal semiconductor body. The forming of the thin film transistor may include forming an insulated gate electrode crossing the upper portion of the single crystal semiconductor body, and implanting impurity ions into the single crystal semiconductor body by using the gate electrode as an ion implantation mask to form source / drain regions. It may include forming.

In another embodiment, an active region may be defined by forming an isolation layer in a predetermined region of the single crystal semiconductor substrate before forming the interlayer insulating layer, and a bulk MOS transistor may be formed in the active region. The bulk MOS transistor may be formed to have a source region and a drain region respectively positioned at both sides of the channel region below the gate electrode in addition to the gate electrode crossing the upper portion of the active region. In this case, the single crystal semiconductor plug may be formed to contact at least one of the source / drain regions of the bulk MOS transistor.

According to another aspect of the present invention, methods of fabricating thin film transistor SRAM cells using damascene technology and selective epitaxial growth technology are provided. The SRAM cell is composed of first and second half cells. Methods of manufacturing any one of the first and second half cells include forming an isolation layer in a predetermined region of a single crystal semiconductor substrate to define an active region, and forming a driving transistor in the active region. The driving transistor is formed to have a source region and a drain region respectively positioned at both sides of the channel region below the driving gate electrode as well as a driving gate electrode crossing the upper portion of the active region. An interlayer insulating layer is formed on a substrate having the drive transistor. A single crystal semiconductor plug is formed to penetrate the interlayer insulating layer. The single crystal semiconductor plug is formed to contact the drain region of the driving transistor. A molding layer pattern is formed on a substrate having the single crystal semiconductor plug. The molding layer pattern is formed to have an opening exposing the single crystal semiconductor plug. A selective epitaxial growth technique employing the exposed single crystal semiconductor plug as a seed layer is used to form a single crystal semiconductor epitaxial pattern covering the exposed single crystal semiconductor plug. A single crystal semiconductor body having a portion of the single crystal semiconductor epitaxial pattern is formed in the opening.

According to another aspect of the invention, integrated circuits having a uniform single crystal semiconductor body are provided. The integrated circuits include an interlayer insulating layer stacked on a single crystal semiconductor substrate and a single crystal semiconductor plug penetrating the interlayer insulating layer. A single crystal semiconductor body is provided on the interlayer insulating layer. The single crystal semiconductor body extends to contact the single crystal semiconductor plug. Sidewalls of the single crystal semiconductor body are surrounded by a molding layer pattern. The molding layer pattern has a thickness substantially the same as that of the single crystal semiconductor body.

In some embodiments of the present invention, the single crystal semiconductor plug may be an epitaxial layer formed using a selective epitaxial growth technique employing the single crystal semiconductor substrate as a seed layer.

In other embodiments, the single crystal semiconductor body may be a single crystal epitaxial pattern formed using a selective epitaxial growth technique employing the single crystal semiconductor plug as a seed layer.

In still other embodiments, the single crystal semiconductor body may comprise a single crystal epitaxial pattern formed using a selective epitaxial growth technique employing the single crystal semiconductor plug as a seed layer and the single crystal epitaxial pattern as a seed layer. Semiconductor layers crystallized using solid state epitaxial techniques. The crystallized semiconductor layer may be a single crystal semiconductor layer formed by crystallizing an amorphous semiconductor layer or a polycrystalline semiconductor layer.

In other embodiments, the molding layer pattern may be a single insulating layer or a double insulating layer. The single insulating layer may be a silicon oxide layer. The double insulation layer may include a lower molding layer pattern and an upper molding layer pattern sequentially stacked. In this case, the lower molding layer pattern may be an insulating layer having an etch selectivity with respect to the interlayer insulating layer and the upper molding layer pattern. For example, the lower molding layer pattern and the upper molding layer pattern may be a silicon nitride layer and a silicon oxide layer, respectively. When the molding layer pattern is the single insulating layer, the single crystal semiconductor body may have a negative sloped sidewall profile or a positive sloped sidewall profile. The single crystal semiconductor body having the negatively sloped sidewall profile has its upper width greater than its lower width, and the single crystal semiconductor body having the positive sidewall profile has its upper width less than its lower width. If the molding layer pattern is the double insulating layer, the single crystal semiconductor body may have a negative sloped sidewall profile such that the top width of the single crystal semiconductor body is greater than its bottom width.

In still other embodiments, a thin film transistor may be provided in the single crystal semiconductor body. The thin film transistor may include an insulated gate electrode crossing an upper portion of a channel region between the source region and the drain region as well as a source region and a drain region formed in the single crystal semiconductor body.

In another embodiment, an isolation layer may be provided in a predetermined region of the single crystal semiconductor substrate to define an active region, and a bulk MOS transistor may be provided in the active region. The bulk MOS transistor may include an insulated gate electrode crossing an upper portion of a channel region between the source region and the drain region, as well as a source region and a drain region formed in the active region. In this case, the single crystal semiconductor plug may be electrically connected to any one of the source / drain regions of the bulk MOS transistor.

According to another aspect of the invention, thin film transistor SRAM cells are provided. Each of the thin film transistor SRAM cells includes first and second half cells. Each of the first and second half cells includes a device isolation layer formed in a predetermined region of a single crystal semiconductor substrate to define an active region, and a driving transistor formed in the active region. The driving transistor has a source region and a drain region formed in the active region, and a driving gate electrode that crosses an upper portion of a channel region between the source / drain regions. An interlayer insulating layer is provided on a substrate having the drive transistor. The drain region of the driving transistor contacts a single crystal semiconductor plug penetrating the interlayer insulating layer. A single crystal semiconductor body is provided on the interlayer insulating layer. The single crystal semiconductor body extends to cover the single crystal semiconductor plug. Sidewalls of the single crystal semiconductor body are surrounded by a molding layer pattern. The molding layer pattern has a thickness substantially the same as that of the single crystal semiconductor body.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

1 is an equivalent circuit diagram of a CMOS SRAM cell, such as a thin film transistor SRAM cell or a bulk CMOS SRAM cell.

Referring to FIG. 1, the CMOS SRAM cell includes a pair of driver transistors TD1 and TD2, a pair of transfer transistors TT1 and TT2, and a pair of driver transistors TD1 and TD2. A pair of load transistors (TL1, TL2). The pair of driving transistors TD1 and TD2 and the pair of transfer transistors TT1 and TT2 are all NMOS transistors, while the pair of load transistors TL1 and TL2 are all PMOS transistors. .

The first driving transistor TD1 and the first transfer transistor TT1 are connected in series with each other. A source region of the first driving transistor TD1 is electrically connected to a ground line Vss, and a drain region of the first transfer transistor TT1 is electrically connected to a first bit line BL1. Similarly, the second driving transistor TD2 and the second transfer transistor TT2 are connected in series with each other. The source region of the second driving transistor TD2 is electrically connected to the ground line Vss, and the drain region of the second transfer transistor TT2 is electrically connected to the second bit line BL2.

The source region and the drain region of the first load transistor TL1 are electrically connected to a power supply line Vcc and a drain region of the first driving transistor TD1, respectively. Similarly, the source region and the drain region of the second load transistor TL2 are electrically connected to the drain region of the power line Vcc and the second driving transistor TD2, respectively. A drain region of the first load transistor TL1, a drain region of the first driving transistor TD1, and a source region of the first transfer transistor TT1 correspond to the first node N1. The drain region of the second load transistor TL2, the drain region of the second driving transistor TD2, and the source region of the second transfer transistor TT2 correspond to the second node N2. The gate electrode of the first driving transistor TD1 and the gate electrode of the first load transistor TL1 are electrically connected to the second node N2, and the gate electrode of the second driving transistor TD2 and the gate electrode of the second driving transistor TD2. The gate electrode of the second load transistor TL2 is electrically connected to the second node N1. In addition, the gate electrodes of the first and second transfer transistors TT1 and TT2 are electrically connected to the word line WL.

The CMOS SRAM cell described above exhibits a small stand-by current and a large noise margin as compared to the high resistance SRAM cell. Therefore, the CMOS SRAM cell has been widely adopted for high performance SRAMs requiring low power voltage. In particular, high performance P-channel thin films having improved electrical properties corresponding to P-channel bulk transistors in which the thin film transistor SRAM cell is used as load transistors of the bulk CMOS SRAM cell. If the film transistors are provided, the thin film transistor SRAM cell has advantages in terms of integration density and latch-up immunity, etc., compared to the bulk CMOS SRAM cell.

In order to implement the high performance P-channel thin film transistor, the thin film transistor should be formed in a body pattern made of a single crystal semiconductor layer. In addition, an ohmic contact should be formed at the first and second nodes N1 and N2 shown in FIG. 1.

In FIG. 1, the first driving transistor TD1, the first transfer transistor TT1, and the first load transistor TL1 constitute a first half cell H1, and the second driving transistor TD2. The second transfer transistor TT2 and the second load transistor TL2 constitute a second half cell H2.

2 is a plan view illustrating a pair of thin film transistor SRAM cells according to embodiments of the present invention. The pair of thin film transistor SRAM cells shown in FIG. 2 are symmetrical with respect to the x axis. The pair of thin film transistor SRAM cells are repeatedly arranged to be symmetrical about the x-axis and the y-axis to form a cell array region. Each of the pair of thin film transistor SRAM cells shown in FIG. 2 is a layout diagram of a CMOS SRAM cell corresponding to the equivalent circuit of FIG. 1. 3A to 8A are cross-sectional views taken along line II ′ of FIG. 2 to describe thin film transistor SRAM cells and methods of fabricating the same, and FIGS. 3B to 8B illustrate the present invention. 2 are cross-sectional views taken along line II-II ′ of FIG. 2 to describe thin film transistor SRAM cells and a method of manufacturing the same. That is, FIGS. 3A to 8A are cross-sectional views crossing the first half cell region H1 and the second half cell region H2 adjacent to each other, and FIGS. 3B to 8B are pairs of second half cell regions adjacent to each other. These are cross sectional views across (H2).

1, 2, 3A, and 3B, an isolation layer 3 is formed in a predetermined region of a single crystal semiconductor substrate 1 such as a single crystal silicon substrate to form the first and second half cell regions ( The first and second active regions 3a and 3b are defined in H1 and H2, respectively. Each of the first and second active regions 3a and 3b may include a transfer transistor active region 3t and a driving transistor active region 3d. A gate insulating layer 5 is formed on the active regions 3a and 3b and a gate conductive layer is formed on a substrate having the gate insulating layer 5. The gate conductive layer is patterned to form a first driving gate electrode 7d 'and a first transfer gate electrode 7t' that cross the upper portion of the first active region 3a, and the second active region 3b. A second driving gate electrode 7d ″ and a second transfer gate electrode 7t ″ that cross the upper portion are formed.

The first transfer gate electrode 7t 'and the first driving gate electrode 7d' are respectively upper portions of the transfer transistor active region 3t and the driving transistor active region 3d of the first active region 3a. And the second transfer gate electrode 7t "and the second driving gate electrode 7d" are respectively the transfer transistor active region 3t and the driving transistor of the second active region 3b. It is formed to cross the upper portion of the active region (3d).

Impurity ions of a first conductivity type are implanted into the active regions 3a and 3b using the transfer gate electrodes 7t 'and 7t "and the driving gate electrodes 7d' and 7d" as ion implantation masks. Thereby forming the LED areas 9. The impurity ions of the first conductivity type may be N-type impurity ions. Gate spacers 11 are formed on sidewalls of the transfer gate electrodes 7t 'and 7t "and the driving gate electrodes 7d' and 7d". Impurity ions of a first conductivity type are implanted into the active regions 3a and 3b using the gate electrodes 7t ', 7t ", 7d', and 7d" and the gate spacers 11 as ion implantation masks. do. As a result, a first node impurity region (not shown) is formed in the first active region 3a between the first driving gate electrode 7d 'and the first transfer gate electrode 7t'. A first bit line impurity region (not shown) is formed in the first active region 3a adjacent to the first transfer gate electrode 7t 'and opposite to the first node impurity region, and the first driving gate is formed. A first ground impurity region (not shown) is formed in the first active region 3a adjacent to the electrode 7d 'and opposite the first node impurity region. In addition, a second node impurity region 13n ″ is formed in the second active region 3b between the second driving gate electrode 7d ″ and the second transfer gate electrode 7t ″, and the second transfer is performed. A second bit line impurity region 13d ″ is formed in the second active region 3b adjacent to the gate electrode 7t ″ and opposite to the second node impurity region 13n ″, and the second driving is performed. A second ground impurity region 13s "is formed in the second active region 3b adjacent to the gate electrode 7d" and opposite the second node impurity region 13n ". In this case, The LED regions 9 remain under the gate spacers 11. The impurity regions 13s ″, 13n ″, and 13d ″ are formed to have a higher concentration than the LED regions 9. do. That is, LED source / drain regions are formed in the active regions 3a and 3b. As a result, a first transfer transistor TT1 and a first driving transistor TD1 connected in series to the first active region 3a are formed, and a second transfer transistor TT2 connected in series to the second active region 3b. ) And a second driving transistor TD2 are formed.

An interlayer insulating layer 17 is formed on the entire surface of the semiconductor substrate having the impurity regions 13s ″, 13n ″, and 13d ″. The interlayer insulating layer 17 may be formed of a silicon oxide layer. The conformal etch stop layer 15 may be formed before forming the insulating layer 17. The etch stop layer 15 is formed of an insulating layer having an etch selectivity with respect to the interlayer insulating layer 17. For example, the etch stop layer 15 may be formed of a silicon nitride layer.

1, 2, 4A, and 4B, the interlayer insulating layer 17 and the etch stop layer 15 are patterned to expose the first and second node impurity regions, respectively. Two node contact holes 19a and 19b are formed. First node semiconductor plugs (not shown) and second node semiconductor plugs 21b are formed in the first and second node contact holes 19a and 19b, respectively. The node semiconductor plugs may be formed using a selective epitaxial growth (SEG) technique that employs the exposed node impurity regions 13n ″ as the seed layer. In this case, the node semiconductors Plugs are grown to have the same crystal state as the exposed node impurity regions, for example, when the semiconductor substrate 1 is a single crystal silicon substrate and the selective epitaxial growth technique is implemented using a silicon source gas. The node semiconductor plugs may be formed to have a single crystal silicon structure, that is, the node semiconductor plugs may be single crystal semiconductor plugs, and the node semiconductor plugs may be doped to have a P-type or N-type conductivity. Alternatively, the node semiconductor plugs may be intrinsic semiconductors. In the case where the interlayer is excessively high so that the top than cotton in the insulating layer 17 growth, the node semiconductor plugs is flattened may have the same height as the interlayer insulating layer 17.

Subsequently, openings are formed on the substrate having the node semiconductor plugs, and the patterning layer is exposed to expose the node semiconductor plugs 21b and a portion of the interlayer insulating layer 17 adjacent thereto ( A molding layer pattern 22c having 22t) is formed. The molding layer may be formed of a single insulating layer such as a silicon oxide layer. When the interlayer insulating layer 17 is formed of the same material layer as the molding layer, the interlayer insulating layer 17 may be additionally etched while the openings 22t are formed. As a result, the depth of the openings 22t may be larger than the thickness of the molding layer, that is, the single insulating layer, and may be nonuniform throughout the semiconductor substrate 1.

In other embodiments of the present invention, in order to prevent the openings 22t from being formed to have a non-uniform depth, the molding layer may be formed as a double insulating layer. In other words, the molding layer may be formed by sequentially stacking a lower molding layer having an etch selectivity with respect to the interlayer insulating layer 17 and an upper molding layer having an etch selectivity with respect to the lower molding layer. In this case, the molding layer pattern 22c is formed to have the lower molding layer pattern 22a and the upper molding layer pattern 22b sequentially stacked. The lower molding layer may be formed of a silicon nitride layer, and the upper molding layer may be formed of a silicon oxide layer. The lower molding layer serves as an etch stop layer during the patterning of the upper molding layer, and the interlayer insulating layer 17 serves as an etch stop layer during the patterning of the lower molding layer. As a result, the openings 22t may be uniformly formed to have the same depth as the thickness of the molding layer pattern 22c.

On the other hand, when the molding layer is formed of the single insulating layer or the double insulating layer, the sidewalls 22s of the openings 22t have a general characteristic of an etching process for patterning the molding layer. Due to the positive sloped profile. Specifically, a conventional etching process is performed using a photoresist pattern as an etching mask. In this case, a polymer may be produced during the etching of the molding layer, and the polymer may be adsorbed on the sidewalls of the etched regions in the molding layer. The polymer may serve as an etch mask during the etching process. Accordingly, when the etching process is completed, lower widths of the openings 22t may be smaller than their upper widths. As a result, the sidewalls 22s of the openings 22t may exhibit a positively inclined profile as described above.

1, 2, 5A, and 5B, single crystal semiconductor epitaxial patterns 23e ′ may be formed using a selective epitaxial growth technique employing the node semiconductor plugs 21b as a seed layer. Form. In this case, the single crystal semiconductor epitaxial patterns 23e 'may be grown upwardly and laterally. When the node semiconductor plugs 21b are single crystal silicon plugs, the single crystal semiconductor epitaxial patterns 23e 'may be grown using a silicon source gas. That is, the single crystal semiconductor epitaxial patterns 23e ′ may be single crystal silicon patterns.

While the single crystal semiconductor epitaxial patterns 23e 'are growing, a first lateral growth rate a first at an interface between the interlayer insulating layer 17 and the single crystal semiconductor epitaxial patterns 23e'. The lateral growth rate A may be smaller than the second lateral growth rate B in the bulk region of the single crystal semiconductor epitaxial patterns 23e ′. This is because the interlayer insulating layer 17 prevents the growth of the single crystal semiconductor epitaxial patterns 23e '. As a result, an undercut region may be formed under the edge of the single crystal semiconductor epitaxial patterns 23e '.

Meanwhile, as shown in FIG. 4B, the pair of node semiconductor plugs 21b are formed to be adjacent to each other, and the pair of openings 22t exposing the adjacent node semiconductor plugs 21b are adjacent to each other. When connected, the pair of single crystal semiconductor epitaxial patterns 23e 'formed by using the pair of node semiconductor plugs 21b as seed layers are continuously grown to form the second half cell regions. It may be in contact with each other at the boundary region between (H2). As a result, the pair of openings 22t is filled with a merged single crystalline semiconductor epitaxial pattern 23e. In this case, a void V may be formed in a boundary region between the second half cell regions H2. The void V is due to the difference between the first and second lateral growth rates A and B of the single crystal semiconductor epitaxial patterns 23e 'described above.

1, 2, 6A and 6B, the integrated single crystal semiconductor epitaxial pattern 23e is planarized to expose the top surface of the molding layer pattern 22c. The planarization of the integrated single crystal semiconductor epitaxial pattern 23e can be carried out using a chemical mechanical polishing process. As a result, single crystal semiconductor bodies 23b are formed in the openings 22t. While the single crystal semiconductor bodies 23b are formed, a pair of other single crystal semiconductor bodies 23a may also be formed in the first half cell regions H1. When the molding layer pattern 22c is formed to have the lower molding layer pattern 22a and the upper molding layer pattern 22b sequentially stacked as described above, the single crystal semiconductor bodies 23b may be It may be formed to have a thickness substantially the same as that of the molding layer pattern 22c. The void V may still remain between the single crystal semiconductor bodies 23b.

In the above-described embodiments, the single crystal semiconductor bodies 23b may be formed to have negative sloped sidewalls 23s. That is, the upper widths of the single crystal semiconductor bodies 23b may be larger than their lower widths. This is because the sidewalls 22s of the molding layer pattern 22c are formed to have a positively inclined profile as described above.

1, 2, 7A, and 7B, the gate insulating layer 25 is formed on the surfaces of the single crystal semiconductor bodies 23b. A gate conductive layer is formed on a substrate having the gate insulating layer 25, and the gate conductive layer is patterned so that gate electrodes crossing the upper portions of the single crystal semiconductor bodies 23b, that is, the load gate electrodes ( 27b). Different load gate electrodes 27a may be formed in the first half cell regions H1 adjacent to the second half cell regions H2 while the load gate electrodes 27b are formed. The load gate electrodes 27a in the first half cell regions H1 may extend to be adjacent to the node semiconductor plugs 21b in the second half cell regions H2. Similarly, the load gate electrodes 27b in the second half cell regions H2 may also extend to be adjacent to the node semiconductor plugs in the first half cell regions H1.

Impurity ions are implanted into the single crystal semiconductor bodies 23b using the load gate electrodes 27b as ion implantation masks to form source regions 29s and drain regions 29d. The drain regions 29d are formed in the single crystal semiconductor bodies 23b on the node semiconductor plugs 21b, and the source regions 29s are formed of the single crystal semiconductor between the load gate electrodes 27b. It is formed in the bodies 23b. As a result, a pair of load thin film transistors TL2 may be formed in the second half cell regions H2, respectively. While forming the load thin film transistors TL2, a pair of other load thin film transistors TL1 may be formed in the first half cell regions H1, respectively.

Each of the load thin film transistors TL2 includes the drain region 29d and the source region 29s positioned at both sides of the load gate electrode 27b together with the load gate electrode 27b. A second interlayer insulating layer 31 is formed on the substrate including the load thin film transistors TL2.

1, 2, 8A, and 8B, the second interlayer insulating layer 31, the load gate electrodes 27a and 27b, the molding layer pattern 22c, and the interlayer insulating layer 17. ) And the first gate contact holes 39a that sequentially etch the etch stop layer 15 to penetrate the load gate electrodes 27a and expose the first driving gate electrodes 7d '. Second gate contact holes 39b penetrating the load gate electrodes 27b and exposing the second driving gate electrodes 7d ″ are formed. The first and second gate contact holes 39a are formed. And metal gate plugs 41b in 39b. The metal gate plugs 41b are formed with respect to both the load gate electrodes 27a and 27b and the driving gate electrodes 7d 'and 7d ". It may be formed of a metal layer that exhibits ohmic contacts, for example a tungsten layer.

Subsequently, the second interlayer insulating layer 31, the load gate electrodes 27a and 27b, the molding layer pattern 22c, the interlayer insulating layer 17, and the etch stop layer 15 are continuously formed. First drain contact holes 43n 'that are etched to expose the load gate electrodes 27b, the drain regions 29d, the node semiconductor plugs, and the first node impurity regions in the first half cell regions H1. And the load gate electrodes 27a, the drain regions 29d, the node semiconductor plugs 21b, and the second node impurity regions 13n "in the second half cell regions H2. Second drain contact holes 43n ″ are formed. Metal drain plugs 45n "are formed in the drain contact holes 43n 'and 43n". The metal drain plugs 45n ″ may be formed on all of the load gate electrodes 27a and 27b, the drain regions 29d, the node semiconductor plugs 21b, and the node impurity regions 13n ″. It may be formed of a metal layer that exhibits ohmic contacts, for example a tungsten layer. The metal drain plugs 45n ″ may be formed before forming the metal gate plugs 41b.

9A and 10A are cross-sectional views taken along line II ′ of FIG. 2 to illustrate thin film transistor SRAM cells and methods of fabricating the same according to other embodiments of the present invention, and FIGS. 9B and 10B illustrate the present invention. FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 2 to describe thin film transistor SRAM cells and a method of manufacturing the same.

Referring to FIGS. 2, 9A and 9B, the first and second drives are driven to the semiconductor substrate 1 using the same methods as the embodiments described with reference to FIGS. 3A to 5A and to FIGS. 3B to 5B. Transistors TD1 and TD2, first and second transfer transistors TL1 and TL2, interlayer insulating layer 17, node semiconductor plugs 21b, molding layer pattern 22c, and single crystal semiconductor epitaxial pattern Field 23e '. In the present exemplary embodiment, the single crystal semiconductor epitaxial patterns 23e 'grown in the adjacent second half cell regions H2 may be formed so as not to contact each other. In this case, undercut regions may be formed below the edges of the separated single crystalline semiconductor epitaxial patterns 23e '.

A non-single crystalline semiconductor layer 23p, such as an amorphous semiconductor layer or a polycrystalline semiconductor layer, is formed on the substrate having the spaced apart single crystal semiconductor epitaxial patterns 23e '. The non-single crystal semiconductor layer 23p may be formed using a thin film deposition technique that exhibits excellent step coverage. For example, the non-single crystal semiconductor layer 23p may be formed using a chemical vapor deposition technique or an atomic layer deposition technique. Accordingly, the non-single crystal semiconductor layer 23p may be formed to completely fill the undercut regions under the edges of the single crystal semiconductor epitaxial patterns 23e '. When the single crystal semiconductor epitaxial patterns 23e ′ are single crystal silicon patterns, the non-single crystal semiconductor layer 23p may be formed of an amorphous silicon layer or a polycrystalline silicon layer.

2, 10A and 10B, the non-single crystal semiconductor layer 23p is crystallized using a conventional solid phase epitaxial technique. The single crystal semiconductor epitaxial patterns 23e 'serve as seed layers during the solid state epitaxial process. The top surface of the molding layer pattern 22c is exposed by planarizing the crystallized semiconductor layer (ie, the single crystal semiconductor layer) and the single crystal semiconductor epitaxial patterns 23e '. The planarization process can be carried out using a chemical mechanical polishing process. As a result, single crystal semiconductor bodies 23b 'which completely fill the openings 22t surrounded by the molding layer pattern 22c are formed. The solid state epitaxial process may be performed after the planarization process.

While the single crystal semiconductor bodies 23b 'are formed, other single crystal semiconductor bodies 23a' of FIG. 2 may also be formed in the first half cell regions H1. Each of the single crystal semiconductor bodies 23a 'and 23b' may be formed to have a planarized single crystal semiconductor epitaxial pattern 23e "and a planarized single crystal semiconductor layer 23p 'as shown in FIG. 10B. In addition, the single crystal semiconductor bodies 23a 'and 23b' are also formed to have sidewalls 23s' showing a negative sloped profile as described with reference to FIGS. 6A and 6B. Can be.

Subsequently, although not shown in the drawings, the substrate having the single crystal semiconductor bodies 23a 'and 23b' may be formed using the same methods as the embodiments described with reference to FIGS. 7A, 7B, 8A, and 8B. Load thin film transistors (TL2 in FIGS. 7A and 7B), metal gate plugs (41b in FIG. 8A), and metal drain plugs (45n ″ in FIG. 8B) may be formed.

11A to 13A are cross-sectional views taken along line II ′ of FIG. 2 to illustrate thin film transistor SRAM cells and methods of fabricating the same according to still other embodiments of the present invention, and FIGS. 11B to 13B illustrate the present invention. 2 are cross-sectional views taken along line II-II ′ of FIG. 2 to describe thin film transistor SRAM cells and a method of fabricating the same. The embodiments shown in FIGS. 3B-10B in conjunction with FIGS. 3A-10A employ a damascene technique to form the single crystal semiconductor bodies 23b, 23b ', whereas the present embodiments employ the single crystal semiconductor bodies. The reverse damascene technique is employed to form single crystal semiconductor bodies corresponding to (23b, 23b ').

2, 11A and 11B, the first and second driving transistors on the semiconductor substrate 1 using the same methods as the embodiments described with reference to FIGS. 3A, 3B, 4A, and 4B. Fields TD1 and TD2, first and second transfer transistors TL1 and TL2, an interlayer insulating layer 17, and node semiconductor plugs 21b are formed. A sacrificial layer is formed on the substrate having the node semiconductor plugs 21b. The sacrificial layer may be formed of a material layer having an etching selectivity with respect to the interlayer insulating layer 17. For example, when the interlayer insulating layer 17 is formed of a silicon oxide layer, the sacrificial layer may be formed of a silicon nitride layer. The sacrificial layer is patterned using a conventional photo / etch process to form sacrificial layer patterns 51b respectively covering the node semiconductor plugs 21b. In this case, the sacrificial layer patterns 51b may be formed to have positive inclined sidewalls 51s due to the general characteristics of the etching process. That is, upper widths of the sacrificial layer patterns 51b may be smaller than their lower widths. In addition, the sacrificial layer patterns 51b may be connected to each other in a boundary region of the second half cell regions H2 adjacent to each other, as shown in FIG.

The molding layer 53 is formed on the substrate having the sacrificial layer patterns 51b. The molding layer 53 may be formed as an insulating layer having an etch selectivity with respect to the sacrificial layer patterns 51b. For example, when the sacrificial layer patterns 51b are formed of a silicon nitride layer, the molding layer 53 may be formed of a silicon oxide layer.

2, 12A and 12B, the molding layer 53 is planarized to expose top surfaces of the sacrificial layer patterns 51b. The planarization process of the molding layer 53 may be performed using a chemical mechanical polishing process. As a result, a molding layer pattern 53a surrounding sidewalls 51s of the sacrificial layer patterns 51b is formed on the interlayer insulating layer 17, and the molding layer pattern 53a is formed on the sacrificial layer. It is formed to have a thickness substantially the same as the patterns 51b.

Subsequently, the sacrificial layer patterns 51b are selectively removed to form openings 53t exposing the node semiconductor plugs 21b, respectively. In this case, the sidewalls 53s of the openings 53t may exhibit a relatively negative inclined profile. In other words, the upper width of the openings 53t may be smaller than their lower width. This is because the sidewalls 51s of the sacrificial layer patterns 51b have a positively inclined profile as described above.

2, 13A and 13B, single crystal semiconductor bodies are formed in the openings 53t using the same methods as the embodiments described with reference to FIGS. 3A to 10A and 3B to 10B, respectively. 23b ″. While the single crystal semiconductor bodies 23b ″ are formed, other single crystal semiconductor bodies 23a ″ in FIG. 2 may also be formed in the first half cell regions H1. That is, each of the single crystal semiconductor bodies 23a "and 23b" is formed of only the flattened single crystal semiconductor epitaxial pattern like the single crystal semiconductor bodies 23b of FIG. 6B or the flattened semiconductor shown in FIG. 10B. It may be formed to have a single crystal semiconductor epitaxial pattern 23e ″ and the planarized single crystal semiconductor layer 23p '.

In the present embodiments, the single crystal semiconductor bodies 23a "and 23b" may be formed to have sidewalls 23s "showing a positive inclined profile. This is the sidewalls of the openings 53t. This is because 53s has a negatively inclined profile as described above.

Subsequently, although not shown in the drawings, the substrate having the single crystal semiconductor bodies 23a ", 23b" may be formed using the same methods as the embodiments described with reference to FIGS. 7A, 7B, 8A, and 8B. Load thin film transistors (TL2 in FIGS. 7A and 7B), metal gate plugs (41b in FIG. 8A), and metal drain plugs (45n ″ in FIG. 8B) may be formed.

According to the present exemplary embodiments, over-etching of the interlayer insulating layer 17 may be prevented while the openings 53t are formed. Accordingly, the single crystal semiconductor bodies 23a ″ and 23b ″ may be formed to have a uniform thickness without using the lower molding layer pattern 22a shown in FIGS. 4A and 4B. In addition, since the lower molding layer pattern 22a having an etch selectivity with respect to the interlayer insulating layers 17 and 31 is not required, contact holes penetrating through the interlayer insulating layers 17 and 31 may be formed. The contact holes can be prevented from being formed to have an abnormal sidewall profile.

The present invention is not limited to the above-described embodiments and can be applied to various other semiconductor integrated circuits. For example, the present invention is also applicable to a three layered structural CMOS SRAM cell having double stacked thin film transistors as shown in FIG. 14. Can be.

FIG. 14 is a cross-sectional view illustrating a first half cell of a CMOS SRAM cell having a pair of bulk MOS transistors, a pair of load thin film transistors, and a pair of transfer thin film transistors.

Referring to FIG. 14, an isolation layer 63 is provided in a predetermined region of the semiconductor substrate 61 to define the active region 63a. The first driving transistor TD1 is provided in the active region 63a. The first driving transistor TD1 crosses an upper portion of a channel region between the source / drain regions 71s and 71d together with a source region 71s and a drain region 71d formed in the active region 63a. It is formed to have a first driving gate electrode 67a. In addition, a second driving transistor (not shown) may be formed in a second half cell region adjacent to the first half cell region. The second driving gate electrode 67b of the second driving transistor may extend to cover the device isolation layer 63 adjacent to the drain region 71d in the first half cell region.

The first driving gate electrode 67a is insulated from the active region 63a by the gate insulating layer 65. Sidewalls of the first and second driving gate electrodes 67a and 67b are surrounded by spacers 69.

An etch stop layer 73 is provided on a substrate having the driving transistors, and an interlayer insulating layer 75 is stacked on the etch stop layer 73. The drain region 71d contacts the node semiconductor plug 77 having a single crystal structure penetrating the interlayer insulating layer 75 and the etch stop layer 73. The node semiconductor plug 77 may be manufactured using the methods of forming the node semiconductor plugs 21b of FIG. 4B.

A molding layer pattern 79 is provided on the interlayer insulating layer 75. The molding layer pattern 79 may be formed to have an opening exposing the node semiconductor plug 77 and the interlayer insulating layer 75 adjacent thereto. The molding layer pattern 79 may be manufactured by using the methods of forming the molding layer pattern 22c of FIGS. 4A and 4B. Alternatively, the molding layer pattern 79 may be manufactured using the methods of forming the molding layer pattern 53a described with reference to FIGS. 11A, 11B, 12A, and 12B.

A single crystal semiconductor body 81 is provided in the opening. The single crystal semiconductor body 81 may be manufactured using the methods of forming the single crystal semiconductor bodies 23b of FIGS. 6A and 6B. Alternatively, the single crystal semiconductor body 81 may be manufactured using the methods of forming the single crystal semiconductor bodies 23b 'of FIGS. 10A and 10B.

The first load thin film transistor TL1 is provided to the single crystal semiconductor body 81. The first load thin film transistor TL1 is adjacent to the first load gate electrode 85a and the first load gate electrode 85a crossing the upper portion of the single crystal semiconductor body 81 and the single crystal semiconductor plug 77. And a drain region 87d positioned above the source region and a source region 87s adjacent to the first load gate electrode 85a and positioned opposite to the drain region 87d. In addition, the first load gate electrode 85a is insulated from the single crystal semiconductor body 81 by the gate insulating layer 83. In addition, a second load thin film transistor (not shown) may be formed in a second half cell region adjacent to the first half cell region. The second load gate electrode 85b of the second load thin film transistor may extend to be adjacent to the drain region 87d in the first half cell region.

A second interlayer insulating layer 89 is provided on the substrate having the first and second load thin film transistors. The drain region 87d contacts the second node semiconductor plug 91 passing through the second interlayer insulating layer 89. The second node semiconductor plug 91 may be manufactured using the methods of forming the node semiconductor plugs 21b of FIG. 4B.

A second molding layer pattern 93 is provided on the second interlayer insulating layer 89. The second molding layer pattern 93 may be formed to have a second opening exposing the second node semiconductor plug 91 and the second interlayer insulating layer 89 adjacent thereto. The second molding layer pattern 93 may be manufactured using the methods of forming the molding layer pattern 22c of FIGS. 4A and 4B. Alternatively, the second molding layer pattern 93 may be fabricated using the methods of forming the molding layer pattern 53a described with reference to FIGS. 11A, 11B, 12A, and 12B. .

A second single crystal semiconductor body 95 is provided in the second opening that exposes the second node semiconductor plug 91. The second single crystal semiconductor body 95 may be manufactured using the methods of forming the single crystal semiconductor bodies 23b of FIGS. 6A and 6B. Alternatively, the second single crystal semiconductor body 95 may be manufactured using the methods of forming the single crystal semiconductor bodies 23b 'of FIGS. 10A and 10B.

A first transfer thin film transistor TT1 is provided to the second single crystal semiconductor body 95. The first transfer thin film transistor TT1 is disposed on the second single crystal semiconductor plug 91 adjacent to the word line 99 and the word line 99 crossing the upper portion of the second single crystal semiconductor body 95. It is formed to have a source region 101s positioned and a drain region 101d adjacent to the word line 99 and located opposite to the source region 101s. In addition, the word line 99 is insulated from the second single crystal semiconductor body 95 by the gate insulating layer 97. In addition, a second transfer thin film transistor (not shown) may be formed in the second half cell region. The word line 99 extends to serve as a gate electrode of the second transfer thin film transistor.

A third interlayer insulating layer 103 is provided on the substrate having the first and second transfer thin film transistors. The drain regions 71d and 87d, the node semiconductor plugs 77 and 91, the source region 101s, the second driving gate electrode 67b, and the second load gate electrode 85b are interlayered. The insulating layers 75, 89, and 103 may be electrically connected to each other through the metal node plug 105 penetrating through the etch stop layer 73 and the molding layer patterns 79 and 93.

As described above, according to the embodiments of the present invention, a single crystal semiconductor plug penetrating the interlayer insulating layer is formed, and the single crystal semiconductor epitaxial pattern is grown on the interlayer insulating layer using the single crystal semiconductor plug as a seed layer. . The single crystal semiconductor epitaxial pattern is planarized using a molding layer pattern formed on the interlayer insulating layer. As a result, a semiconductor body having a uniform thickness and an excellent single crystalline structure can be formed on the interlayer insulating layer. Therefore, in the case of forming a thin film transistor in the single crystal semiconductor body, it is possible to significantly improve the integration density, reliability, and electrical characteristic of the semiconductor integrated circuit.

1 is an exemplary equivalent circuit diagram of a CMOS SRAM cell.

2 is a plan view of CMOS SRAM cells employing thin film transistors fabricated in accordance with embodiments of the present invention.

3A to 8A are cross-sectional views taken along line II ′ of FIG. 2 to explain methods of manufacturing thin film transistors according to example embodiments.

3B to 8B are cross-sectional views taken along line II-II ′ of FIG. 2 to explain methods of manufacturing thin film transistors according to example embodiments.

9A and 10A are cross-sectional views taken along line II ′ of FIG. 2 to explain methods of fabricating thin film transistors according to other exemplary embodiments.

9B and 10B are cross-sectional views taken along line II-II ′ of FIG. 2 to explain methods of manufacturing thin film transistors according to other exemplary embodiments.

11A to 13A are cross-sectional views taken along line II ′ of FIG. 2 to explain methods of fabricating thin film transistors according to other exemplary embodiments.

11B to 13B are cross-sectional views taken along line II-II ′ of FIG. 2 to explain methods of fabricating thin film transistors according to other exemplary embodiments.

14 is a cross-sectional view illustrating a half cell of a CMOS SRAM cell employing thin film transistors according to other exemplary embodiments of the present inventive concept.

Claims (94)

Forming an interlayer insulating layer on the single crystal semiconductor substrate, Forming a single crystal semiconductor plug penetrating the interlayer insulating layer, Forming a molding layer pattern having an opening that exposes the single crystal semiconductor plug on a substrate having the single crystal semiconductor plug, Forming a single crystal semiconductor epitaxial pattern covering the exposed single crystal semiconductor plug using a selective epitaxial growth technique employing the exposed single crystal semiconductor plug as a seed layer, Forming a single crystal semiconductor body having a portion of the single crystal semiconductor epitaxial pattern in the opening. The method of claim 1, wherein forming the single crystal semiconductor plug Patterning the interlayer insulating layer to form a contact hole exposing the single crystal semiconductor substrate, Growing a single crystal semiconductor epitaxial layer filling the contact hole using a selective epitaxial growth technique employing the exposed single crystal semiconductor substrate as a seed layer. The method of claim 2, And planarizing the single crystal semiconductor epitaxial layer. The method of claim 1, wherein the forming of the molding layer pattern is performed. Forming a molding layer on the substrate having the single crystal semiconductor plug, Patterning the molding layer to expose the single crystal semiconductor plug. The method of claim 4, wherein And the molding layer is formed of a single layer of silicon oxide. The method of claim 1, wherein the forming of the molding layer pattern is performed. A lower molding layer and an upper molding layer are sequentially formed on the substrate having the single crystal semiconductor plug, And patterning the upper molding layer and the lower molding layer to expose the single crystal semiconductor plug. The method of claim 6, The lower molding layer is formed of an insulating layer having an etch selectivity with respect to the interlayer insulating layer, and the upper molding layer is formed of an insulating layer having an etch selectivity with respect to the lower molding layer. Manufacturing method. The method of claim 7, wherein And the lower molding layer is formed of a silicon nitride layer, and the upper molding layer is formed of a silicon oxide layer. The method of claim 1, wherein the forming of the molding layer pattern is performed. Forming a sacrificial layer pattern covering the single crystal semiconductor plug on the substrate having the single crystal semiconductor plug, Forming a molding layer covering the sacrificial layer pattern and the interlayer insulating layer, Planarizing the molding layer to expose an upper surface of the sacrificial layer pattern, Selectively removing the sacrificial layer pattern to expose the single crystal semiconductor plug. The method of claim 9, The sacrificial layer pattern may be formed of a material layer having an etch selectivity with respect to the interlayer insulating layer and the molding layer. The method of claim 10, The sacrificial layer pattern is formed of a silicon nitride layer, and the molding layer is a manufacturing method of a semiconductor integrated circuit, characterized in that the silicon oxide layer. The method of claim 1, wherein the single crystal semiconductor body is formed by planarizing the single crystal semiconductor epitaxial pattern until the upper surface of the molding layer pattern is exposed. The method of claim 1, wherein forming the single crystal semiconductor body Forming an amorphous semiconductor layer or a polycrystalline semiconductor layer on the substrate having the single crystal semiconductor epitaxial pattern, Crystallizing the amorphous semiconductor layer or the polycrystalline semiconductor layer using a solid state epitaxial technique, Planarizing the crystallized semiconductor layer and the single crystal semiconductor epitaxial pattern until the top surface of the molding layer pattern is exposed. The method of claim 1, wherein forming the single crystal semiconductor body Forming an amorphous semiconductor layer or a polycrystalline semiconductor layer on the substrate having the single crystal semiconductor epitaxial pattern, Continuously planarizing the single crystal semiconductor epitaxial pattern together with the amorphous semiconductor layer or the polycrystalline semiconductor layer until the upper surface of the molding layer pattern is exposed, And crystallizing the planarized amorphous semiconductor layer or the planarized polycrystalline semiconductor layer using a solid state epitaxial process. The method of claim 1, And forming a thin film transistor in the single crystal semiconductor body. The method of claim 15, wherein forming the thin film transistor Forming an insulated gate electrode across the top of the single crystal semiconductor body, And forming source / drain regions by implanting impurity ions into the single crystal semiconductor body using the gate electrode as an ion implantation mask. The method of claim 1, Before forming the interlayer insulating layer, an isolation layer is formed in a predetermined region of the single crystal semiconductor substrate to define an active region. And forming a bulk MOS transistor in the active region, wherein the bulk MOS transistor includes a source region located at both sides of the channel region below the gate electrode, together with a gate electrode crossing the upper portion of the active region; A method for manufacturing a semiconductor integrated circuit, characterized in that it is formed to have a drain region. The method of claim 17, And the single crystal semiconductor plug is formed to contact at least one of the source / drain regions of the bulk MOS transistor. A method of manufacturing a thin film transistor SRAM cell consisting of first and second half cells, the method of manufacturing any one of the first and second half cells Forming an isolation layer in a predetermined region of the single crystal semiconductor substrate to limit the active region, A driving transistor is formed in the active region, wherein the driving transistor has a source region and a drain region respectively positioned at both sides of the channel region below the driving gate electrode together with a driving gate electrode crossing the upper portion of the active region. Formed, Forming an interlayer insulating layer on the substrate having the drive transistor, Forming a single crystal semiconductor plug penetrating the interlayer insulating layer to contact the drain region of the driving transistor; Forming a molding layer pattern having an opening that exposes the single crystal semiconductor plug on a substrate having the single crystal semiconductor plug, Forming a single crystal semiconductor epitaxial pattern covering the exposed single crystal semiconductor plug using a selective epitaxial growth technique employing the exposed single crystal semiconductor plug as a seed layer, And forming a single crystal semiconductor body having a portion of the single crystal semiconductor epitaxial pattern in the opening. 20. The method of claim 19, wherein forming the single crystal semiconductor plug Patterning the interlayer insulating layer to form a node contact hole exposing the drain region of the driving transistor, Growing a single crystal semiconductor epitaxial layer filling the node contact hole using a selective epitaxial growth technique employing the exposed drain region as a seed layer. The method of claim 20, And planarizing the single crystal semiconductor epitaxial layer. The method of claim 19, wherein forming the molding layer pattern Forming a molding layer on the substrate having the single crystal semiconductor plug, Patterning the molding layer to expose the single crystal semiconductor plug. The method of claim 22, And the molding layer is formed of a silicon oxide layer. 20. The method of claim 19, wherein forming the molding layer pattern A lower molding layer and an upper molding layer are sequentially formed on the substrate having the single crystal semiconductor plug, And patterning the upper molding layer and the lower molding layer to expose the single crystal semiconductor plug. The method of claim 24, The lower molding layer is formed of an insulating layer having an etch selectivity with respect to the interlayer insulating layer, and the upper molding layer is formed of an insulating layer having an etch selectivity with respect to the lower molding layer. Ram cell manufacturing method. The method of claim 25, And the lower molding layer is formed of a silicon nitride layer, and the upper molding layer is formed of a silicon oxide layer. The method of claim 19, wherein forming the molding layer pattern Forming a sacrificial layer pattern covering the single crystal semiconductor plug on the substrate having the single crystal semiconductor plug, Forming a molding layer covering the sacrificial layer pattern and the interlayer insulating layer, Planarizing the molding layer to expose an upper surface of the sacrificial layer pattern, And selectively removing the sacrificial layer pattern to expose the single crystal semiconductor plug. The method of claim 27, The sacrificial layer pattern may be formed of a material layer having an etch selectivity with respect to the interlayer insulating layer and the molding layer. The method of claim 28, The sacrificial layer pattern is formed of a silicon nitride layer, and the molding layer is a thin film transistor SRAM cell manufacturing method characterized in that the silicon oxide layer. 20. The method of claim 19, wherein the single crystal semiconductor body is formed by planarizing the single crystal semiconductor epitaxial pattern until the upper surface of the molding layer pattern is exposed. 20. The method of claim 19, wherein forming the single crystal semiconductor body Forming an amorphous semiconductor layer or a polycrystalline semiconductor layer on the substrate having the single crystal semiconductor epitaxial pattern, Crystallizing the amorphous semiconductor layer or the polycrystalline semiconductor layer using a solid state epitaxial technique, Planarizing the crystallized semiconductor layer and the single crystal semiconductor epitaxial pattern until the top surface of the molding layer pattern is exposed. 20. The method of claim 19, wherein forming the single crystal semiconductor body Forming an amorphous semiconductor layer or a polycrystalline semiconductor layer on the substrate having the single crystal semiconductor epitaxial pattern, Continuously planarizing the single crystal semiconductor epitaxial pattern together with the amorphous semiconductor layer or the polycrystalline semiconductor layer until the upper surface of the molding layer pattern is exposed, Thinning the planarized amorphous semiconductor layer or the planarized polycrystalline semiconductor layer using a solid state epitaxial process. The method of claim 19, Forming a load thin film transistor serving as a load transistor in the single crystal semiconductor body, wherein the load thin film transistor includes a load gate electrode crossing the upper portion of the single crystal semiconductor body, and the load gate electrode. And a drain region adjacent to and positioned on the single crystal semiconductor plug, and a source region adjacent to the load gate electrode and opposite to the drain region. The method of claim 33, wherein Forming a second interlayer insulating layer on the substrate having the load thin film transistor, Forming a second single crystal semiconductor plug penetrating the second interlayer insulating layer to contact the drain region of the load thin film transistor, Forming a second molding layer pattern having a second opening that exposes the second single crystal semiconductor plug on the substrate having the second single crystal semiconductor plug, Forming a second single crystal semiconductor epitaxial pattern covering the second single crystal semiconductor plug by using a selective epitaxial growth technique employing the second single crystal semiconductor plug as a seed layer, And forming a second single crystal semiconductor body having a portion of the second single crystal semiconductor epitaxial pattern in the second opening. The method of claim 34, wherein And the second single crystal semiconductor plug is formed using a selective epitaxial growth technique employing the drain region of the load thin film transistor as a seed layer. 35. The method of claim 34, wherein forming the second molding layer pattern Forming a second molding layer on the substrate having the second single crystal semiconductor plug, And patterning the second molding layer to expose the second single crystal semiconductor plug. The method of claim 36, And the second molding layer is formed of a silicon oxide layer. 35. The method of claim 34, wherein forming the second molding layer pattern A second lower molding layer and a second upper molding layer are sequentially formed on the substrate having the second single crystal semiconductor plug, And patterning the second upper molding layer and the second lower molding layer to expose the second single crystal semiconductor plug. The method of claim 38, The second lower molding layer is formed of an insulating layer having an etch selectivity with respect to the second interlayer insulating layer, and the second upper molding layer is formed of an insulating layer having an etch selectivity with respect to the second lower molding layer. Thin film transistor SRAM cell manufacturing method characterized in that. The method of claim 39, And the second lower molding layer is formed of a silicon nitride layer, and the second upper molding layer is formed of a silicon oxide layer. 35. The method of claim 34, wherein forming the second molding layer pattern Forming a second sacrificial layer pattern covering the second single crystal semiconductor plug on the substrate having the second single crystal semiconductor plug; Forming a second molding layer covering the second sacrificial layer pattern and the second interlayer insulating layer; Planarizing the second molding layer to expose an upper surface of the second sacrificial layer pattern, And selectively removing the second sacrificial layer pattern to expose the second single crystal semiconductor plug. The method of claim 41, wherein The second sacrificial layer pattern may be formed of a material layer having an etch selectivity with respect to the second interlayer insulating layer and the second molding layer. The method of claim 42, And the second sacrificial layer pattern is formed of a silicon nitride layer, and the second molding layer is formed of a silicon oxide layer. The method of claim 34, wherein And the second single crystal semiconductor body is formed by planarizing the second single crystal semiconductor epitaxial pattern until the upper surface of the second molding layer pattern is exposed. 35. The method of claim 34, wherein forming the second single crystal semiconductor body is Forming a second amorphous semiconductor layer or a second polycrystalline semiconductor layer on the substrate having the second single crystal semiconductor epitaxial pattern, Crystallizing the second amorphous semiconductor layer or the second polycrystalline semiconductor layer using a solid state epitaxial technique, Planarizing the crystallized semiconductor layer and the second single crystal semiconductor epitaxial pattern until the top surface of the second molding layer pattern is exposed. 35. The method of claim 34, wherein forming the second single crystal semiconductor body is Forming a second amorphous semiconductor layer or a second polycrystalline semiconductor layer on the substrate having the second single crystal semiconductor epitaxial pattern, Continuously planarizing the second single crystal semiconductor epitaxial pattern together with the second amorphous semiconductor layer or the second polycrystalline semiconductor layer until the upper surface of the second molding layer pattern is exposed, Thinning the planarized semiconductor layer using a solid state epitaxial process. The method of claim 34, wherein Forming a transfer thin film transistor serving as a transfer transistor in the second single crystal semiconductor body, wherein the transfer thin film transistor comprises a transfer gate electrode crossing the upper portion of the second single crystal semiconductor body; And a source region adjacent to the transfer gate electrode and positioned on the second single crystal semiconductor plug, and a drain region adjacent to the transfer gate electrode and positioned opposite to the source region. Cell manufacturing method. The method of claim 47, Forming a third interlayer insulating layer on the substrate having the transfer thin film transistor, And forming a node metal plug passing through the first to third interlayer insulating layers, wherein the node metal plug comprises: the drain region of the driving transistor, the single crystal semiconductor plug, the drain region of the load thin film transistor, And forming a metal layer having ohmic contacts with respect to the source region of the second single crystal semiconductor plug and the transfer thin film transistor. The method of claim 33, wherein And forming a transfer transistor in the active region while forming the driving transistor, wherein the transfer transistor is adjacent to both sides of the channel region below the transfer gate electrode, together with a transfer gate electrode across the top of the active region. And a source region and a drain region respectively disposed in the source transistor, wherein the source region of the transfer transistor corresponds to the drain region of the driving transistor. The method of claim 49, Forming a second interlayer insulating layer on the substrate having the load thin film transistor, And forming a node metal plug passing through the first and second interlayer insulating layers, wherein the node metal plug comprises the drain region of the driving transistor, the single crystal semiconductor plug, and the drain region of the load thin film transistor. And forming a metal layer having ohmic contacts with respect to the thin film transistor. An interlayer insulating layer stacked on the single crystal semiconductor substrate; A single crystal semiconductor plug penetrating the interlayer insulating layer; A single crystal semiconductor body provided on said interlayer insulating layer and extending in contact with said single crystal semiconductor plug; And And a molding layer pattern surrounding sidewalls of the single crystal semiconductor body, wherein the molding layer pattern has a thickness substantially the same as that of the single crystal semiconductor body. The method of claim 51, wherein And said single crystal semiconductor plug is an epitaxial layer formed using a selective epitaxial growth technique employing said single crystal semiconductor substrate as a seed layer. The method of claim 51, wherein And wherein said single crystal semiconductor body is a single crystal epitaxial pattern formed using a selective epitaxial growth technique employing said single crystal semiconductor plug as a seed layer. The method of claim 51, wherein the single crystal semiconductor body A single crystal epitaxial pattern formed using a selective epitaxial growth technique employing the single crystal semiconductor plug as a seed layer; And And a semiconductor layer crystallized using a solid state epitaxial technique employing the single crystal epitaxial pattern as a seed layer. The method of claim 54, wherein And the crystallized semiconductor layer is a single crystal semiconductor layer formed by crystallizing an amorphous semiconductor layer or a polycrystalline semiconductor layer. The method of claim 51, wherein The molding layer pattern is a semiconductor layer, characterized in that a single insulating layer (a single insulating layer) or a double insulating layer (a double insulating layer). The method of claim 56, wherein And said single insulating layer is a silicon oxide layer. The method of claim 56, wherein The double insulating layer may include a lower molding layer pattern and an upper molding layer pattern sequentially stacked, and the lower molding layer pattern may be an insulating layer having an etch selectivity with respect to the interlayer insulating layer and the upper molding layer pattern. Semiconductor integrated circuit. The method of claim 58, And the lower molding layer pattern and the upper molding layer pattern are silicon nitride layers and silicon oxide layers, respectively. The method of claim 56, wherein Wherein when the molding layer pattern is the single insulating layer, the single crystal semiconductor body has a negative sloped sidewall profile such that the top width of the single crystal semiconductor body is greater than its bottom width. Semiconductor integrated circuit. The method of claim 56, wherein Wherein when the molding layer pattern is the single insulating layer, the single crystal semiconductor body has a positive sloped sidewall profile such that the top width of the single crystal semiconductor body is less than its bottom width. Semiconductor integrated circuit. The method of claim 56, wherein Wherein when the molding layer pattern is the double insulating layer, the single crystal semiconductor body has a negative sloped sidewall profile such that the top width of the single crystal semiconductor body is greater than its bottom width. Semiconductor integrated circuit. 53. The semiconductor device of claim 51, further comprising a thin film transistor formed on the single crystal semiconductor body, wherein the thin film transistor includes a source region and a drain region formed at both ends of the single crystal semiconductor body, as well as a channel between the source region and the drain region. And an insulated gate electrode across the top of the region. The method of claim 51, wherein An isolation layer formed in a predetermined region of the single crystal semiconductor substrate to define an active region; And The bulk MOS transistor further includes a bulk MOS transistor formed in the active region, wherein the bulk MOS transistor includes an insulated gate electrode crossing an upper portion of a channel region between the source region and the drain region, together with a source region and a drain region formed in the active region. It has a semiconductor integrated circuit. The method of claim 64, wherein And the single crystal semiconductor plug is electrically connected to any one of the source / drain regions of the bulk MOS transistor. In the thin film transistor SRAM cell consisting of first and second half cells, each of the first and second half cells An isolation layer formed in a predetermined region of the single crystal semiconductor substrate and defining an active region; A driving transistor formed in the active region, the driving transistor having a source region and a drain region formed in the active region and a driving gate electrode crossing the upper portion of the channel region between the source / drain regions; An interlayer insulating layer provided on the substrate having the drive transistor; A single crystal semiconductor plug penetrating the interlayer insulating layer to contact the drain region of the driving transistor; A single crystal semiconductor body provided on the interlayer insulating layer and extending to cover the single crystal semiconductor plug; And And a molding layer pattern surrounding sidewalls of the single crystal semiconductor body, wherein the molding layer pattern has a thickness substantially the same as that of the single crystal semiconductor body. The method of claim 66, wherein And the single crystal semiconductor plug is an epitaxial layer formed using a selective epitaxial growth technique employing the drain region of the driving transistor as a seed layer. The method of claim 66, wherein And the single crystal semiconductor body is a single crystal epitaxial pattern formed using a selective epitaxial growth technique employing the single crystal semiconductor plug as a seed layer. 67. The method of claim 66, wherein the single crystal semiconductor body is A single crystal epitaxial pattern formed using a selective epitaxial growth technique employing the single crystal semiconductor plug as a seed layer; And And a semiconductor layer crystallized using a solid state epitaxial technique employing the single crystal epitaxial pattern as a seed layer. The method of claim 69, And the crystallized semiconductor layer is a single crystal semiconductor layer formed by crystallizing an amorphous semiconductor layer or a polycrystalline semiconductor layer. The method of claim 66, wherein The molding layer pattern is a thin film transistor SRAM cell, characterized in that a single insulating layer (a single insulating layer) or a double insulating layer (a double insulating layer). The method of claim 71 wherein And the single insulating layer is a silicon oxide layer. The method of claim 71 wherein The double insulating layer may include a lower molding layer pattern and an upper molding layer pattern sequentially stacked, and the lower molding layer pattern may be an insulating layer having an etch selectivity with respect to the interlayer insulating layer and the upper molding layer pattern. Thin film transistor SRAM cell. The method of claim 73, wherein And the lower molding layer pattern and the upper molding layer pattern are silicon nitride and silicon oxide layers, respectively. The method of claim 71 wherein Wherein when the molding layer pattern is the single insulating layer, the single crystal semiconductor body has a negative sloped sidewall profile such that the top width of the single crystal semiconductor body is greater than its bottom width. Thin film transistor SRAM cell. The method of claim 71 wherein Wherein when the molding layer pattern is the single insulating layer, the single crystal semiconductor body has a positive sloped sidewall profile such that the top width of the single crystal semiconductor body is less than its bottom width. Thin film transistor SRAM cell. The method of claim 71 wherein Wherein when the molding layer pattern is the double insulating layer, the single crystal semiconductor body has a negative sloped sidewall profile such that the top width of the single crystal semiconductor body is greater than its bottom width. Thin film transistor SRAM cell. 67. The semiconductor device of claim 66, further comprising a load thin film transistor formed on the single crystal semiconductor body, wherein the load thin film transistor is a load gate electrode across the top of the single crystal semiconductor body, adjacent the load gate electrode and on the single crystal semiconductor plug. And a source region adjacent to the load gate electrode and opposite to the drain region. The method of claim 78, A second interlayer insulating layer formed on the substrate having the load thin film transistor; A second single crystal semiconductor plug penetrating the second interlayer insulating layer to contact the drain region of the load thin film transistor; A second single crystal semiconductor body provided on the second interlayer insulating layer and extending to cover the second single crystal semiconductor plug; And And a second molding layer pattern surrounding sidewalls of the second single crystal semiconductor body, wherein the second molding layer pattern has a thickness substantially the same as that of the second single crystal semiconductor body. 80. The method of claim 79 wherein And the second single crystal semiconductor plug is an epitaxial layer formed using a selective epitaxial growth technique employing the drain region of the load thin film transistor as a seed layer. 80. The method of claim 79 wherein And the second single crystal semiconductor body is a single crystal epitaxial pattern formed using a selective epitaxial growth technique employing the second single crystal semiconductor plug as a seed layer. 80. The semiconductor device of claim 79 wherein the second single crystal semiconductor body is A second single crystal epitaxial pattern formed using a selective epitaxial growth technique employing the second single crystal semiconductor plug as a seed layer; And And a second crystallized semiconductor layer crystallized using a solid state epitaxial technique employing the second single crystal epitaxial pattern as a seed layer. 83. The method of claim 82, And the second crystallized semiconductor layer is a second single crystal semiconductor layer formed by crystallizing an amorphous semiconductor layer or a polycrystalline semiconductor layer. 80. The method of claim 79 wherein And the second molding layer pattern is a single insulating layer or a double insulating layer. 87. The method of claim 84, And the single insulating layer is a silicon oxide layer. 87. The method of claim 84, The double insulating layer may include a lower molding layer pattern and an upper molding layer pattern sequentially stacked, and the lower molding layer pattern may be an insulating layer having an etch selectivity with respect to the interlayer insulating layer and the upper molding layer pattern. Thin film transistor SRAM cell. 87. The method of claim 86, And the lower molding layer pattern and the upper molding layer pattern are silicon nitride and silicon oxide layers, respectively. 87. The method of claim 84, When the second molding layer pattern is the single insulating layer, the second single crystal semiconductor body has a negative sloped sidewall profile such that an upper width of the second single crystal semiconductor body is larger than its lower width. A thin film transistor SRAM cell having a). 87. The method of claim 84, In the case where the second molding layer pattern is the single insulating layer, the second single crystal semiconductor body has a positive sloped sidewall profile such that the upper width of the second single crystal semiconductor body is smaller than its lower width. A thin film transistor SRAM cell having a). 87. The method of claim 84, When the second molding layer pattern is the double insulating layer, the second single crystal semiconductor body has a negative sloped sidewall profile such that an upper width of the second single crystal semiconductor body is larger than its lower width. A thin film transistor SRAM cell having a). 80. The semiconductor device of claim 79, further comprising a transfer thin film transistor formed on the second single crystal semiconductor body, wherein the transfer thin film transistor is a transfer gate electrode across an upper portion of the second single crystal semiconductor body, adjacent the transfer gate electrode, and And a drain region positioned on a second single crystal semiconductor plug, and a drain region adjacent to the transfer gate electrode and opposite to the source region. 92. The method of claim 91 wherein A third interlayer insulating layer provided on the substrate having the transfer thin film transistor; And a node metal plug passing through the first to third interlayer insulating layers, wherein the node metal plug includes the drain region of the driving transistor, the single crystal semiconductor plug, the drain region of the load thin film transistor, and the second plug. And a metal layer having ohmic contacts with respect to the source region of the single crystal semiconductor plug and the transfer thin film transistor. The method of claim 78, A transfer transistor formed in the active region and adjacent to the driving transistor, wherein the transfer transistor is positioned at both sides of the channel region below the transfer gate electrode together with a transfer gate electrode crossing the upper portion of the active region; And a source region and a drain region, wherein the source region of the transfer transistor corresponds to the drain region of the driving transistor. 94. The method of claim 93, A second interlayer insulating layer formed on the substrate having the load thin film transistor and the transfer transistor; And And a node metal plug penetrating the first and second interlayer insulating layers, wherein the node metal plug is resistant to the drain region of the driving transistor, the single crystal semiconductor plug, and the drain region of the load thin film transistor. A thin film transistor SRAM cell, characterized in that it is a metal layer having an ohmic contact.