KR20050096563A - Array substrate and the fabrication method for lcd - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and relates to an array substrate for a liquid crystal display device for reducing a mask and a manufacturing method thereof.

According to the present invention, in the manufacture of a liquid crystal display device using poly-silicon, the gate wiring and the pixel electrode are formed as one mask, thereby reducing the number of masks, reducing the manufacturing process and manufacturing cost, and improving the production yield. .

In addition, the present invention has a pad structure that enables the rework and prevention of electroforming by forming the pad portion with a transparent conductive electrode, and reduces the spreading and defects of the pad portion by forming the pad structure with a transparent conductive electrode material. It has the advantage of improving the reliability.

Description

Array substrate for liquid crystal display device and manufacturing method therefor {array substrate and the fabrication method for LCD}

The present invention relates to a flat panel display device.

In general, a flat panel display device includes a liquid crystal display device (LCD), a plasma display panel (PDP), a field emission display (FED), and the like.

Today, the liquid crystal display device has been spotlighted as a next generation advanced display device having low power consumption, good portability, technology intensive and high added value.

The liquid crystal display device injects a liquid crystal between an array substrate including a thin film transistor (TFT) and a color filter substrate to obtain an image effect by using a difference in refractive index of light according to the anisotropy of the liquid crystal. Means an image display device by a non-light emitting element.

In the current flat panel display field, active matrix liquid crystal display (AMLCD) is the mainstream. In AMLCD, a thin film transistor is used as a switching element that changes the transmittance of a pixel by adjusting a voltage applied to a liquid crystal of one pixel.

Hydrogenated amorphous silicon (Amorphous-Silicon: H; abbreviated as amorphous silicon) is mainly used as the thin film transistor device, which is easy to fabricate in large areas, highly productive, and deposited at a low substrate temperature of 350 ° C or lower. This is because a low cost insulating substrate can be used.

However, the hydrogenated amorphous silicon has a weak Si-Si bond and dangling bond because of its disordered atomic arrangement, which is converted into a quasi-stable state when irradiated with light or an electric field, and used as a thin film transistor device. Stability is a problem.

In particular, amorphous silicon has a problem in that its characteristics are deteriorated by light irradiation, and it is difficult to use in a driving circuit due to the electrical characteristics (low field effect mobility: 0.1 to 1.0 cm 2 / V · s) and reliability of the display pixel driving element. There are disadvantages.

That is, the amorphous silicon thin film transistor substrate connects an insulating substrate and a printed circuit board (PCB) using a tape carrier package (TCP) driving IC (Integrated Circuit), and a large portion of the cost is used for the driving IC and the actual equipment.

In addition, when the resolution of the liquid crystal panel for a liquid crystal display device is increased, the pad pitch outside the substrate connecting the gate wiring and the data wiring of the thin film transistor substrate with the TCP becomes short, so that the TCP bonding itself becomes difficult.

However, since polycrystalline silicon has a greater field effect mobility than amorphous silicon, a driving circuit can be made on a substrate. If the driving circuit is directly made on the substrate, the IC cost can be reduced and the mounting can be simplified.

In addition, polycrystalline silicon has a higher field effect mobility than amorphous silicon, and is advantageous as a switching device of a high resolution panel. The polycrystalline silicon may be applied to a display device in which a lot of light is irradiated due to less photocurrent than amorphous silicon.

1A and 1B, the structure of the thin film transistor provided in the conventional liquid crystal display will be described.

In the pixel portion thin film transistor portion I of FIG. 1A, a buffer layer 114 is formed over an entire surface of an insulating substrate 100, and a semiconductor layer 116 is formed thereon, and the semiconductor layer ( The gate insulating film 118 and the gate electrode 120 are sequentially stacked on the center portion 116.

In addition, an interlayer insulating layer 124 including first and second semiconductor layer contact holes 122a and 122b is formed on the gate electrode 120, and the first and second semiconductor layer contact holes 122a are formed. And 122b, respectively, and the source and drain electrodes 126 and 128 are formed to be spaced apart from each other at positions overlapping the gate electrode 120 by a predetermined interval.

Here, a passivation layer 132 including a drain contact hole 130 is formed on the source and drain electrodes 126 and 128, and the drain contact hole 130 is formed on the passivation layer 132. The pixel electrode 134 is connected to the drain electrode 128.

In the semiconductor layer 116, a region corresponding to the gate insulating layer 118 forms an activation layer 116a, and a portion of the semiconductor layer 116 contacting the source and drain electrodes 126 and 128 is n + doped n-type impurity. A lightly doped drain (LDD) layer 116b is formed at the junction between the drain electrode 128 and the gate electrode 120 between the activation layer 116a and the n-type impurity layer 116c. ) Is located.

The LDD layer 116b serves to prevent an increase in leakage current and prevent current loss in an on state by doping at a low concentration for the purpose of dispersing hot carriers.

On the other hand, as shown in Figure 1b, the thin film transistor of the drive circuit portion is a thin film transistor section (II) having a channel (channel) by the n-type ion doping treatment, and a thin film transistor section having a channel by the p-type ion doping treatment It consists of (III), and for convenience of description, the same code | symbol is described in order of II and III about the same element.

As shown in FIG. 1B, the n-type semiconductor layer 140 and the p-type semiconductor layer 142 are formed to be spaced apart from each other on the substrate 100 on which the buffer layer 114 is formed.

Gate insulating layers 144a and 144b and gate electrodes 146a and 146b are formed on the n-type and p-type semiconductor layers 140 and 142, respectively, and on the entire surface of the substrate on the gate electrodes 146a and 146b. An interlayer insulating film 124 including semiconductor layer contact holes 147a, 147b, 147c, and 147d is formed.

In addition, the interlayer insulating layer 124 is connected to the n-type and p-type semiconductor layers 140 and 142 through the semiconductor layer contact holes 147a, 147b, 147c, and 147d, respectively. And 152a, 150b and 152b, and a protective layer 132 is formed over the entire surface of the source and drain electrodes 150a, 152a and 150b and 152b.

The n-type semiconductor layer 140 contacts the source and drain electrodes 150a and 152a with the active layer 140a having a region in contact with the gate insulating layer 144a as in the semiconductor layer 116 of FIG. 1A. The n-type impurity layer 140c is included, and the region therebetween is composed of the LDD layer 140b.

In addition, since the p-type semiconductor layer 142 uses a positively charged carrier, there is no greater effect of carrier degradation and leakage current than the n-type thin film transistor unit II, and thus does not form a separate LDD layer. A region in contact with the second gate insulating layer 144b is used as the activation layer 142a, and an outer region of the activation layer 142a is configured as the p-type impurity layer 142b.

Hereinafter, a manufacturing process of a thin film transistor of a pixel unit and a thin film transistor of a driving circuit unit of the conventional liquid crystal display device will be described with reference to FIG. 2. 2 is a process flowchart showing a manufacturing method of a conventional liquid crystal display device.

Each step of the manufacturing process shown in FIG. 2 involves a photolithography process (hereinafter, abbreviated as a mask process) using a photosensitive photo resist (PR).

As shown, first, an active layer is formed on an insulating substrate (step S101).

In more detail, first, a buffer layer having a thickness of about 3000 μs is formed on the transparent insulating substrate. In this case, an inorganic insulating film such as a silicon nitride film (SiNx) or a silicon oxide film (SiOx) is mainly used as a material of the buffer layer.

Thereafter, amorphous silicon (a-Si) is deposited to a thickness of about 550 상 에 on the substrate on which the buffer layer is formed, and after dehydrogenation, crystalline silicon such as polycrystalline or monocrystalline silicon is formed through a crystallization step.

Then, the crystalline silicon is formed into an activation layer by a first mask process.

Thereafter, a process of forming a gate insulating film and a gate electrode is performed (step S102). Here, a silicon nitride film of about 1000 mW and molybdenum (Mo) of 2000 mW are continuously deposited on the substrate on which the activation layer is formed, and then a gate insulating film and a gate electrode are formed through a second mask process.

Then, the step of forming the n-type semiconductor layer is performed (step S103). Here, the LDD layer is formed by performing n-doping treatment on the substrate on which the gate insulating film and the gate electrode are formed, and then an n-type impurity layer treated with n + doping is formed through a third mask process.

Subsequently, a step of forming a p-type semiconductor layer is performed (step S104). Here, the p-type doped p-type impurity layer is formed on the substrate on which the n-type impurity layer is formed through a fourth mask process.

Then, the step of forming the interlayer insulating film is performed (step S105). Here, after depositing an inorganic insulating film such as a silicon nitride film or a silicon oxide film of about 7000 kV on the substrate on which the p-type impurity layer is formed, a contact hole for contact with the semiconductor layer is formed in the interlayer insulating film by a fifth mask process. do.

Next, the step of forming the source and drain electrodes is performed (step S106). In this step, about 500 kW of molybdenum and about 3000 kW of aluminum neodium (AlNd) are sequentially deposited on the substrate on which the interlayer insulating film is formed.

Then, batch etching is performed by a sixth mask process to form source and drain electrodes connected to the impurity layer through the contact hole formed in step S105.

Thereafter, a step of forming a protective layer is performed (step S107).

In this step, a silicon nitride film of about 4000 kV is deposited on the substrate on which the source and drain electrodes are formed, and the silicon nitride film is subjected to a hydrogenation heat treatment process.

At this time, the hydrogenation heat treatment process, including the annealing step to drive the hydrogen contained in the silicon nitride film on the bottom, generally is performed once using nitrogen (N ₂ ) at 380 ℃.

In the pixel portion thin film transistor portion I, a drain contact hole for contact with the drain electrode is formed in the protective layer by a seventh mask process.

Subsequently, the step of forming the pixel electrode is performed (step S108).

In this step, as a process corresponding to the pixel portion thin film transistor portion I, indium tin oxide (ITO) having a thickness of about 400 kHz is deposited on the substrate on which the protective layer is formed.

A pixel electrode connected to the drain electrode is formed through the drain contact hole formed in step S107 by an eighth mask process.

According to the liquid crystal display device and the manufacturing method described above, a total of eight mask processes are required.

However, when the number of mask processes used is reduced, the manufacturing process of the liquid crystal display device can be simplified. In addition, as the manufacturing process of the liquid crystal display device becomes simpler, manufacturing cost is reduced.

Accordingly, in manufacturing a liquid crystal display, research on a new manufacturing process that can reduce the number of mask processes used is actively being conducted.

SUMMARY OF THE INVENTION The present invention provides an array substrate for a liquid crystal display device which reduces the number of masks by forming a gate wiring and a pixel electrode in one mask in manufacturing a liquid crystal display device using poly-silicon, and a method of manufacturing the same. There is a purpose.

Another object of the present invention is to provide an array substrate for a liquid crystal display device and a method of manufacturing the same.

In order to achieve the above object, an array substrate for a liquid crystal display device according to the present invention includes a gate electrode, a gate pad, a data pad, and a pixel electrode formed of a transparent conductive electrode material on a substrate and a gate metal layer on the transparent conductive electrode material. A gate wiring formed of this stacked structure; A gate insulating film formed on a portion of the gate electrode and the pixel electrode; A polycrystalline semiconductor layer forming an active region, a source region, and a drain region at a position corresponding to the gate electrode on the gate insulating layer; A protective film covering the polycrystalline semiconductor layer including an active region; And a source electrode orthogonal to the gate wiring and extending from the gate wiring to connect with a source region of the polycrystalline semiconductor layer, and a drain electrode for connecting with a drain region and a pixel electrode of the polycrystalline semiconductor layer. .

The data line is electrically connected to a data pad.

The transparent conductive electrode material may be selected from among Indium-Tin-Oxide, Indium-Zinc-Oxide, and Indium-Tin-Zinc-Oxide. Characterized in that formed by either.

The gate metal layer includes at least one of aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr), tantalum (Ta), aluminum alloy (Al alloy), and tungsten (W) -based metal. Characterized in that formed one.

A capacitor electrode overlapping the pixel electrode and forming a capacitor with the gate insulating layer interposed therebetween is further formed.

In addition, in order to achieve the above object, a method of manufacturing an array substrate for a liquid crystal display device according to the present invention comprises the steps of: laminating a transparent conductive electrode material and a gate metal layer on a substrate; A gate electrode, a gate pad, a data pad, and a pixel electrode formed of the transparent conductive electrode material by using a diffraction exposure method using a diffraction mask having a fully exposed portion and a partially exposed portion on the laminated transparent conductive electrode material and the gate metal layer. Forming a gate wiring having a structure in which the transparent conductive electrode material and the gate metal layer are stacked; Forming a gate insulating film on a portion of the gate electrode and the pixel electrode; Coating amorphous silicon on the gate insulating film and crystallizing it into polycrystalline silicon; Forming a polycrystalline semiconductor layer in the polycrystalline silicon, the active region, the source region, and the drain region, at a position corresponding to the gate electrode; Forming a protective film on the polycrystalline semiconductor layer and covering the active region; And forming a source electrode extending from a data line orthogonal to the gate line and connected to a source region of the polycrystalline semiconductor layer, and a drain electrode connected to a drain region and a pixel electrode of the polycrystalline semiconductor layer. It is done.

Here, in the forming of the source electrode and the drain electrode,

One end extending from the data line is electrically connected to the data pad.

The transparent conductive electrode material may be selected from among Indium-Tin-Oxide, Indium-Zinc-Oxide, and Indium-Tin-Zinc-Oxide. Characterized in that formed by either.

The gate metal layer includes at least one of aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr), tantalum (Ta), aluminum alloy (Al alloy), and tungsten (W) -based metal. Characterized in that formed one.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a schematic plan view of an array substrate for a liquid crystal display according to the present invention, and FIG. 4 is a cross-sectional view taken along line A-A ', B-B', and C-C 'of FIG. 3.

As shown in FIG. 3 and FIG. 4, in the array substrate for a liquid crystal display according to the present invention, a buffer layer 214 is formed on a transparent insulating substrate 200, and the gate wiring has a horizontal direction on the buffer layer 214. 221, a gate electrode 222 extending from the gate wiring 221, and a gate pad 233 are formed.

The data pad 235 made of the same material as the gate pad 233 is formed.

The gate wiring 221 has a double structure of a transparent conductive material and a metal material, and the gate electrode 222, the gate pad 233, and the data pad 235 are made of a transparent conductive material.

A pixel electrode 234 made of a transparent conductive material is formed in the pixel area defined by the gate line 221 and the data line 261 to be formed later.

The transparent conductive material may be any one of indium-tin-oxide, indium-zinc-oxide, and indium-tin-zinc-oxide. It is formed as one.

The metal material is at least one of aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr), tantalum (Ta), aluminum alloy (Al alloy), tungsten (W) -based metals It is characterized by that.

A gate insulating layer 230 is formed on the gate wiring 221 and the gate electrode 222, and a capacitor electrode 275 made of a polycrystalline silicon layer overlaps a portion of the pixel electrode 234 and the gate wiring 221. The semiconductor layer 241 is sequentially formed on the gate electrode 222.

A passivation layer 232 is formed on the semiconductor layer 241 and the capacitor electrode 275, and a source electrode extending from the data line 261 and the data line 261 orthogonal to the gate line 221. 226 and the drain electrode 228 facing the source electrode 226 are formed around the gate electrode 222.

The drain electrode 228 extends to the pixel electrode 234 and is electrically connected to the drain electrode 228.

In this case, the data pad 235 made of a transparent conductive electrode formed in the isolated form is electrically connected to the data line 261.

Hereinafter, a method of manufacturing the array substrate for a liquid crystal display device according to the present invention will be described in more detail.

5 is a plan view and a cross-sectional view illustrating gate patterns and a pixel electrode formed by a first mask process in a method of manufacturing an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 5A is a plan view illustrating a process of manufacturing a first mask using a first mask in an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 5B illustrates A-A 'and B respectively of a data pad, a gate pad, and a thin film transistor in FIG. 5A. It is sectional drawing cut by -B ', C-C'.

5A and 5B, in the array substrate for a liquid crystal display according to the present invention, a buffer layer 214 is formed on a transparent insulating substrate 200, and sputtering or the like is deposited on the buffer layer 214. Through the method, the transparent conductive electrode layer 202a and the gate metal layer 202b composed of metals such as chromium (Cr), aluminum (Al), and molybdenum (Mo) are sequentially deposited.

In addition, gate patterns such as the gate electrode 222, the gate wiring 221, the gate pad 233, and the data pad 235 and the transparent conductive electrode layer may be formed using a photolithography process and an etching process using the first mask. The pixel electrode 234 made of 202a is collectively formed.

In this case, the first mask is formed using a diffraction mask and is formed using a diffraction exposure method.

The gate electrode 222, the gate pad 233, the data pad 235, and the pixel electrode 234 remove the gate metal layer 202b so that the gate electrode 221 is formed of the transparent conductive electrode layer 202a. ) Is a double structure of the transparent conductive electrode layer 202a and the gate metal layer 202b.

That is, as mentioned, a photolithography process is performed using a diffraction mask. The diffraction exposure method using the diffraction mask is composed of a portion through which light passes and a grating, and partially passes light using diffraction and disappearance of light. It is a method of patterning through two etching processes using the diffraction mask which consists of a part to make and a part which completely blocks light.

The gate metal layer 202b of the gate electrode 222, the pixel electrode 234, the gate pad 233, and the data pad 235 is selectively removed using the diffraction exposure method.

As shown in FIG. 5B, a gate insulating film 220 made of an insulating material such as silicon nitride film (SiNx), silicon oxide film (SiO ₂ ), and amorphous silicon (a-si) are sequentially deposited on the gate patterns. do.

Specifically, amorphous silicon (a-Si) is deposited on the substrate 200 on which the gate insulating layer 220 is formed to a thickness of several hundreds of micrometers.

After dehydrogenation, polycrystalline silicon is formed through laser crystallization, and the semiconductor layer 241 is formed using the polycrystalline silicon. Preferably, the amorphous silicon is deposited to about 550 mm thick.

In the laser crystallization step, a laser annealing method of growing an amorphous silicon thin film by applying an excimer laser while heating the substrate temperature to about 250 ° C., and solid phase crystallization formed by long-term heat treatment of amorphous silicon at a high temperature. SPC) and the like, and metal-induced crystallization (MIC), which deposits metal on amorphous silicon to form polycrystalline silicon as a seed.

6A and 6B are plan and cross-sectional views of a substrate for forming a semiconductor layer pattern using second to fourth masks in a method of manufacturing an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIGS. 6A and 6B, a photoresist pattern is formed on the substrate 200 on which the polycrystalline silicon is formed, and the semiconductor layer 241 is doped with n + or p + ions using the photoresist pattern as the second and third masks. Thereafter, activation is performed using a laser or the like so that a part of the semiconductor layer 241 becomes the source / drain regions 241a and 241c.

Although not shown, a low concentration ion implantation region LDD is formed on a part of the polycrystallized semiconductor layer to form a low concentration ion implantation region LDD.

The semiconductor layer 241 and the capacitor electrode 275 are formed by forming a pattern of the semiconductor layer 241 using a photolithography method using a fourth mask.

In this case, the gate insulating layer 220 together with the semiconductor layer 241 pattern is also patterned in the same etching process to expose the gate pad 233 and the data pad 235.

As mentioned above, the semiconductor layer 241 may form an LDD region doped with a low concentration of impurities between the active region 241b and the source and drain regions 241a and 241c doped with a high concentration of impurities.

As shown in FIG. 6B, the passivation layer 232 is deposited on the entire surface of the substrate 200 on which the semiconductor layer 241 is formed, and a dehydrogenation (H) process and an activation process are performed.

Specifically, ions doped in the source and drain regions 241a and 241c of the semiconductor layer 241 are activated through a hydrogen evolution process at 400 ° C to 500 ° C.

FIG. 7 is a cross-sectional view illustrating a substrate formed by a fifth mask process in a method of manufacturing an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 7, the passivation layer 232 formed on the substrate 200 is patterned by a photolithography method using a fifth mask to cover a portion of the semiconductor layer 241 and the capacitor electrode 275. 232).

8A and 8B are plan views and cross-sectional views illustrating a substrate on which source and drain electrodes and data lines are formed in a sixth mask process in a method of manufacturing an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIGS. 8A and 8B, the data metal layer is deposited on the entire surface of the substrate 200 using a deposition method such as sputtering, and a photolithography process and an etching process using a sixth mask are performed to form the data metal layer. By patterning, the source and drain electrodes 226 and 228 and the data wiring 261 are formed.

The data line 261 is formed to be orthogonal to the gate line 221, and the data line 261 overlaps the previously formed data pad 235 to be electrically connected.

A source electrode 226 extending from the data line 261 and a drain electrode 228 facing the source electrode 226 with respect to the gate electrode 222 and spaced apart from each other by a predetermined interval are formed. .

The drain electrode 228 overlaps the pixel electrode 234 and is electrically connected to the drain electrode 228.

In addition, the source electrode 226 is in contact with the source region 241a of the semiconductor layer 241, and the drain electrode 228 is in contact with the drain region 241c of the semiconductor layer 241.

As described above, the liquid crystal display which reduces the mask not only reduces manufacturing cost but also difficult to achieve electrical and rework problems caused by exposure of the metal layer forming the data pad and the gate pad to air. This is solved by forming the pad and the gate pad using a transparent conductive electrode.

FIG. 9 illustrates various embodiments of a data pad and a data wire connection structure in manufacturing an array substrate for a liquid crystal display according to the present invention.

As shown in (a) to (d) of FIG. 9, in the structure of one end of the data wire 261 that is overlapped with the data pad 235 by a predetermined region, the contact characteristics are formed by forming various shapes such as branches. To improve.

Although the present invention has been described in detail through specific embodiments, this is for explaining the present invention in detail, and the array substrate for a liquid crystal display device and a method of manufacturing the same according to the present invention are not limited thereto, and within the technical spirit of the present invention. It is apparent that modifications and improvements are possible by those skilled in the art.

In manufacturing an array substrate for a liquid crystal display device, the transparent conductive electrode layer and the gate metal layer are double stacked and diffraction-exposed when the gate wiring is formed, thereby forming the gate patterns and the pixel electrode collectively to reduce the number of masks. It can reduce the process and improve the production yield.

In addition, according to the present invention, by forming the pad portion made of a transparent conductive electrode material, there is an effect of reducing the padding and defects of the pad portion to improve the reliability of the product.

1A and 1B are cross-sectional views illustrating a structure of a thin film transistor provided in a conventional liquid crystal display device.

FIG. 2 is a process flowchart showing a manufacturing process of a thin film transistor of a pixel portion and a driving circuit portion of a conventional liquid crystal display device; FIG.

3 is a schematic plan view of an array substrate for a liquid crystal display device according to the present invention;

4 is a cross-sectional view taken along line A-A ', B-B', and C-C 'of FIG. 3.

5A and 5B are plan views and cross-sectional views illustrating gate patterns and pixel electrodes formed by a first mask process in a method of manufacturing an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

6A and 6B are plan and cross-sectional views of a substrate for forming a semiconductor layer pattern using second to fourth masks in a method of manufacturing an array substrate for a liquid crystal display device according to an exemplary embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a substrate formed by a fifth mask process in a method of manufacturing an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention. FIG.

8A and 8B are plan and cross-sectional views illustrating a substrate on which source and drain electrodes and data wirings are formed in a sixth mask process in a method of manufacturing an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

9 is a view illustrating various embodiments of a data pad and a data wire connection structure in manufacturing an array substrate for a liquid crystal display according to the present invention.

<Description of Signs of Major Parts of Drawings>

200 substrate 202a transparent conductive electrode layer

202b: gate metal layer 214: buffer layer

220: gate insulating film 221: gate wiring

222: gate electrode 226: source electrode

228: drain electrode 232: protective film

233: gate pad 234: pixel electrode

235 data pad 241 semiconductor layer

241a and 241c: source and drain regions 241b: active region

261 data wiring 275 capacitor electrode

Claims (9)

A gate wiring, a gate pad, a data pad and a pixel electrode formed of a transparent conductive electrode material on a substrate, and a gate wiring formed of a structure in which a gate metal layer is stacked on the transparent conductive electrode material; A gate insulating film formed on a portion of the gate electrode and the pixel electrode; A polycrystalline semiconductor layer forming an active region, a source region, and a drain region at a position corresponding to the gate electrode on the gate insulating layer; A protective film covering the polycrystalline semiconductor layer including an active region; And a source electrode orthogonal to the gate wiring and extending from the gate wiring and connected to the source region of the polycrystalline semiconductor layer, and a drain electrode connected to the drain region and the pixel electrode of the polycrystalline semiconductor layer. Array substrate for liquid crystal display device. The method of claim 1, And the data line is electrically connected to a data pad. The method of claim 1, The transparent conductive electrode material may be selected from among Indium-Tin-Oxide, Indium-Zinc-Oxide, and Indium-Tin-Zinc-Oxide. An array substrate for a liquid crystal display device, characterized in that formed in any one. The method of claim 1, The gate metal layer may include at least one of aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr), tantalum (Ta), aluminum alloy (Al alloy), and tungsten (W) -based metal. An array substrate for a liquid crystal display device, characterized in that formed in any one. The method of claim 1, And a capacitor electrode overlapping the pixel electrode and forming a capacitor with the gate insulating layer interposed therebetween. Laminating a transparent conductive electrode material and a gate metal layer on the substrate in duplicate; A gate electrode, a gate pad, a data pad, and a pixel electrode formed of the transparent conductive electrode material by using a diffraction exposure method using a diffraction mask having a fully exposed portion and a partially exposed portion on the laminated transparent conductive electrode material and the gate metal layer. Forming a gate wiring having a structure in which the transparent conductive electrode material and the gate metal layer are stacked; Forming a gate insulating film on a portion of the gate electrode and the pixel electrode; Coating amorphous silicon on the gate insulating film and crystallizing it into polycrystalline silicon; Forming a polycrystalline semiconductor layer in the polycrystalline silicon, the active region, the source region, and the drain region, at a position corresponding to the gate electrode; Forming a protective film on the polycrystalline semiconductor layer and covering the active region; And forming a source electrode extending from a data line orthogonal to the gate line and connected to a source region of the polycrystalline semiconductor layer, and a drain electrode connected to a drain region and a pixel electrode of the polycrystalline semiconductor layer. The manufacturing method of the array substrate for liquid crystal display devices used. The method of claim 6, In the forming of the source electrode and the drain electrode, And one end extending from the data line is electrically connected to the data pad. The method of claim 6, The transparent conductive electrode material may be selected from among Indium-Tin-Oxide, Indium-Zinc-Oxide, and Indium-Tin-Zinc-Oxide. It is formed in any one, The manufacturing method of the array substrate for liquid crystal display devices. The method of claim 6, The gate metal layer may include at least one of aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr), tantalum (Ta), aluminum alloy (Al alloy), and tungsten (W) -based metal. It is formed in any one, The manufacturing method of the array substrate for liquid crystal display devices.