KR20050093219A - Method for forming an isolation in a semiconductor device - Google Patents

Abstract

A device isolation film formation method of a semiconductor device having a shallow trench device isolation structure is disclosed. A trench is formed on the substrate by etching using the pad oxide layer pattern and the pad nitride layer pattern sequentially stacked on the substrate as an etching mask. After sufficiently filling the trench as an insulating film, dry etching using CHF ₃ , CF, and Ar gas and wet etching using BOE are performed to sufficiently remove the insulating film. Subsequently, chemical mechanical polishing is performed to planarize the insulating film. Thus, the loss of laminated structures is sufficiently reduced.

Description

Method for forming an isolation in a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device having a shallow trench isolation (STI) structure.

Conventional device isolation structures can be formed by performing thermal field oxidation processes such as silicon partial oxidation (LOCOS). According to the silicon partial oxidation method, bird's beak frequently occurs at the end of the field oxide film while oxygen penetrates to the side of the oxide film from the lower part of the nitride film used as the anti-oxidation mask during selective oxidation. As described above, when the buzz beak occurs, the width of the active area is reduced because the length of the field oxide film is extended to the active area by the buzz beak.

Therefore, in the manufacture of semiconductor devices that require a fine structure in recent years, a shallow trench element isolation structure has been spotlighted as an element isolation film. The cell trench isolation structure, that is, the trench isolation layer may be obtained by performing etching to form trenches and planarization such as trench filling and chemical mechanical polishing.

In addition, before performing planarization by chemical mechanical polishing, an etching process for planarization is generally performed in the case of an active region of a large area, that is, an active region of a logic device. At this time, an oxide film for trench filling formed on the logic element region is formed to a thickness slightly lower than that of other regions. Therefore, when an additional etching process for planarization is performed, as shown in FIG. 1, the loss of the oxide film 18 for embedding occurs at the boundary portion where the trench 12 is formed. The loss of the pattern 16 and the pad oxide film pattern 14 also occurs. Reference numeral 10 denotes a substrate.

Here, a method of reducing the etching target in the etching of the oxide film for embedding as part of reducing the loss can be devised. However, reducing the etch target provides a cause for subsequent flattening, i.e., lowering the uniformity of chemical mechanical polishing.

Therefore, in the conventional device isolation layer, a situation in which stacking structures are lost due to etching for planarization frequently occurs. Therefore, there is a problem that the reliability due to the manufacture of the semiconductor device is lowered.

An object of the present invention is to provide a method for easily performing an etching for planarization without affecting the stacked structures in the formation of the device isolation layer.

The device isolation film forming method of the present invention for achieving the above object,

Forming a pad oxide film pattern and a pad nitride film pattern sequentially stacked on the substrate;

Forming a trench in the substrate by performing etching using the pad nitride layer pattern and the pad oxide layer pattern as an etching mask;

Filling the trench sufficiently by stacking an insulating film on the substrate on which the trench is formed, the pad nitride film pattern, and the pad oxide film pattern;

Exposing a portion where the trench is not formed by forming a photoresist pattern on the insulating layer;

Performing dry etching using CHF ₃ , CF, and Ar gas to remove the insulating layer of the exposed region to expose the surface of the pad nitride layer pattern below; And

Performing wet etching using BOE to sufficiently remove the insulating film remaining on the exposed pad nitride film pattern.

Removing the photoresist pattern to expose the insulating layer below; And

And performing a chemical mechanical polishing to planarize the exposed insulating film to the surface height of the pad nitride film pattern.

In addition, it is preferable to select a high density plasma oxide film by sufficiently considering the buried property, and the region where the trench is not formed by forming the photoresist pattern is preferably an active region of a logic element. This is because the active area of the logic device occupies a sufficiently large area, and it is common to perform additional etching for planarization.

As described above, according to the present invention, dry etching and wet etching are performed as an etching process for planarization in the formation of the device isolation layer, particularly the trench device isolation layer. Therefore, the loss of the insulating film for filling in the trench portion and the stacked structures such as the pad nitride film pattern and the pad oxide film pattern below is sufficiently reduced. As such, since the loss of the laminated structures can be sufficiently reduced, damage to the substrate due to the loss can be reduced, and the polishing uniformity in subsequent chemical mechanical polishing can be secured well.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views illustrating a method of forming a device isolation layer according to an embodiment of the present invention.

Referring to FIG. 2A, a pad oxide film and a pad nitride film are sequentially formed on the substrate 20. Subsequently, patterning is performed to form the pad nitride film and the pad oxide film with the pad nitride film pattern 24 and the pad oxide film pattern 22. As described above, the pad nitride film pattern 24 and the pad oxide film pattern 22 are formed to expose the surface of the substrate 20 in the partial region. Subsequently, the exposed substrate 20 is etched by etching using the pad nitride film pattern 24 as a mask. As such, the trench 26 is formed in a portion of the substrate 20 by etching the substrate 20. Then, a high density plasma oxide film having sufficient embedding characteristics as an insulating film 28 is laminated on the substrate 20 having the trench 26 and the pad nitride film pattern 24 so as to be sufficiently embedded in the trench 26. Here, the high density plasma oxide film formed in the active region of the logic element is formed to a thickness slightly lower than other regions due to its characteristics. Therefore, as shown in FIG. 2A, the insulating film 28, that is, the high density plasma oxide film is formed to be somewhat stepped.

2B and 2C, the photoresist pattern 30, which is an etch mask, is formed to perform an etching process for planarization of the insulating layer 28. In this case, the photoresist pattern 30 is formed on a region other than the active region of the logic device. As such, the active region of the logic device is exposed by forming the photoresist pattern 30.

Subsequently, etching is performed using the photoresist pattern 30 as an etching mask to remove the insulating layer 28 in the exposed region. Specifically, dry etching using CHF ₃ , CF, and Ar gas is performed. As described above, the surface of the pad nitride layer pattern 24 is exposed by removing the insulating layer 28 in the exposed region by performing the dry etching. Then, wet etching using a buffered oxide etchant (BOE) is performed. Accordingly, the insulating film 28 remaining on the exposed pad nitride film pattern 24 is sufficiently removed. At this time, since the selectivity of the oxide film and the nitride film is very high, the BOE can remove the oxide film without damaging the nitride film.

As described above, by performing the dry etching and the wet etching continuously, damage to the boundary between the active region and the field region, that is, the region where the trench 26 is formed, may be sufficiently reduced. Therefore, the defects due to the loss can be reduced.

2D to 2F, after removing the photoresist pattern 30, which is the etching mask, chemical mechanical polishing is performed to planarize the insulating layer 28 under the photoresist pattern 30. In this case, the planarization may be performed to a height where the pad nitride film pattern 24 exposed by the etching is formed. In particular, in the polishing, not only the securing of the polishing uniformity but also the damage applied by the etching is removed.

Subsequently, the pad nitride film pattern 24 and the pad oxide film pattern 22 are sequentially removed to obtain the trench structure 32 in which the insulating film 28 is embedded only in the trench 26, as shown in FIG. 2F. . That is, a trench element isolation film is obtained.

According to the present invention, by simultaneously applying dry etching and wet etching as the etching for the planarization performed before the chemical mechanical polishing, the damage of the active area caused by the chemical mechanical polishing can be reduced, and the polishing uniformity can be reduced. We can secure enough. Therefore, there is an effect that the defect removal of the device and the uniformity of the insulating properties can be kept constant.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

1 is a cross-sectional view illustrating a device isolation film formed according to a conventional method.

2A to 2F are cross-sectional views illustrating a method of forming a device isolation layer according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

20: substrate 22: pad oxide film pattern

24: pad nitride film pattern 26: trench

28 insulating film 30 photoresist pattern

32: trench structure

Claims (4)

Forming a pad oxide film pattern and a pad nitride film pattern sequentially stacked on the substrate; Forming a trench in the substrate by performing etching using the pad nitride layer pattern and the pad oxide layer pattern as an etching mask; Filling the trench sufficiently by stacking an insulating film on the substrate on which the trench is formed, the pad nitride film pattern, and the pad oxide film pattern; Exposing a portion where the trench is not formed by forming a photoresist pattern on the insulating layer; Performing dry etching using CHF ₃ , CF, and Ar gas to remove the insulating layer of the exposed region to expose the surface of the pad nitride layer pattern below; And Performing wet etching using BOE to sufficiently remove the insulating film remaining on the exposed pad nitride film pattern. The method of claim 1, wherein the insulating film is a high density plasma oxide film. The method of claim 1, wherein a portion of the region in which the trench exposed by forming the photoresist pattern is not formed is an active region of a logic device. The method of claim 1, further comprising: removing the photoresist pattern to expose an insulating layer below; And And performing a chemical mechanical polishing to planarize the exposed insulating film to the surface height of the pad nitride film pattern.