KR20050092861A - Method for forming contact plug of semiconductor device - Google Patents
Method for forming contact plug of semiconductor device Download PDFInfo
- Publication number
- KR20050092861A KR20050092861A KR1020040017971A KR20040017971A KR20050092861A KR 20050092861 A KR20050092861 A KR 20050092861A KR 1020040017971 A KR1020040017971 A KR 1020040017971A KR 20040017971 A KR20040017971 A KR 20040017971A KR 20050092861 A KR20050092861 A KR 20050092861A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- semiconductor device
- contact hole
- barrier metal
- insulating film
- Prior art date
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Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B28—WORKING CEMENT, CLAY, OR STONE
- B28B—SHAPING CLAY OR OTHER CERAMIC COMPOSITIONS; SHAPING SLAG; SHAPING MIXTURES CONTAINING CEMENTITIOUS MATERIAL, e.g. PLASTER
- B28B5/00—Producing shaped articles from the material in moulds or on moulding surfaces, carried or formed by, in, or on conveyors irrespective of the manner of shaping
- B28B5/06—Producing shaped articles from the material in moulds or on moulding surfaces, carried or formed by, in, or on conveyors irrespective of the manner of shaping in moulds on a turntable
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B28—WORKING CEMENT, CLAY, OR STONE
- B28B—SHAPING CLAY OR OTHER CERAMIC COMPOSITIONS; SHAPING SLAG; SHAPING MIXTURES CONTAINING CEMENTITIOUS MATERIAL, e.g. PLASTER
- B28B11/00—Apparatus or processes for treating or working the shaped or preshaped articles
- B28B11/18—Apparatus or processes for treating or working the shaped or preshaped articles for removing burr
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B28—WORKING CEMENT, CLAY, OR STONE
- B28B—SHAPING CLAY OR OTHER CERAMIC COMPOSITIONS; SHAPING SLAG; SHAPING MIXTURES CONTAINING CEMENTITIOUS MATERIAL, e.g. PLASTER
- B28B7/00—Moulds; Cores; Mandrels
- B28B7/0058—Moulds, cores or mandrels with provisions concerning the elimination of superfluous material; Moulds with burr-removing means provided therein or carried thereby
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B28—WORKING CEMENT, CLAY, OR STONE
- B28B—SHAPING CLAY OR OTHER CERAMIC COMPOSITIONS; SHAPING SLAG; SHAPING MIXTURES CONTAINING CEMENTITIOUS MATERIAL, e.g. PLASTER
- B28B7/00—Moulds; Cores; Mandrels
- B28B7/0064—Moulds characterised by special surfaces for producing a desired surface of a moulded article, e.g. profiled or polished moulding surfaces
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B28—WORKING CEMENT, CLAY, OR STONE
- B28B—SHAPING CLAY OR OTHER CERAMIC COMPOSITIONS; SHAPING SLAG; SHAPING MIXTURES CONTAINING CEMENTITIOUS MATERIAL, e.g. PLASTER
- B28B7/00—Moulds; Cores; Mandrels
- B28B7/02—Moulds with adjustable parts specially for modifying at will the dimensions or form of the moulded article
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- E—FIXED CONSTRUCTIONS
- E01—CONSTRUCTION OF ROADS, RAILWAYS, OR BRIDGES
- E01C—CONSTRUCTION OF, OR SURFACES FOR, ROADS, SPORTS GROUNDS, OR THE LIKE; MACHINES OR AUXILIARY TOOLS FOR CONSTRUCTION OR REPAIR
- E01C15/00—Pavings specially adapted for footpaths, sidewalks or cycle tracks
-
- E—FIXED CONSTRUCTIONS
- E01—CONSTRUCTION OF ROADS, RAILWAYS, OR BRIDGES
- E01C—CONSTRUCTION OF, OR SURFACES FOR, ROADS, SPORTS GROUNDS, OR THE LIKE; MACHINES OR AUXILIARY TOOLS FOR CONSTRUCTION OR REPAIR
- E01C5/00—Pavings made of prefabricated single units
- E01C5/06—Pavings made of prefabricated single units made of units with cement or like binders
Abstract
본 발명에 따른 반도체 소자의 콘택 플러그 형성 방법은, 반도체 기판의 소정영역을 노출시키는 콘택홀을 구비한 절연막 패턴을 형성하는 단계와, 상기 절연막 패턴에 대하여 300℃이상의 온도에서 디가스 공정을 수행하는 단계와, 콘택홀 표면에 배리어 메탈을 증착하는 단계와, 상기 콘택홀을 매립하는 텅스텐 플러그를 형성하는 단계를 포함하는 것을 특징으로 하고, 콘택홀 매립시 배리어 메탈의 증착전에 300℃이상의 디가스 공정을 통하여 배리어 메탈층 증착시 절연막으로 부터의 아웃가싱을 방지함으로써 배리어 메탈의 증착 특성을 향상시켜 텅스텐 플러그의 매립 특성을 향상시키며 궁극적으로 콘택의 저항을 감소시킬 수 있는 반도체 소자의 콘택 플러그 형성 방법을 제공하는 것을 목적으로 한다. A method of forming a contact plug of a semiconductor device according to the present invention includes forming an insulating film pattern having a contact hole exposing a predetermined region of a semiconductor substrate, and performing a degas process on the insulating film pattern at a temperature of 300 ° C. or higher. And depositing a barrier metal on the surface of the contact hole, and forming a tungsten plug filling the contact hole. The method for forming a contact plug of a semiconductor device capable of improving the buried property of the tungsten plug by ultimately improving the deposition property of the barrier metal by preventing outgassing from the insulating layer when the barrier metal layer is deposited through It aims to provide.
Description
본 발명은 따른 반도체 소자의 콘택 플러그 형성 방법에 관한 것으로, 300℃이상의 디가스 공정을 통하여 배리어 메탈 증착시 절연층으로 부터의 아웃가싱을 방지함으로써 배리어 메탈의 증착 특성을 향상시켜 텅스텐 플러그의 매립 특성을 향상시키며 궁극적으로 콘택의 저항을 감소시킬 수 있는 반도체 소자의 콘택 플러그 형성 방법에 관한 것이다.The present invention relates to a method of forming a contact plug of a semiconductor device according to the present invention. The present invention relates to a method for forming a contact plug of a semiconductor device capable of improving the resistance and ultimately reducing the contact resistance.
도시되지는 않았으나, 종래기술을 설명하면 다음과 같다. Although not shown, the prior art will be described below.
반도체 기판에 절연막을 형성한다. 상기 절연막을 식각하여 콘택홀을 형성하고, 콘택홀을 포함한 전체 표면에 배리어 메탈층을 증착한다. 여기서, 상기 배리어 메탈층의 증착전에 200℃의 온도에서 40초 정도의 디가스 공정을 진행한다. An insulating film is formed on a semiconductor substrate. The insulating layer is etched to form a contact hole, and a barrier metal layer is deposited on the entire surface including the contact hole. Here, a degas process of about 40 seconds is performed at a temperature of 200 ° C. before deposition of the barrier metal layer.
상기 절연막은 PSG, BPSG 및 PE-TEOS 중 하나를 선택하여 증착한다. 상기 절연막은 메탈층 증착이 진행되는 300∼400℃정도의 온도에서 아웃가싱되는 수분이나 수소 성분이 많이 존재하기 때문에 배리어 메탈층의 증착 특성이 취약해지고, 텅스텐의 매립 특성도 악화되어 콘택의 저항이 증가되는 문제점이 있다. The insulating film is deposited by selecting one of PSG, BPSG and PE-TEOS. Since the insulating layer contains a lot of water or hydrogen components outgassed at a temperature of about 300 to 400 ° C. at which the metal layer is deposited, the deposition property of the barrier metal layer is weak, and the buried property of tungsten is also deteriorated, resulting in poor contact resistance. There is an increasing problem.
상기 문제점을 해결하기 위하여, 콘택홀 매립시 배리어 메탈층의 증착 전에 300℃이상의 디가스 공정을 통하여 배리어 메탈층 증착시 절연막으로 부터의 아웃가싱을 방지함으로써 배리어 메탈층의 증착 특성을 향상시켜 텅스텐 플러그의 매립 특성을 향상시키며 궁극적으로 콘택의 저항을 감소시킬 수 있는 반도체 소자의 콘택 플러그 형성 방법을 제공하는 것을 그 목적으로 한다. In order to solve the above problems, the deposition characteristics of the barrier metal layer are improved by preventing outgassing from the insulating layer during the deposition of the barrier metal layer through a degas process of 300 ° C. or more prior to the deposition of the barrier metal layer when the contact hole is buried. It is an object of the present invention to provide a method for forming a contact plug of a semiconductor device capable of improving the buried property of the semiconductor device and ultimately reducing the contact resistance.
본 발명에 따른 반도체 소자의 콘택 플러그 형성 방법은, 반도체 기판의 소정영역을 노출시키는 콘택홀을 구비한 절연막 패턴을 형성하는 단계와, 상기 절연막 패턴에 대하여 300℃이상의 온도에서 디가스 공정을 수행하는 단계와, 콘택홀 표면에 배리어 메탈층을 증착하는 단계와, 상기 콘택홀을 매립하는 텅스텐 플러그를 형성하는 단계를 포함하는 것을 특징으로 한다.A method of forming a contact plug of a semiconductor device according to the present invention includes forming an insulating film pattern having a contact hole exposing a predetermined region of a semiconductor substrate, and performing a degas process on the insulating film pattern at a temperature of 300 ° C. or higher. And depositing a barrier metal layer on the surface of the contact hole, and forming a tungsten plug filling the contact hole.
이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다. Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.
도 1a 내지 1c는 본 발명에 따른 반도체 소자의 콘택 플러그 형성 방법을 도시한 단면도이다. 1A to 1C are cross-sectional views illustrating a method for forming a contact plug of a semiconductor device according to the present invention.
도 1a를 참조하면, 반도체 기판(10) 상부에 절연막(20)을 형성한다. Referring to FIG. 1A, an insulating film 20 is formed on the semiconductor substrate 10.
여기서, 절연막(20)은 PSG, BPSG 및 PE-TEOS 중 선택된 어느 하나인 것이 바람직하다. Here, the insulating film 20 is preferably any one selected from PSG, BPSG and PE-TEOS.
도 1b를 참조하면, 절연막(20)을 식각하여 반도체 기판(10)의 소정영역을 노출시키는 콘택홀(40)을 구비한 절연막 패턴(30)을 형성한다. Referring to FIG. 1B, the insulating film 20 is etched to form an insulating film pattern 30 having a contact hole 40 exposing a predetermined region of the semiconductor substrate 10.
다음에는, 절연막 패턴(30)에 대하여 300℃이상의 온도에서 300초이상 디가스 공정을 수행한다. Next, a degas process is performed on the insulating film pattern 30 at a temperature of 300 ° C. or higher for at least 300 seconds.
도 1c를 참조하면, 콘택홀(40)을 포함한 전체 표면에 배리어 메탈층(50)을 증착한다. Referring to FIG. 1C, the barrier metal layer 50 is deposited on the entire surface including the contact hole 40.
다음에는, 콘택홀(40)을 매립하는 텅스텐 플러그(미도시)를 형성한다. Next, a tungsten plug (not shown) filling the contact hole 40 is formed.
도 2는 본 발명에 따른 반도체 소자의 콘택 플러그 형성시 배리어 메탈층(50) 증착 공정 온도에 따른 아웃가스의 양의 변화를 도시한 그래프이다. 2 is a graph illustrating a change in the amount of outgas according to the deposition process temperature of the barrier metal layer 50 when forming the contact plug of the semiconductor device according to the present invention.
도 2를 참조하면, 절연막 패턴(30)은 PSG, BPSG 또는 PE-TEOS인데, 절연막 패턴(30)의 종류에 따라 아웃가싱량도 각각 다름을 알 수 있다. 여기서, 배리어 메탈층(50) 증착 공정의 온도가 300∼400℃에서 아웃가싱량이 감소함을 나타낸다. 아웃가싱되는 수분 또는 수소 성분이 감소됨으로써 배리어 메탈층(50)의 증착 특성이 향상되며, 텅스텐 플러그 매립 특성도 향상된다. Referring to FIG. 2, the insulating film pattern 30 may be PSG, BPSG, or PE-TEOS, and the outgassing amount may also be different depending on the type of the insulating film pattern 30. Here, the outgassing amount is decreased when the temperature of the barrier metal layer 50 deposition process is 300 to 400 ° C. By reducing the outgassing moisture or hydrogen content, the deposition property of the barrier metal layer 50 is improved, and the tungsten plug embedding property is also improved.
궁극적으로 콘택의 저항을 감소시킬 수 있는 반도체 소자의 콘택 플러그 형성 방법을 제공하는 것을 목적으로 한다. It is an object of the present invention to provide a method for forming a contact plug of a semiconductor device that can ultimately reduce the resistance of a contact.
본 발명에 따른 반도체 소자의 콘택 플러그 형성 방법은 콘택홀 매립시 배리어 메탈층의 증착전에 300℃이상의 디가스 공정을 통하여 배리어 메탈층 증착시 절연막으로부터의 아웃가싱을 방지함으로써 배리어 메탈층의 증착 특성을 향상시켜 텅스텐 플러그의 매립 특성을 향상시키며 궁극적으로 콘택의 저항을 감소시킬 수 있는 효과가 있다. The method for forming a contact plug of a semiconductor device according to the present invention prevents outgassing from an insulating layer during deposition of a barrier metal layer through a degas process of 300 ° C. or more prior to deposition of the barrier metal layer at the time of contact hole filling. This improves the buried properties of the tungsten plug and ultimately reduces the contact resistance.
도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 콘택 플러그 형성 방법을 도시한 단면도.1A to 1C are cross-sectional views illustrating a method for forming a contact plug of a semiconductor device according to the present invention.
도 2는 본 발명에 따른 반도체 소자의 콘택 플러그 형성시 배리어 메탈 증착 공정 온도에 따른 아웃가스의 양의 변화를 도시한 그래프.2 is a graph showing a change in the amount of outgas according to the barrier metal deposition process temperature when forming a contact plug of a semiconductor device according to the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
10 : 반도체 기판 20 : 절연막10 semiconductor substrate 20 insulating film
30 : 절연막 패턴 40 : 콘택홀 30 insulating film pattern 40 contact hole
50 : 배리어 메탈층50: barrier metal layer
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KR1020040017971A KR20050092861A (en) | 2004-03-17 | 2004-03-17 | Method for forming contact plug of semiconductor device |
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KR1020040017971A KR20050092861A (en) | 2004-03-17 | 2004-03-17 | Method for forming contact plug of semiconductor device |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9376541B2 (en) | 2013-10-10 | 2016-06-28 | Samsung Electronics Co., Ltd. | Non-conductive film and non-conductive paste including zinc particles, semiconductor package including the same, and method of manufacturing the semiconductor package |
US10128168B2 (en) | 2013-11-18 | 2018-11-13 | Samsung Electronics Co., Ltd. | Integrated circuit device including through-silicon via structure and method of manufacturing the same |
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2004
- 2004-03-17 KR KR1020040017971A patent/KR20050092861A/en not_active Application Discontinuation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9376541B2 (en) | 2013-10-10 | 2016-06-28 | Samsung Electronics Co., Ltd. | Non-conductive film and non-conductive paste including zinc particles, semiconductor package including the same, and method of manufacturing the semiconductor package |
US10128168B2 (en) | 2013-11-18 | 2018-11-13 | Samsung Electronics Co., Ltd. | Integrated circuit device including through-silicon via structure and method of manufacturing the same |
US10777487B2 (en) | 2013-11-18 | 2020-09-15 | Samsung Electronics Co., Ltd. | Integrated circuit device including through-silicon via structure and method of manufacturing the same |
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