KR20050079546A - Method of manufacturing capacitor in semiconductor device - Google Patents
Method of manufacturing capacitor in semiconductor device Download PDFInfo
- Publication number
- KR20050079546A KR20050079546A KR1020040008034A KR20040008034A KR20050079546A KR 20050079546 A KR20050079546 A KR 20050079546A KR 1020040008034 A KR1020040008034 A KR 1020040008034A KR 20040008034 A KR20040008034 A KR 20040008034A KR 20050079546 A KR20050079546 A KR 20050079546A
- Authority
- KR
- South Korea
- Prior art keywords
- interlayer insulating
- metal
- film
- insulating film
- forming
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 반도체 소자의 커패시터 제조방법에 관한 것으로, 본 발명의 사상은 금속배선이 구비된 제1 층간 절연막 상에 하부전극용 제1 금속막, 유전막 및 상부전극용 제2 금속막을 순차적으로 형성한 후 패터닝하여 커패시터 패턴을 형성하는 단계, 상기 커패시터 패턴을 포함한 결과물 전면에 제2 층간 절연막을 형성하는 단계, 상기 제2 층간 절연막이 형성된 결과물 전면에 평탄화 공정을 수행하는 단계, 상기 평탄화 공정이 완료된 제2 층간 절연막을 패터닝하여 상기 금속배선을 노출하는 비아홀을 형성하는 단계, 및 상기 비아홀에 금속물질을 형성하여 비아를 형성하는 단계를 포함한다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device. The idea of the present invention is to sequentially form a first metal film for a lower electrode, a dielectric film, and a second metal film for an upper electrode on a first interlayer insulating film having metal wiring. And patterning the capacitor pattern to form a capacitor pattern, forming a second interlayer insulating film on the entire surface of the product including the capacitor pattern, performing a planarization process on the entire surface of the resultant product on which the second interlayer insulating film is formed, and completing the planarization process. Patterning a second interlayer insulating film to form a via hole exposing the metal wiring; and forming a via by forming a metal material in the via hole.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 더욱 상세하게는 반도체 소자의 커패시터 제조방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a capacitor of a semiconductor device.
일반적으로 반도체 소자의 커패시터 구조로는 MIM(Metal-Insulator-Metal), PIP(Polysilicon- Insulator- Polysilicon), PIS(Polysilicon- Insulator- Silicon), MIS(Metal-Insulator-Silicon), MIP(Metal-Insulator-Polysilicon)등 다양한 구조들이 사용되고 있다. In general, capacitor structures of semiconductor devices include metal-insulator-metal (MIM), polysilicon-insulator-polysilicon (PIP), polysilicon-insulator-silicon (PIS), metal-insulator-silicon (MIS), and metal-insulator (MIP). Various structures such as polysilicon are used.
상기 커패시터 중 MIM 구조를 커패시터로 형성하는 공정은, 금속배선이 형성된 제1 층간 절연막 상에 MIM 커패시터 패턴을 형성하고, 이 MIM 커패시터 패턴이 형성된 결과물 전면에 제2 층간 절연막을 형성한다. 이 제2 층간 절연막에 다마신 공정을 수행하여 비아홀을 형성하고, 상기 결과물 전면에 구리물질을 형성하여 비아홀에만 구리물질이 형성되도록 CMP 공정과 같은 평탄화 공정을 수행하여 비아를 형성한다. In the process of forming a MIM structure among the capacitors as a capacitor, a MIM capacitor pattern is formed on the first interlayer insulating film on which metal wiring is formed, and a second interlayer insulating film is formed on the entire surface of the resultant product on which the MIM capacitor pattern is formed. A via hole is formed by performing a damascene process on the second interlayer insulating layer, and a copper material is formed on the entire surface of the resultant to perform a planarization process such as a CMP process so that only a via material is formed.
이때 상기 제2 층간 절연막은 상기 MIM 커패시터 패턴에 의해 단차를 가지게 되는 데, 이 단차로 인해 이후 상기 비아홀에만 구리물질이 증착되도록 하기 위해 수행하는 CMP 공정시 평탄화의 균일성이 저하되어 금속잔류물이 잔존하게 되는 등의 문제가 발생한다. In this case, the second interlayer insulating layer has a step due to the MIM capacitor pattern, and due to the step, the uniformity of the planarization during the CMP process performed so that the copper material is deposited only in the via hole is reduced, resulting in a metal residue. Problems such as remaining.
상술한 문제점을 해결하기 위한 본 발명의 목적은 MIM 커패시터 형성방법에 있어서, 평탄화의 균일성을 향상시킬 수 있도록 하는 반도체 소자의 커패시터 제조방법을 제공함에 있다. An object of the present invention for solving the above problems is to provide a capacitor manufacturing method of a semiconductor device to improve the uniformity of planarization in the MIM capacitor forming method.
상술한 목적을 달성하기 위한 본 발명의 사상은 금속배선이 구비된 제1 층간 절연막 상에 하부전극용 제1 금속막, 유전막 및 상부전극용 제2 금속막을 순차적으로 형성한 후 패터닝하여 커패시터 패턴을 형성하는 단계, 상기 커패시터 패턴을 포함한 결과물 전면에 제2 층간 절연막을 형성하는 단계, 상기 제2 층간 절연막이 형성된 결과물 전면에 평탄화 공정을 수행하는 단계, 상기 평탄화 공정이 완료된 제2 층간 절연막을 패터닝하여 상기 금속배선을 노출하는 비아홀을 형성하는 단계, 및 상기 비아홀에 금속물질을 형성하여 비아를 형성하는 단계를 포함한다. The idea of the present invention for achieving the above object is to form a capacitor pattern by sequentially forming and patterning the first metal film for the lower electrode, the dielectric film and the second metal film for the upper electrode on the first interlayer insulating film provided with metal wiring. Forming a second interlayer insulating film on the entire surface of the resultant including the capacitor pattern, performing a planarization process on the entire surface of the resultant on which the second interlayer insulating film is formed, and patterning the second interlayer insulating film on which the planarization process is completed Forming a via hole exposing the metal wiring; and forming a via by forming a metal material in the via hole.
상기 비아홀에 형성되는 금속물질은 구리인 것이 바람직하다. The metal material formed in the via hole is preferably copper.
이하, 첨부 도면을 참조하여 본 발명의 실시 예를 상세히 설명한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있지만 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안 된다. 본 발명의 실시예들은 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해 제공되어지는 것이다. 또한 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다 또는 접촉하고 있다 라고 기재되는 경우에, 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제 3의 막이 개재되어질 수도 있다. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, but the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. In addition, when a film is described as being on or in contact with another film or semiconductor substrate, the film may be in direct contact with the other film or semiconductor substrate, or a third film is interposed therebetween. It may be done.
도 1을 참조하면, 금속배선(12)이 구비된 제1 층간 절연막(10) 상에 하부전극용 제1 금속막(14), 유전막(16) 및 상부전극용 제2 금속막(18)을 순차적으로 형성한다. 이어서, 상기 상부전극용 제2 금속막 상에 커패시터 형성용 포토레지스트 패턴을 형성한 후 이를 식각 마스크로 상부전극용 제2 금속막, 유전막, 하부전극용 제1 금속막을 순차적으로 식각하여 MIM 커패시터 패턴(C. P)을 형성한다. 이어서, 상기 MIM 커패시터 패턴(C.P)이 형성된 결과물 전면에 층간 절연막(20)을 형성한다. Referring to FIG. 1, the first metal film 14 for the lower electrode, the dielectric film 16, and the second metal film 18 for the upper electrode are formed on the first interlayer insulating film 10 having the metal wiring 12. Form sequentially. Subsequently, after forming a photoresist pattern for forming a capacitor on the second metal film for the upper electrode, the second metal film for the upper electrode, the dielectric film, and the first metal film for the lower electrode are sequentially etched using the etching mask to sequentially MIM capacitor pattern. (C. P). Subsequently, an interlayer insulating layer 20 is formed on the entire surface of the resultant product in which the MIM capacitor pattern C.P is formed.
이 층간 절연막(20)에는 단차가 발생(A)하는 데, 이 단차는 하부의 MIM 커패시터 패턴(C.P)이 형성된 영역과 MIM 커패시터 패턴이 형성되지 않은 영역에 의해 발생한다. A step (A) occurs in the interlayer insulating film 20, which is caused by a region where the lower MIM capacitor pattern C.P is formed and a region where the MIM capacitor pattern is not formed.
도 2를 참조하면, 상기 층간 절연막(20)이 형성된 결과물 전면에 CMP 공정과 같은 평탄화 공정을 수행한다. 상기 CMP 공정과 같은 평탄화 공정으로 인해 상기 층간 절연막에 발생된 단차(A)를 제거할 수 있다. Referring to FIG. 2, a planarization process such as a CMP process is performed on the entire surface of the resultant in which the interlayer insulating layer 20 is formed. The step A generated in the interlayer insulating layer may be removed due to the planarization process such as the CMP process.
도 3을 참조하면, 상기 단차가 제거된 층간 절연막(20)에 다마신 공정을 수행하여 비아홀을 형성한다. 즉, 상기 층간 절연막(20)상에 비아홀을 정의하는 포토레지스트 패턴(미도시)을 형성하고, 이를 식각 마스크로 층간 절연막(20)을 식각하여 하부의 제1 금속배선을 노출하는 비아홀을 형성한다. 이어서, 상기 형성된 비아홀의 측벽에 이후 형성되는 금속물질의 확산을 방지하는 확산 방지막(22)을 형성하고, 상기 확산 방지막(22)이 형성된 결과물 전면에 금속물질을 증착하고 CMP 공정과 같은 평탄화 공정을 수행하여 비아홀(24)의 형성을 완료한다. Referring to FIG. 3, a via hole is formed by performing a damascene process on the interlayer insulating layer 20 from which the step is removed. That is, a photoresist pattern (not shown) defining a via hole is formed on the interlayer insulating film 20, and the interlayer insulating film 20 is etched using an etching mask to form a via hole exposing a lower first metal wiring. . Subsequently, a diffusion barrier 22 is formed on the sidewall of the formed via hole to prevent diffusion of the metal material to be subsequently formed, and a metal material is deposited on the entire surface of the resultant on which the diffusion barrier 22 is formed, and a planarization process such as a CMP process is performed. Performing the formation of the via hole 24 is completed.
상기 비아홀 내에 형성되는 금속물질은 구리인 것이 바람직하다. The metal material formed in the via hole is preferably copper.
본 발명에 의하면, MIM 커패시터 패턴 형성시 발생된 단차를 평탄화 공정으로 인해 제거함으로써, 평탄화에 대한 균일성을 확보하면서 동시에 금속 잔류물 유발을 방지하여 커패시터의 특성을 향상시킬 수 있다. According to the present invention, by removing the step generated during the MIM capacitor pattern formation by the planarization process, it is possible to secure the uniformity of the planarization and at the same time prevent the occurrence of metal residues to improve the characteristics of the capacitor.
이상에서 살펴본 바와 같이 본 발명에 의하면, MIM 커패시터 패턴 형성시 발생된 단차를 평탄화 공정으로 인해 제거함으로써, 평탄화에 대한 균일성을 확보하여 금속 잔류물 유발을 방지하여 커패시터의 특성을 향상시킬 수 있는 효과가 있다. As described above, according to the present invention, by removing the step difference generated when forming the MIM capacitor pattern by the planarization process, it is possible to improve the characteristics of the capacitor by ensuring the uniformity of the planarization to prevent the occurrence of metal residues There is.
본 발명은 구체적인 실시 예에 대해서만 상세히 설명하였지만 본 발명의 기술적 사상의 범위 내에서 변형이나 변경할 수 있음은 본 발명이 속하는 분야의 당업자에게는 명백한 것이며, 그러한 변형이나 변경은 본 발명의 특허청구범위에 속한다 할 것이다.Although the present invention has been described in detail only with respect to specific embodiments, it is apparent to those skilled in the art that modifications or changes can be made within the scope of the technical idea of the present invention, and such modifications or changes belong to the claims of the present invention. something to do.
도 1 내지 도 3은 본 발명에 따른 반도체소자의 커패시터 제조방법을 설명하기 위한 단면도들이다. 1 to 3 are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10: 제1 층간 절연막 12: 제1 금속배선10: first interlayer insulating film 12: first metal wiring
14: 제1 금속막 16: 유전막14: first metal film 16: dielectric film
18: 제2 금속막 20: 제2 층간 절연막18: second metal film 20: second interlayer insulating film
22: 확산방지막 24: 비아 22: diffusion barrier 24: via
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020040008034A KR20050079546A (en) | 2004-02-06 | 2004-02-06 | Method of manufacturing capacitor in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020040008034A KR20050079546A (en) | 2004-02-06 | 2004-02-06 | Method of manufacturing capacitor in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20050079546A true KR20050079546A (en) | 2005-08-10 |
Family
ID=37266465
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020040008034A KR20050079546A (en) | 2004-02-06 | 2004-02-06 | Method of manufacturing capacitor in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20050079546A (en) |
-
2004
- 2004-02-06 KR KR1020040008034A patent/KR20050079546A/en not_active Application Discontinuation
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7109090B1 (en) | Pyramid-shaped capacitor structure | |
| KR100869749B1 (en) | Metal insulator metal capacitor and method for manufacture thereof | |
| KR100482029B1 (en) | Method for forming mim capacitor | |
| US7846808B2 (en) | Method for manufacturing a semiconductor capacitor | |
| US20080157277A1 (en) | Mim capacitor | |
| KR100477541B1 (en) | Method for forming mim capacitor | |
| KR100482025B1 (en) | Method of Manufacturing Semiconductor Device | |
| KR100639000B1 (en) | Method of fabricating metal-insulator-metal capacitor | |
| KR20050079546A (en) | Method of manufacturing capacitor in semiconductor device | |
| KR100929626B1 (en) | MM capacitor formation method | |
| KR20060072232A (en) | Method of fabricating mim(metal-insulator-metal) capacitor | |
| KR100964116B1 (en) | Method for fabricating of semiconductor device | |
| KR100678298B1 (en) | Method of fabricating metal-insulator-metal capacitor having trench structure | |
| KR101057753B1 (en) | Method of manufacturing semiconductor device | |
| KR100607662B1 (en) | Method for forming metal insulator metal capacitor | |
| KR100638984B1 (en) | Method of fabricating metal-insulator-metal capacitor | |
| KR100866114B1 (en) | Method for forming inverse structure MIM capacitor | |
| KR100718456B1 (en) | Semiconductor device and method for manufacturing the same | |
| KR20090119168A (en) | Method of manufacturing a capacitor of a semiconductor device | |
| KR100641984B1 (en) | Method of fabricating MIMMetal-Insulator-Metal capacitor | |
| KR100842471B1 (en) | A method for forming a mim capacitor in a semiconductor device | |
| KR100971325B1 (en) | Metal-insulator-metal capacitor manufacturing method for semiconductor device | |
| KR100579862B1 (en) | Metal-insulator-metal capacitor and method of fabricating the same | |
| KR100688724B1 (en) | Method for manufacturing high volume mim capacitor | |
| KR101091742B1 (en) | Method of manufacturing capacitor in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| N231 | Notification of change of applicant | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |