KR20050070800A - Method for fabricating of non-volatile memory device - Google Patents

Abstract

The present invention relates to a method of manufacturing a nonvolatile memory device, and more particularly, to a nonvolatile memory device having excellent device isolation characteristics with a minimum area (2F ² ) without using a conventional SAS process or SA-STI process. It relates to a manufacturing method.

According to another aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, the method including: forming and panning a buffer oxide film and a buffer nitride film on an entire surface of a semiconductor substrate; Forming a sidewall floating gate on sidewalls of the patterned buffer nitride film; Depositing and patterning polysilicon on the substrate to form a polysilicon gate; Removing the buffer nitride film; Forming a first sidewall spacer on sidewalls of the floating gate and the polysilicon gate; Implanting impurity ions into the substrate to form a common source / drain region; Depositing and planarizing an insulating film on the substrate to gap fill between polysilicon gates; Depositing polysilicon for word lines on the substrate; Patterning the substrate for the word line polysilicon, the polysilicon gate, and the substrate to form an STI and forming a second sidewall spacer on sidewalls of the word line and the polysilicon gate; It is achieved by a method for manufacturing a nonvolatile memory device, characterized in that.

Therefore, the method of manufacturing a nonvolatile memory device of the present invention allows the STI to be selectively formed when forming the word line without separately performing the STI forming process, and thus the device isolation characteristics between the word line and the word line and between the common source and the common drain. By ensuring device isolation, NOR flash cells occupy less space without using SAS or SA-STI processes.

Description

Method for fabricating of non-volatile memory device

The present invention relates to a method for manufacturing a nonvolatile memory device, and more particularly, to minimize the area (2F ² ) without using a conventional Self-Aligned Source (SAS) process or a Self-Aligned STI (SA-STI) process. The present invention relates to a method of manufacturing a nonvolatile memory device having excellent device isolation characteristics.

In general, semiconductor memory devices are classified into volatile memory and non-volatile memory. Most of volatile memory is occupied by RAM such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), and data can be input and stored when power is applied, but data cannot be saved because of volatilization when power is removed. Has On the other hand, nonvolatile memory, which is mostly occupied by ROM (Read Only Memory), is characterized in that data is preserved even when power is not applied.

At present, in terms of process technology, a nonvolatile memory device is classified into a floating gate series and a metal insulator semiconductor (MIS) series in which two or more dielectric layers are stacked in two or three layers.

Floating gate-type memory devices realize potential memory characteristics using potential wells, and are a simple stack-type EPROM (EPROM Tunnel Oxide) structure that is currently widely used as flash electrically erasable programmable read only memory (EEPROM). And a split gate structure in which one transistor includes two transistors.

On the other hand, the MIS series performs a memory function by using traps present at the dielectric bulk, the dielectric film-dielectric film interface, and the dielectric film-semiconductor interface. A typical example is the MONOS / SONOS (Metal / Silicon ONO Semiconductor) structure, which is mainly used as a flash EEPROM.

A method of manufacturing a flash memory cell of the prior art will be briefly described with reference to FIG. 1. The gate oxide film 12 is formed on the semiconductor substrate 10 on which the device isolation film 11 is formed, and the first polysilicon layer 13 is formed thereon. Is used as a floating gate. A dielectric layer 15 and a second polysilicon layer 16 are formed on the floating gate 13 to use the second polysilicon layer 16 as a control gate. The metal layer 17 and the nitride film 18 are formed on the control gate 16 and patterned in a cell structure to form a flash memory cell.

In the current NOR flash memory manufacturing process, the SAS process or SA-STI process is mainly used to minimize the NOR flash unit cell area. In addition, even if the SAS process, the SA-STI process, or both processes are used, bit contact must be formed so that the minimum area (4F ² ) of the NAND flash cell mainly used for data flash memory is not reduced. In addition, in the case of the 2-bit sidewall floating gate device to be used in the present invention, since each contact and source must be formed in the source / drain, an additional area is required to form each bit line, thereby minimizing the area. To do this, a cell structure without bit contact must be formed.

Accordingly, the present invention is to solve the above problems of the prior art, it is possible to implement a NOR flash cell having excellent device isolation characteristics while having a minimum area (2F ² ) without using a SAS process or SA-STI process. It is an object of the present invention to provide a method of manufacturing a nonvolatile memory device.

According to another aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, the method including: forming and panning a buffer oxide film and a buffer nitride film on an entire surface of a semiconductor substrate; Forming a sidewall floating gate on sidewalls of the patterned buffer nitride film; Depositing and patterning polysilicon on the substrate to form a polysilicon gate; Removing the buffer nitride film; Forming a first sidewall spacer on sidewalls of the floating gate and the polysilicon gate; Implanting impurity ions into the substrate to form a common source / drain region; Depositing and planarizing an insulating film on the substrate to gap fill between polysilicon gates; Depositing polysilicon for word lines on the substrate; Patterning the substrate for the word line polysilicon, the polysilicon gate, and the substrate to form an STI and forming a second sidewall spacer on sidewalls of the word line and the polysilicon gate; It is achieved by a method for manufacturing a nonvolatile memory device, characterized in that.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

2 is a view comparing the area of a NOR flash unit cell having a conventional bit contact with the area of a unit cell of a 2-bit sidewall floating gate nonvolatile memory device having no bit contact implemented by the manufacturing process of the present invention.

a shows the area of the NOR flash unit cell with bit contact when neither SAS process nor SA-STI process is used, and occupies approximately 10.5F ² .

b represents the area of the NOR flash unit cell with bit contact when the SAS process is used but the SA-STI process is not used, and occupies approximately 9F ² . Therefore, using the SAS process reduces the cell area by approximately 15% compared to 2a.

c represents the area of the NOR flash unit cell having a bit contact when the SAS process and the SA-STI process are used, and occupies approximately 6F ² . Therefore, by using both SAS and SA-STI processes, the cell area can be reduced by about 43% compared to 2a and by about 33% compared to 2b.

d represents the area of a 2-bit sidewall floating gate NOR flash unit cell without bit contact according to the present invention, and occupies an area of approximately 2F ² . This is about half the number of NAND flash unit cells using the conventional SA-STI process and can reduce cell area by approximately 81% compared to 3a, cell area by 78% compared to 3b, and roughly compared to 3c. The cell area can be reduced by 67%.

3 illustrates a cell array layout of a nonvolatile memory device according to the present invention. Sectional views in the directions A-A ', B-B', C-C ', and D-D' of FIG. 3 will be described below in the process sequence in FIG. 4.

4A to 4H are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to the present invention.

First, as shown in FIG. 4A, a deep N well 502 and a P well 503 are formed on an entire surface of the P-type semiconductor substrate 501 by an ion implantation process. At this time, when forming the P well, threshold voltage adjustment and ion implantation for preventing punch-through are performed together. Subsequently, a first buffer oxide layer 504 is grown or deposited on the substrate, and a buffer nitride layer 505 is deposited on the first buffer oxide layer. Instead of forming the first buffer oxide film, an oxide film used in a well forming ion implantation process may be used. Next, the buffer nitride film and the buffer oxide film are patterned in the word line direction. Subsequently, a tunnel oxide layer is formed on the exposed silicon substrate after the patterning. The first buffer oxide film is preferably grown or deposited in the range of 50 kV to 300 kV, and the buffer nitride film is preferably deposited in the range of 100 kV to 2000 kV. The tunnel oxide film is preferably grown or deposited in the range of 30 kV to 300 kV.

Next, as shown in FIG. 4B, the polysilicon 507 is deposited on the entire surface of the wafer to form the sidewall floating gate, and a sidewall floating gate is formed on the side of the buffer nitride layer through a blanket etching process. The deposition thickness of the polysilicon deposited to form the sidewall floating gate is preferably deposited in the range of 100 to 1500 kPa.

Next, as shown in FIG. 4C, after the tunnel oxide film in the open region is removed, the gate oxide film 509 is grown on the open silicon substrate through the oxide film growth process and coupled to the surface of the sidewall floating gate simultaneously exposed. The ring oxide film 508 is grown. The oxide film may be deposited instead of growing the oxide film on the gate oxide and sidewall floating gate surfaces.

Next, as shown in FIG. 4D, the polysilicon 510, the second buffer oxide layer 511, and the second buffer nitride layer 512 are sequentially deposited on the wafer front to form a polysilicon gate and then patterned. The polysilicon deposited to form the polysilicon gate may use doped poly or may be doped through an ion implantation process after depositing the undoped poly. The deposition thickness of the polysilicon for forming the polysilicon gate is preferably deposited in the range of 500 kV to 4000 kV. The second buffer oxide film deposition process may not proceed.

Next, as shown in FIG. 4E, after the first buffer nitride layer is removed by wet etching, an oxide layer is processed to grow or deposit an oxide layer 515 on the side of the polysilicon gate and the sidewall floating gate. Subsequently, an ion implantation process is performed using a polysilicon gate as a mask to form an LDD or source / drain extension region, an insulating film is deposited on the entire surface of the wafer, and a sidewall spacer 516 is formed on the side of the polysilicon gate through blanket etching. . Subsequently, an ion implantation process is performed using the polysilicon cone gate and the sidewall spacers to form a source / drain region. Next, the silicide process is performed to selectively form silicide in a region used as a common source / drain to reduce resistance. The source / drain regions may be formed before the sidewall spacers are formed without forming the LDD separately. The sidewall spacer is preferably formed of an oxide film, and may be formed using a nitride film or both of an oxide film and a nitride film. If necessary, the silicide process may be omitted in the common source / drain region.

Next, as shown in FIG. 4F, an etch back process is performed while filling the voids between the polysilicon gates using an Atmospheric Pressure Chemical Vapor Deposition (APCVD) process or a High Density Plasma Chemical Vapor Deposition (HDP-CVD) process. The planarization of the gap-filled oxide film 517 is performed through the recess until the polysilicon gate is exposed. In this case, a chemical mechanical polishing (CMP) process may be used instead of the etch back process.

Next, as shown in FIG. 4G, the oxide film formed on the polysilicon gate is removed by a wet etching process, and then polysilicon 518 is deposited on the entire surface of the wafer to form a word line. The polysilicon deposited to form the word line may use a doped poly or may be doped through an ion implantation process after depositing the undoped poly. The deposition thickness of the polysilicon for forming the word line is preferably deposited in the range of 500 kV to 3000 kV.

Next, as shown in FIG. 4H, patterning is performed in the word line direction to form a shallow trench isolation (STI). The word line, the polysilicon gate, and the substrate are etched in the word line direction to form an STI. Through the patterning process, the word line and the polysilicon gate in the B-B 'direction form a stack gate. Each stack gate is separated by an STI to improve device isolation between word lines. In the CC 'direction, the gapfill oxide layer and the sidewall spacer are formed on the region where the common source / drain is formed, thus protecting the common source / drain during the word line forming process. Therefore, the word line polysilicon, polysilicon gate and Only the underlying silicon substrate is selectively etched to selectively form an STI between the common source and the common drain region. Therefore, the STI formed in the process physically separates the common source / drain, thereby improving device isolation between the common source and the common drain. Here, the word lines serve to connect the polysilicon gates formed in the previous process to each other in the word line direction. After forming the STI in the word line direction, the oxide film growth process may be further performed. As described above, after forming the STI selectively between the word line and the word line through the word line forming process, a channel stop implantation process is performed to increase the threshold voltage of the filter transistor. You can go further.

Next, as shown in FIG. 4I, an insulating film for forming sidewall spacers is deposited on the entire surface of the substrate, and then sidewall spacers are formed through blanket etching, and then silicide is selectively formed on a word line through a silicide process. The insulating film deposited to form the sidewall spacer is preferably an oxide film and may deposit a nitride film or both an oxide film and a nitride film. Instead of the sidewall spacer process, the word line surface is exposed while filling the gaps and STIs between the stack gates using the APCVD process or the HDP process and the planarized oxide film is planarized through the etch back process, and then the word line surface exposed through the silicide process. Alternatively, silicide may be formed. Subsequently, the nonvolatile memory device of the present invention is manufactured using the same process as the conventional MOS transistor fabrication process.

As described above, the STI is selectively formed when forming the word line without performing the STI forming process, thereby assuring device isolation between the word line and the word line and device isolation between the common source and the common drain. It can effectively reduce the area occupied by NOR flash cells without using the STI process. In addition, the effective implementation of a two-bit sidewall floating gate NOR flash cell with no bit contact can reduce the area occupied by the NAND flash cell by half. In addition, silicide may be selectively formed in the common source and the common drain region, thereby effectively reducing the resistance values of the common source and the common drain, thereby reducing the number of contacts for boot strapping, thereby increasing the device area. It can be made small.

It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.

Therefore, the method of manufacturing a nonvolatile memory device of the present invention allows the STI to be selectively formed when forming the word line without separately performing the STI forming process, and thus the device isolation characteristics between the word line and the word line and between the common source and the common drain. By ensuring device isolation, NOR flash cells occupy less space without using SAS or SA-STI processes. In addition, silicide may be selectively formed in the common source and the common drain region, thereby effectively reducing the resistance values of the common source and the common drain, thereby reducing the number of contacts for boot strapping, thereby increasing the device area. There is an effect that can be made small.

1 is a cross-sectional view of a flash memory cell according to the prior art.

2 is a view comparing the area of a conventional NOR flash unit cell with the area of a unit cell of a nonvolatile memory device of the present invention.

3 is a cell array layout of a nonvolatile memory device according to the present invention.

4A to 4I are cross-sectional views of a method of manufacturing a nonvolatile memory device in accordance with the present invention.

Claims (7)

In the method of manufacturing a nonvolatile memory device, Forming and patterning a buffer oxide film and a buffer nitride film on the entire surface of the semiconductor substrate; Forming a sidewall floating gate on sidewalls of the patterned buffer nitride film; Depositing and patterning polysilicon on the substrate to form a polysilicon gate; Removing the buffer nitride film; Forming a first sidewall spacer on sidewalls of the floating gate and the polysilicon gate; Implanting impurity ions into the substrate to form a common source / drain region; Depositing and planarizing an insulating film on the substrate to gap fill between polysilicon gates; Depositing polysilicon for word lines on the substrate; Patterning the substrate for the word line polysilicon, polysilicon gate and substrate in a word line direction to form an STI; And Forming a second sidewall spacer on sidewalls of the word line and the polysilicon gate Method of manufacturing a nonvolatile memory device comprising a. The method of claim 1, The buffer oxide film is a method of manufacturing a nonvolatile memory device, characterized in that formed in a thickness of 50 to 300Å. The method of claim 1, The buffer nitride film is a method of manufacturing a nonvolatile memory device, characterized in that formed in a thickness of 100 to 2000Å. The method of claim 1, Forming a gate oxide film on the exposed semiconductor substrate and a coupling oxide film on the exposed sidewall floating gate prior to forming the polysilicon gate. The method of claim 1, The polysilicon for forming the polysilicon gate is formed in a thickness of 500 to 4000 소자. The method of claim 1, The polysilicon for forming the word line is a manufacturing method of a nonvolatile memory device, characterized in that formed to a thickness of 500 to 3000Å. The method of claim 1, And the word line connects the polysilicon gates to each other in a word line direction.