KR20050068466A - Liquid crystal display device and method for fabricating the same - Google Patents

Abstract

It is an object of the present invention to provide a liquid crystal display device and a method of manufacturing the same, which can improve a process profile, prevent contact failure due to corrosion, and save production cost. The liquid crystal display device of the present invention for achieving the above object includes a gate line formed in a single layer on the substrate and a gate pad extending at one end thereof; A data line formed vertically and horizontally with the gate line to define a pixel area; A thin film transistor (TFT) formed of a gate electrode, a source electrode, and a drain electrode at an intersection of the gate line and the data line; A storage electrode overlapping one region of the front gate line; A data pad extending from the data line and formed at one end thereof; A protective film formed on an entire surface of the substrate including the thin film transistor; A pixel electrode formed in the pixel region such that the drain electrode is connected to one region of the storage electrode through an ohmic connection layer; A gate pad electrode connected to the gate pad; And a data pad electrode connected to the data pad.

Description

Liquid crystal display device and method for manufacturing the same {Liquid Crystal Display Device and method for fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method for manufacturing the same, which can improve a process profile, prevent contact failure due to corrosion, and reduce production costs.

As the information society develops, the demand for display devices is increasing in various forms.In recent years, liquid crystal display (LCD), plasma display panel (PDP), electro luminescent display (ELD), and vacuum fluorescent display (VFD) have been developed. Various flat panel display devices have been studied, and some are already used as display devices in various devices.

Among them, LCD is the most widely used as a substitute for CRT (Cathode Ray Tube) for the use of mobile image display device because of the excellent image quality, light weight, thinness, and low power consumption, and mobile type such as monitor of notebook computer. In addition, it is being developed in various ways, such as a television for receiving and displaying broadcast signals, and a monitor of a computer.

As described above, although various technical advances have been made in order for the liquid crystal display device to serve as a screen display device in various fields, the task of improving the image quality as the screen display device has many advantages and disadvantages.

Therefore, in order to use a liquid crystal display device in various parts as a general screen display device, the key to development is how much high definition images such as high definition, high brightness, and large area can be realized while maintaining the characteristics of light weight, thinness, and low power consumption. It can be said.

Such a liquid crystal display may be largely divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel. The liquid crystal panel has a predetermined space, and includes an upper substrate, a lower substrate, and the upper and lower substrates. It is composed of a liquid crystal layer formed between the lower substrate.

Here, the lower substrate (TFT array substrate) includes a plurality of gate wirings arranged in one direction at a predetermined interval, a plurality of data wirings arranged at regular intervals in a direction perpendicular to the respective gate wirings, and the respective gate wirings. A plurality of pixel electrodes formed in a matrix form in each pixel region defined by intersections of the data lines and a plurality of thin film transistors which are switched by signals of the gate lines to transfer the signals of the data lines to the pixel electrodes. Is formed.

In addition, the upper substrate (color filter array substrate) includes a black matrix layer for blocking light in portions other than the pixel region, an R, G, B color filter layer for expressing color colors, and a common electrode for realizing an image. Is formed.

In addition, the upper substrate and the lower substrate thus formed have a predetermined space by a spacer for maintaining a cell gap, and are bonded by a sealant. And liquid crystal is formed in the space inside a seal material.

When manufacturing a liquid crystal display device having such a structure, instead of forming one liquid crystal panel on one substrate, a plurality of liquid crystal panels are simultaneously formed on one large substrate according to the size of the substrate and the size of the liquid crystal panel.

As described above, a liquid crystal display generally has a structure in which a liquid crystal is injected between two substrates, and light transmittance is controlled by adjusting the intensity of an electric field applied between the two substrates.

The lower substrate (TFT array substrate) of the two substrates includes a plurality of gate wirings, data wirings, and pixel electrodes, and is formed by repeating a process of forming a thin film and etching a plurality of times.

In recent years, as the size of liquid crystal displays increases, there is a need to use low-resistance metals as wiring materials in order to reduce the signal delay due to the length of wirings on the lower substrate. This is mainly used.

In the manufacturing process of the lower substrate, the gate wiring may be formed of a double layer of Mo / AlNd. In this case, the RC of the signal flowing through the gate line is small because the resistance of the aluminum-based metal used as the lower layer of the gate wiring is small. Delay can be reduced, and since the molybdenum used as the upper layer has high corrosion resistance to chemicals, it is possible to prevent the problem of disconnection defect caused by the etching solution.

However, when the gate wiring is formed of a double layer of Mo / AlNd as described above, the wet etching process must be performed using both wet etching and dry etching processes, which leads to a complicated process. .

The data line is formed before the pixel electrode, and some of the data line is in contact with the pixel electrode. However, when Al or an Al alloy is used as the data line, the ITO etchant easily corrodes the data line when the indium-tin-oxide (ITO) is etched to form the pixel electrode. In addition, the data line and the pixel electrode are poorly contacted, and even if the contact is made, the contact resistance is high and there is a possibility that the contact portion is broken with time.

In order to prevent this, there is a method of completely covering the Al wiring by using an extra conductive material, but since the number of photolithography processes increases, there is a large manufacturing cost problem.

In the liquid crystal display of the 4 and 5 masks, the data wiring can be formed by a triple layer of Cr / AlNd / Cr. In the case of the 5 mask, Cr, AlNd, and Cr are sequentially processed three times in separate process equipment. The wet etching process is required, and in the case of four masks, three wet etching processes for forming data wirings and three wet etching processes for forming channel regions are required to be performed separately. Therefore, the problem of low production competitiveness may occur.

The present invention has been made to solve the above problems, and an object of the present invention is to improve the process profile, to prevent poor contact due to corrosion, and to reduce the cost of production, and a manufacturing method thereof To provide.

The liquid crystal display device of the present invention for achieving the above object comprises a gate line formed in a single layer on the substrate and a gate pad extending at one end thereof; A data line formed vertically and horizontally with the gate line to define a pixel area; A thin film transistor (TFT) formed of a gate electrode, a source electrode, and a drain electrode at an intersection of the gate line and the data line; A storage electrode overlapping one region of the front gate line; A data pad extending from the data line and formed at one end thereof; A protective film formed on an entire surface of the substrate including the thin film transistor; A pixel electrode formed in the pixel region such that the drain electrode is connected to one region of the storage electrode through an ohmic connection layer; A gate pad electrode connected to the gate pad; And a data pad electrode connected to the data pad.

The gate line, the gate electrode, and the gate pad may include a single layer of AlNd, which is an aluminum metal layer.

The thin film transistor TFT is formed to be spaced apart from the gate electrode protruding from one side of the gate line, the source electrode protruding from one side of the data line, and the source electrode and connected to the pixel electrode. And a semiconductor pattern overlapping the drain electrode with the gate electrode and the gate insulating layer interposed therebetween to form a channel between the source electrode and the drain electrode.

The data line, the source electrode and the drain electrode may be formed of a double layer of AlNd / Mo or AlNd may be formed on the silicide layer.

The semiconductor pattern may include a channel portion between the source electrode and the drain electrode, and an active layer disposed below the data line, the source electrode, and the drain electrode, and each of the data line, the source electrode, and the drain electrode. And an ohmic contact layer formed between the active layers.

The storage electrode and the data pad may be formed of a double layer of an amorphous silicon layer, an n + amorphous silicon layer, and AlNd / Mo, or may be formed by forming AlNd on an amorphous silicon layer, an n + amorphous silicon layer, and a silicide layer.

The protective layer may include a first hole formed to expose one region and a pixel region of the drain electrode, the storage electrode, and first and second contact holes formed to expose one region of the gate pad and the data pad. It features.

Molybdenum (Mo) is formed on the gate pad and the data pad where the first and second contact holes are formed.

Molybdenum (Mo) is formed in one region where the pixel electrode, the drain electrode and the storage electrode are connected to form an ohmic connection layer of an AlNd-Mo alloy.

The pixel electrode may extend in a first hole to be directly connected to the drain electrode and the upper portion of the storage electrode above the previous gate line.

The thin film transistor TFT may include the gate electrode protruding from one side of the gate line, an active layer patterned on the gate insulating layer including the gate electrode by placing a gate insulating layer, and protruding from one side of the data line. The source electrode overlapped with an upper portion of the one side, and the source electrode is characterized in that it further comprises a drain electrode formed at a predetermined interval spaced apart on the other side of the active layer.

The storage electrode and the data pad may further include AlNd formed on a double layer or silicide layer of AlNd / Mo.

A method of manufacturing a liquid crystal display device according to the present invention having the above structure includes the steps of: forming a gate line, a gate electrode, and a gate pad as a single layer on a substrate using a first mask process; Forming a data line arranged vertically and horizontally with the gate line to define a pixel region, a source electrode, a drain electrode, a data pad, and a storage electrode using a second mask process; Forming a passivation layer on the entire surface of the substrate; A photoresist pattern may be formed using a third mask process, and the first hole, the gate pad, and the first region may be formed on the passivation layer to expose one region and a pixel region of the drain electrode and the storage electrode using the photoresist pattern. A fourth step of forming first and second contact holes to expose one region of the data pad; A fifth step of forming an ohmic metal layer only on one region of the drain electrode and the storage electrode of the first hole and the gate pad and the data pad below the first and second contact holes; And a sixth step of forming a pixel electrode, a gate pad electrode, and a data pad electrode to be connected to the first hole, the first contact hole, and the second contact hole, respectively, via an ohmic metal layer.

The first step may include forming a gate metal layer on the substrate; Patterning the gate metal layer by a photolithograph process and an etching process using the first mask.

The gate metal layer is characterized by using an aluminum-based metal of AlNd.

The second step may include sequentially forming an amorphous silicon layer, an n + amorphous silicon layer, and a first metal layer for forming a source / drain; Forming a photoresist pattern having a thin thickness in the channel portion by a photolithography process using the second mask having a diffraction exposure portion in the channel portion of the thin film transistor on the first metal layer; A source / drain pattern including the data line, the source electrode, and a drain electrode integrated with the source electrode by patterning the first metal layer by a wet etching process using the photoresist pattern, and data formed at one end of the data line Forming a storage electrode on the pad and one region of the previous gate line; Patterning the n + amorphous silicon layer and the amorphous silicon layer by a dry etching process using the same photoresist pattern to form an ohmic contact layer and an active layer; Ashing the photoresist pattern and then dry etching the mask with the mask to etch the source / drain pattern and the ohmic contact layer of the channel part to separate the source electrode and the drain electrode; And removing the photoresist pattern.

The first metal layer is composed of a double layer of AlNd / Mo or a single layer of AlNd.

When the first metal layer is formed of a single layer of AlNd, it is further characterized by forming a silicide layer by depositing a metal such as Mo or Cr before forming the AlNd.

Forming a second metal layer on the photoresist pattern including the first hole and the first and second contact holes; And etching the entire surface of the second metal layer by using a fruit-based etchant.

The fruit water etchant is characterized in that using H2O2 + CH3COO- (additive).

The second metal layer is characterized in that it uses molybdenum (Mo).

When etching using the permeable etchant, all of the second metal layer except for the upper portion of the drain electrode and the storage electrode of the first hole and the first and second contact holes is removed.

The sixth step may include forming a transparent conductive film on the entire surface of the substrate including the photoresist pattern; And removing the photoresist pattern by a lift-off process.

The pixel electrode may be formed to be in direct contact with the storage electrode on an upper gate line of the drain electrode.

The transparent conductive film is characterized by using indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO).

A method of manufacturing a liquid crystal display device according to the present invention having the above structure includes the steps of: forming a gate line, a gate electrode, and a gate pad as a single layer on a substrate using a first mask process; A second step of forming an active layer and an ohmic contact layer on one region of the gate electrode by using a second mask process; A data line arranged vertically and horizontally with the gate line to define a pixel region using a third mask process, a source electrode connected to the data line, a drain electrode spaced at a predetermined distance from the source electrode, and at the data line A third step of extending a data pad formed at one end and a storage electrode formed at one region of a previous gate line; Forming a passivation layer on the entire surface of the substrate; A photoresist pattern is formed using a fourth mask process, and a first hole, the gate pad, and the first region are formed in the passivation layer to expose one region and a pixel region of the drain electrode and the storage electrode using the photoresist pattern. A fifth step of forming first and second contact holes to expose one region of the data pad; A sixth step of forming an ohmic metal layer only on one region of the drain electrode and the storage electrode of the first hole and the gate pad and the data pad below the first and second contact holes; And a seventh step of forming a pixel electrode, a gate pad electrode, and a data pad electrode to be connected to the first hole, the first contact hole, and the second contact hole, respectively, via an ohmic metal layer.

The data line, the source electrode, the drain electrode, the storage electrode and the data pad may be formed of a double layer of AlNd / Mo or a single layer of AlNd.

When forming a single layer of the AlNd, before forming the AlNd is characterized in that it further comprises forming a silicide layer by depositing a metal such as Mo or Cr.

Forming a metal layer on the photoresist pattern including the first hole and the first and second contact holes; And etching the entire surface of the second metal layer by using a fruit-based etchant.

The fruit water etchant is characterized in that using H2O2 + CH3COO- (additive).

The metal layer is characterized in that it uses molybdenum (Mo).

The seventh step may include forming a transparent conductive film on the entire surface of the substrate including the photoresist pattern; And removing the photoresist pattern by a lift-off process.

Hereinafter, a liquid crystal display and a method of manufacturing the same according to the present invention will be described with reference to the accompanying drawings.

First embodiment

First, a liquid crystal display according to a first embodiment of the present invention will be described.

1 is a plan view of a liquid crystal display according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of a structure of the liquid crystal display according to the first embodiment of the present invention.

As shown in FIGS. 1 and 2, the liquid crystal display according to the first exemplary embodiment of the present invention protrudes from one side of the gate line 31 and one side of the gate line 31 formed on the lower substrate 30. The gate electrode 31a, the gate pad 31b extending from the gate line 31, and formed at one end thereof, the gate insulating layer 32 formed on the entire surface including the gate line 31, and the gate line. A data line 35a intersecting with 31 to define a pixel region; a thin film transistor TFT formed of a gate electrode 31a, a source electrode 35b, and a drain electrode 35c at each of the intersections; The storage electrode 35d overlapping one region of the line, the data pad 35e extending from the data line 35a and formed at one end thereof, and the passivation layer 37 formed on the entire surface of the lower substrate 30 including the thin film transistor. And the drain electrode 35c and the storage electrode 35d. A first hole 39a formed in a pixel region including one region of the first region, first and second contact holes 39b and 39c formed on the gate pad 31d and the data pad 35e, and the first hole. A pixel electrode 41a formed in the pixel region including the 39a, a gate pad electrode 41b connected to the gate pad 31b through the first contact hole 39b, and the second contact hole 39c. It consists of the data pad electrode 41c connected to the data pad 35e through the said.

The gate line 31, the gate electrode 31a, and the gate pad 31b are formed of a single layer of AlNd, which is an aluminum metal layer.

The thin film transistor TFT is spaced apart from the gate electrode 31a protruding from one side of the gate line 31, the source electrode 35b protruding from one side of the data line 35a, and the source electrode 35b. And a drain electrode 35c connected to the pixel electrode 41a, the gate electrode 31b and the gate insulating layer 32 interposed therebetween, and a channel between the source electrode 35b and the drain electrode 35c. It consists of a semiconductor pattern to form.

The data line 35a, the source electrode 35b, and the drain electrode 35c have a double layer of AlNd / Mo or AlNd formed on the silicide layer.

The thin film transistor TFT allows the pixel voltage signal supplied to the data line 35a to be charged and held in the pixel electrode 41a in response to the gate signal supplied to the gate line 31.

The semiconductor pattern is composed of an active layer 33a and an ohmic contact layer 34a, wherein the active layer 33a includes a channel portion between the source electrode 35b and the drain electrode 35c, and the data line 35a and the source electrode. An ohmic contact layer 34a is formed between the data line 35a, the source electrode 35b, the drain electrode 35c, and the active layer 33a so as to overlap the 35b and the drain electrode 35c. Is formed.

The storage electrode 35d and the data pad 35e are formed by laminating an amorphous silicon layer 33, an n + amorphous silicon layer 34, and a first metal layer 35. In this case, the first metal layer 35 is formed of a double layer of AlNd / Mo, or AlNd is formed on the silicide layer.

The storage capacitor includes the previous gate line 31, the gate insulating layer 32, and the storage electrode 35d. The storage capacitor includes a pixel voltage charged in the pixel electrode 41a and a next pixel voltage. It will help you stay there.

A second metal layer 40 formed of molybdenum (Mo) is formed under the first and second contact holes 39b and 39c of the gate pad 31b and the data pad 35e.

A second metal layer 40 made of molybdenum (Mo) is formed in one region of the drain electrode 35c connected to the pixel electrode 41a and the storage electrode 35d to form an ohmic contact layer of an AlNd-Mo alloy. It consists.

The pixel electrode 41a is formed on the pixel area of the lower substrate 30 and extends so as to be directly connected to the storage electrode 35d of the previous gate line in the drain electrode 35c of the thin film transistor.

The pixel electrode 41a generates a potential difference with the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. Due to this potential difference, the liquid crystal positioned between the thin film transistor substrate and the upper substrate rotates by dielectric anisotropy, and transmits the light incident through the pixel electrode 41a from the light source (not shown) toward the upper substrate.

Although not shown, the gate line 31 is connected to the gate driver through the gate pad 31b, and the data line 35a is connected to the data driver through the data pad 35e.

The thin film transistor array substrate having such a configuration is formed by a three mask process.

Next, a manufacturing method of the liquid crystal display device according to the first embodiment of the present invention formed by the three mask process having the above configuration will be described.

3A to 3H are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention, taken along lines II ′, II-II ′, III-III ′, and IV-IV ′ of FIG. 1. to be.

In the method of manufacturing the liquid crystal display according to the first embodiment of the present invention, as shown in FIG. 3A, the gate metal layer is formed on the lower substrate 30 through a deposition method such as a sputtering method. Subsequently, the gate patterns including the gate line 31, the gate electrode 31a, and the gate pad 31b are formed by patterning the gate metal layer by a photolithograph process and an etching process using a first mask. The gate metal layer is formed of a single layer of aluminum-based metal, for example AlNd. The gate pad 31b extends from the gate line 31 and is formed at one end thereof.

Subsequently, as shown in FIG. 3B, the gate insulating layer 32, the amorphous silicon layer 33, and the n + amorphous silicon layer 34 are deposited on the lower substrate 30 on which the gate patterns are formed through a deposition method such as PECVD or sputtering. And the first metal layer 35 for source / drain formation are sequentially formed. At this time, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the material of the gate insulating film 32.

The first metal layer 35 for forming a source / drain may be formed of a double layer of AlNd / Mo or a single layer of AlNd. In the following drawings, a case where a double layer of AlNd / Mo is formed will be described as an example.

Although not shown in the drawing, when the first metal layer 35 is formed using a single layer of AlNd, the silicide layer is formed by depositing a metal such as Mo or Cr after forming the n + amorphous silicon layer 34. After forming the first metal layer 35 made of AlNd on the front surface.

Thereafter, the photoresist pattern 36 is formed on the first metal layer 35 by a photolithography process using a second mask. In this case, the second mask uses a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor so that the photoresist pattern of the channel portion has a lower height than other source / drain pattern portions.

Subsequently, as shown in FIG. 3C, the first metal layer 35 is patterned by a wet etching process using the photoresist pattern 36 to form the data line 35a, the source electrode 35b, and the source electrode 35b. Metal patterns including the integrated drain electrode 35c and the storage electrode and the data pad are formed.

Then, the n + amorphous silicon layer 34 and the amorphous silicon layer 33 are simultaneously patterned by a dry etching process using the same photoresist pattern, thereby forming the ohmic contact layer 34a and the active layer 33a.

The storage electrode 35d, the data pad 35e are formed by laminating an amorphous silicon layer 33, an n + amorphous silicon layer 34, and a first metal layer 35.

3D, the photoresist pattern having a relatively low height in the channel portion is removed by an ashing process, and then the source / drain pattern and the ohmic contact layer 34a of the channel portion are removed by a dry etching process. Etched. Accordingly, when the active layer 33a of the channel portion is exposed and the active layer 33a is not activated, the source electrode 35b and the drain electrode 35c are electrically separated.

Subsequently, the photoresist pattern remaining on the source / drain pattern portion is removed by a stripping process.

By the above process, a thin film transistor (TFT) including a gate electrode 31a, an active layer 33a, a source electrode 35b, and a drain electrode 35c is formed, and an amorphous silicon layer (above the previous gate line 31) is formed. 33, a storage electrode 35d on which the n + amorphous silicon layer 34 and the first metal layer 35 are stacked, and a gate pad 31b is formed at one end extending from the gate line 31. A data pad 35e in which an amorphous silicon layer 33, an n + amorphous silicon layer 34, and a first metal layer 35 are stacked is formed at an end extending from the line 35a.

Next, as shown in FIG. 3E, a protective film 37 is formed on the entire surface of the lower substrate 30 including the thin film transistor TFT by a deposition method such as PECVD, and a photoresist is applied on the protective film 37. .

The photoresist is selectively patterned by an exposure and development process using a third mask to form a photoresist pattern 38. Thereafter, the protective layer 37 is etched using the photoresist pattern 38 as a mask to form first holes 39a and first and second contact holes 39b and 39c.

In this case, the first hole 39a is opened to expose the pixel region including one region of the drain electrode 35c and the storage electrode 35d through the passivation layer 37, and the first contact hole 39b is formed of the passivation layer ( The gate pad 31b is exposed through the gate insulating layer 32 and the gate insulating layer 32, and the second contact hole 39c is formed through the passivation layer 37 to expose the data pad 35e.

As the material of the protective film 37, an inorganic insulating material such as the gate insulating film 32 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used.

Thereafter, the second metal layer 40 is formed on the photoresist pattern 38 including the first hole 39a and the first and second contact holes 39b and 39c. At this time, the second metal layer 40 uses molybdenum (Mo). When the second metal layer 40 is deposited, an AlNd-Mo alloy layer is formed on the drain electrode 35c of the first hole 39a and the storage electrode 35d, and the pixel region of the first hole 39a is formed. Only molybdenum (Mo) is formed, and an AlNd-Mo alloy layer is formed in the first and second contact holes 39b and 39c.

Next, as shown in FIG. 3F, when the entire surface is etched using the peroxide-based etchant, the second metal layer 40 having only Mo except for the AlNd-Mo alloy layer is removed. All of the second metal layer 40 is removed except the drain electrode 35c of the first hole 39a and the upper portion of the storage electrode 35d and the AlNd-Mo alloy layers of the first and second contact holes 39b and 39c. do.

At this time, the fruit water etchant is composed of H2O2 + CH3COO- (additive).

Subsequently, as shown in FIG. 3G, a transparent conductive film 41 is formed on the entire surface of the lower substrate 30 including the photoresist pattern 38. In this case, indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO) is used for the transparent conductive film 41.

Thereafter, as shown in FIG. 3H, the photoresist pattern 38 is removed by a lift-off process. As a result, the pixel electrode 41a is formed in the pixel region, the gate pad electrode 41b is formed on the gate pad 31b, and the data pad electrode 41c is formed on the data pad 35e.

The pixel electrode 41a extends from the drain electrode 35c to the storage electrode 35d on the previous gate line.

The liquid crystal display device is formed using three masks.

Second embodiment

In addition to the method for manufacturing the liquid crystal display of the three masks, the present invention can produce a liquid crystal display in a four-mask process. Shall be.

First, a liquid crystal display according to a second embodiment of the present invention will be described.

4 is a plan view illustrating a liquid crystal display device according to a second embodiment of the present invention, and FIG. 5 is a cross-sectional view of a structure of the liquid crystal display device according to a second embodiment of the present invention.

4 and 5, the gate line 31 formed in one direction on the lower substrate 30, the gate electrode 31a protruding from one side of the gate line 31, and the gate line 31. A gate pad 31b formed at one end extending from the gate pad, a gate insulating film 32 formed on the entire surface including the gate line 31, and a data line crossing the gate line 31 to define a pixel region ( 35a, a thin film transistor TFT formed of a gate electrode 31a, a source electrode 35b, and a drain electrode 35c at each intersection, a storage electrode 35d overlapping one region of a front gate line, A data pad 35e extending from the data line 35a and formed at one end thereof, a passivation layer 37 formed on an entire surface of the lower substrate 30 including the thin film transistor, the drain electrode 35c and the storage electrode 35d. A first hole 3 formed in the pixel region including one region of the 9a, the pixel electrode 41a formed in the pixel region including the first and second contact holes 39b and 39c formed on the gate pad 31d and the data pad 35e, and the first hole 39a. ), A gate pad electrode 41b connected to the gate pad 31b through the first contact hole 39b, and a data pad electrode connected to the data pad 35e through the second contact hole 39c. It consists of 41c.

The gate line 31, the gate electrode 31a, and the gate pad 31b are formed of a single layer of AlNd, which is an aluminum metal layer.

The thin film transistor TFT includes a gate electrode 31a protruding from one side of the gate line 31 and a gate insulating layer 32 to pattern the active layer formed on the gate insulating layer 32 including the gate electrode 31a. A source electrode 35b protruding from one side of the data line 35a and overlapping an upper portion of the active layer 33a, and spaced apart from the source electrode 35b at a predetermined interval and on the other side of the active layer 33a. It consists of the drain electrode 35c which overlapped in the upper part.

An ohmic contact layer 34a is further provided between the active layer 33a and the source electrode 35b, and between the active layer 33a and the drain electrode 35c.

The data line 35a, the source electrode 35b, and the drain electrode 35c may be formed of a double layer of AlNd / Mo or AlNd formed on a silicide layer. In this case, the silicide layer may be a chromium silicide layer or a molybdenum silicide layer.

The thin film transistor TFT allows the pixel voltage signal supplied to the data line 35a to be charged and held in the pixel electrode 41a in response to the gate signal supplied to the gate line 31.

The storage electrode 35d and the data pad 35e are made of AlNd formed on the AlNd / Mo double layer or the silicide layer. At this time, the silicide layer is composed of molybdenum silicide or chromium silicide.

The storage capacitor includes the previous gate line 31, the gate insulating layer 32, and the storage electrode 35d. The storage capacitor includes a pixel voltage charged in the pixel electrode 41a and a next pixel voltage. It will help you stay there.

A second metal layer 40 formed of molybdenum (Mo) is formed under the first and second contact holes 39b and 39c of the gate pad 31b and the data pad 35e.

A second metal layer 40 made of molybdenum (Mo) is formed in one region of the drain electrode 35c connected to the pixel electrode 41a and the storage electrode 35d to form an ohmic contact layer of an AlNd-Mo alloy. It consists.

The pixel electrode 41a is formed on the pixel area of the lower substrate 30 and extends so as to be directly connected to the storage electrode 35d of the previous gate line in the drain electrode 35c of the thin film transistor.

The pixel electrode 41a generates a potential difference with the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. Due to this potential difference, the liquid crystal positioned between the thin film transistor substrate and the upper substrate rotates by dielectric anisotropy, and transmits the light incident through the pixel electrode 41a from the light source (not shown) toward the upper substrate.

Although not shown, the gate line 31 is connected to the gate driver through the gate pad 31b, and the data line 35a is connected to the data driver through the data pad 35e.

Next, a manufacturing method of the liquid crystal display device according to the second embodiment of the present invention having the above configuration will be described.

6A through 6F are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a second exemplary embodiment, in which lines V-V ′, VI-VI ′, VIII-VIII, and VIII-VIII in FIG. to be.

As shown in FIG. 6A, a gate metal layer is formed on the lower substrate 30 through a deposition method such as a sputtering method. Subsequently, gate patterns including the gate line 31, the gate electrode 31a, and the gate pad 31b are formed by patterning the gate metal layer by a photolithography process and an etching process using a first mask.

The gate metal layer is formed of a single layer of aluminum-based metal, for example AlNd. The gate pad 31b extends from the gate line 31 and is formed at one end thereof.

Subsequently, as illustrated in FIG. 6B, the gate insulating layer 32, the amorphous silicon layer, and the n + amorphous silicon layer are sequentially deposited on the entire surface including the gate line 31, and then photolithography and etching using a second mask are performed. A process is performed to form the photoresist pattern 36. Thereafter, the n + amorphous silicon layer and the amorphous silicon layer are sequentially etched so as to remain in one region including the gate electrode 31a using the photoresist pattern 36 as a mask to stack the active layer 33a and the ohmic contact layer 34a.

Next, as illustrated in FIG. 6C, the first metal layer for source / drain formation is deposited on the entire surface, and the first metal layer is etched by a photolithography process and an etching process using a third mask to etch the data lines 35a and the source. The electrode 35b, the drain electrode 35c, the storage electrode 35d and the data pad 35e are formed. At this time, the ohmic contact layer 34a of the channel part is etched to expose the active layer 33a.

The data line 35a is arranged in a direction perpendicular to the gate line 31 to define a pixel region. The source electrode 35b protrudes from one side of the data line 35a, and the drain electrode 35c The storage electrode 35d is formed at a predetermined distance from the source electrode 35b, and the storage electrode 35d is formed at one end of the previous gate line, and the data pad 35e is formed at one end of the data line 35b.

The first metal layer 35 for forming a source / drain may be formed of a double layer of AlNd / Mo or a single layer of AlNd. In the following drawings, a case where a double layer of AlNd / Mo is formed will be described as an example.

Although not shown in the drawing, when the first metal layer 35 is formed using a single layer of AlNd, the silicide layer is formed by depositing a metal such as Mo or Cr after forming the n + amorphous silicon layer 34. After forming the first metal layer 35 made of AlNd on the front surface.

Next, as shown in FIG. 6D, a protective film 37 is formed on the entire surface of the lower substrate 30 including the thin film transistor by PECVD or the like, and a photoresist is applied on the protective film 37.

The photoresist is selectively patterned by an exposure and development process using a fourth mask to form a photoresist pattern 38.

Thereafter, the protective layer 37 is etched using the photoresist pattern 38 as a mask to form first holes 39a and first and second contact holes 39b and 39c.

In this case, the first hole 39a is opened to expose the pixel region including one region of the drain electrode 35c and the storage electrode 35d through the passivation layer 37. The gate pad 31b is exposed through the gate insulating layer 32 and the gate insulating layer 32, and the second contact hole 39c is formed through the passivation layer 37 to expose the data pad 35e.

As the material of the protective film 37, an inorganic insulating material such as the gate insulating film 32 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used.

Thereafter, the second metal layer 40 is formed on the photoresist pattern 38 including the first hole 39a and the first and second contact holes 39b and 39c. At this time, the second metal layer 40 uses Mo. When the second metal layer 40 is deposited, an AlNd-Mo alloy layer is formed on the drain electrode 35c of the first hole 39a and the storage electrode 35d, and the pixel region of the first hole 39a is formed. Only Mo is formed, and an AlNd-Mo alloy layer is formed in the first and second contact holes 39b and 39c.

Next, as shown in FIG. 6E, when the entire surface is etched using the peroxide-based etchant, the second metal layer 40 having only Mo except for the AlNd-Mo alloy layer is removed. All of the second metal layer 40 is removed except the drain electrode 35c of the first hole 39a and the upper portion of the storage electrode 35d and the AlNd-Mo alloy layers of the first and second contact holes 39b and 39c. do.

At this time, the fruit water etchant is composed of H2O2 + CH3COO- (additive).

Subsequently, a transparent conductive film 41 is formed on the entire surface of the lower substrate 30 including the photoresist pattern 38. In this case, indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO) is used for the transparent conductive film 41.

Thereafter, as shown in FIG. 6F, the photoresist pattern 38 is removed by a lift-off process. As a result, the pixel electrode 41a is formed in the pixel region, the gate pad electrode 41b is formed on the gate pad 31b, and the data pad electrode 41c is formed on the data pad 35e.

The pixel electrode 41a extends from the drain electrode 35c to the storage electrode 35d on the previous gate line.

As described above, the method shown in FIGS. 6D, 6E, and 6F is formed by the same method as the method according to the first embodiment of the present invention shown in FIGS. 3E through 3H.

As described above, the manufacturing method of the liquid crystal display according to the second exemplary embodiment of the present invention comprises using an active layer, an ohmic contact layer, a source / drain electrode, a data line, a storage electrode, and a data pad using one diffraction exposure mask. It forms without using a 2nd, 3rd mask.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the above embodiments, but should be defined by the claims.

The liquid crystal display of the present invention as described above and a manufacturing method thereof have the following effects.

First, when the gate line / electrode / pad is formed of a single layer of AlNd, the process profile can be improved.

Second, by forming molybdenum having high corrosion resistance to chemicals without an additional mask process on the gate pad to be in contact with the gate pad electrode formed of a transparent metal, it is possible to prevent contact failure due to corrosion.

Third, since the liquid crystal display device can be formed using a lift-off method for forming the pixel electrode and three masks, the production cost can be saved.

1 is a plan view illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a cross-sectional view of a structure of a liquid crystal display device according to a first embodiment of the present invention.

3A to 3H are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention, taken along lines II ′, II-II ′, III-III ′, and IV-IV ′ of FIG. 1.

4 is a plan view showing a liquid crystal display according to a second embodiment of the present invention.

5 is a cross-sectional view of a structure of a liquid crystal display according to a second exemplary embodiment of the present invention.

6A through 6F are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a second exemplary embodiment, in which lines V-V ′, VI-VI ′, VIII-VIII, and VIII-VIII in FIG.

Explanation of symbols on the main parts of the drawings

30: lower substrate 31: gate line

31a: gate electrode 31b: gate pad

32: gate insulating film 33: amorphous silicon layer

33a: active layer 34: n + amorphous silicon layer

34a: ohmic contact layer 35: first metal layer

35a: data line 35b: source electrode

35c: drain electrode 35d: storage electrode

35e: Data pad 36, 38: Photoresist pattern

37: protective film 39a: first hole

39b, 39c: first and second contact holes 40: second metal layer

41 transparent conductive film 41a pixel electrode

41b: gate pad electrode 41c: data pad electrode

Claims (32)

A gate line formed as a single layer on the substrate and a gate pad extended to the gate line; A data line formed vertically and horizontally with the gate line to define a pixel area; A thin film transistor (TFT) formed of a gate electrode, a source electrode, and a drain electrode at an intersection of the gate line and the data line; A storage electrode overlapping one region of the front gate line; A data pad extending from the data line and formed at one end thereof; A protective film formed on an entire surface of the substrate including the thin film transistor; A pixel electrode formed in the pixel region such that the drain electrode is connected to one region of the storage electrode through an ohmic connection layer; A gate pad electrode connected to the gate pad; And a data pad electrode connected to the data pad. The method of claim 1, And the gate line, the gate electrode, and the gate pad are formed of a single layer of AlNd, which is an aluminum metal layer. The method of claim 1, The thin film transistor TFT may include the gate electrode protruding from one side of the gate line; The source electrode protruding from one side of the data line; The drain electrode formed to be spaced apart from the source electrode at a predetermined interval and connected to the pixel electrode; And a semiconductor pattern overlapping the gate electrode and the gate insulating layer therebetween and forming a channel between the source electrode and the drain electrode. The method of claim 1, And the data line, the source electrode and the drain electrode are formed of a double layer of AlNd / Mo, or AlNd is formed on a silicide layer. The method of claim 3, wherein The semiconductor pattern may include a channel portion between the source electrode and the drain electrode, and an active layer formed at a lower portion thereof to overlap the data line, the source electrode, and the drain electrode; And an ohmic contact layer formed between each of the data line, the source electrode, the drain electrode, and the active layer. The method of claim 1, The storage electrode and the data pad may be formed of a double layer of an amorphous silicon layer, an n + amorphous silicon layer, and AlNd / Mo, or an AlNd may be formed on an amorphous silicon layer, an n + amorphous silicon layer, and a silicide layer. Device. The method of claim 1, The passivation layer may include a first hole formed to expose one region and a pixel region of the drain electrode and the storage electrode; And first and second contact holes formed to expose one region of the gate pad and the data pad. The method of claim 7, wherein And molybdenum (Mo) is formed on the gate pad and the data pad where the first and second contact holes are formed. The method of claim 1, Molybdenum (Mo) is formed in one region where the pixel electrode, the drain electrode and the storage electrode is connected to form an ohmic connection layer of AlNd-Mo alloy. The method according to claim 1 or 7, And the pixel electrode extends in the first hole so as to be directly connected to the drain electrode and the upper portion of the storage electrode above the previous gate line. The method of claim 1, The thin film transistor TFT may include the gate electrode protruding from one side of the gate line, an active layer patterned on the gate insulating layer including the gate electrode by placing a gate insulating layer, and protruding from one side of the data line. And the source electrode overlapped with an upper portion of one side of the source electrode, and the drain electrode formed to be spaced apart from the source electrode at a predetermined interval and overlapped with an upper portion of the other side of the active layer. The method of claim 1, And the storage electrode and the data pad are made of AlNd formed on a double layer or a silicide layer of AlNd / Mo. Forming a gate line, a gate electrode, and a gate pad as a single layer on the substrate using a first mask process; Forming a data line arranged vertically and horizontally with the gate line to define a pixel region, a source electrode, a drain electrode, a data pad, and a storage electrode using a second mask process; Forming a passivation layer on the entire surface of the substrate; A photoresist pattern may be formed using a third mask process, and the first hole, the gate pad, and the first region may be formed on the passivation layer to expose one region and a pixel region of the drain electrode and the storage electrode using the photoresist pattern. A fourth step of forming first and second contact holes to expose one region of the data pad; A fifth step of forming an ohmic metal layer only on one region of the drain electrode and the storage electrode of the first hole and the gate pad and the data pad below the first and second contact holes; And a sixth step of forming a pixel electrode, a gate pad electrode, and a data pad electrode so as to be connected to the first hole, the first contact hole, and the second contact hole, respectively, via an ohmic metal layer. Manufacturing method. The method of claim 13, The first step may include forming a gate metal layer on the substrate; And patterning the gate metal layer using a photolithograph process and an etching process using the first mask. The method of claim 14, The gate metal layer is a manufacturing method of the liquid crystal display device, characterized in that the aluminum metal of AlNd. The method of claim 13, The second step, Sequentially forming an amorphous silicon layer, an n + amorphous silicon layer, and a first metal layer for forming a source / drain; Forming a photoresist pattern having a thin thickness in the channel portion by a photolithography process using the second mask having a diffraction exposure portion in the channel portion of the thin film transistor on the first metal layer; A source / drain pattern including the data line, the source electrode, and a drain electrode integrated with the source electrode by patterning the first metal layer by a wet etching process using the photoresist pattern, and data formed at one end of the data line Forming a storage electrode on the pad and one region of the previous gate line; Patterning the n + amorphous silicon layer and the amorphous silicon layer by a dry etching process using the same photoresist pattern to form an ohmic contact layer and an active layer; Ashing the photoresist pattern and then dry etching the mask with the mask to etch the source / drain pattern and the ohmic contact layer of the channel part to separate the source electrode and the drain electrode; And removing the photoresist pattern. The method of claim 16, The first metal layer is a liquid crystal display device comprising a double layer of AlNd / Mo or a single layer of AlNd. The method of claim 17, When the first metal layer is formed of a single layer of AlNd, And forming a silicide layer by depositing a metal such as Mo or Cr before forming the AlNd. The method of claim 13, Forming a second metal layer on the photoresist pattern including the first hole and the first and second contact holes; And etching the entire surface of the second metal layer by using a fruit-based etchant. The method of claim 19, The method of manufacturing a liquid crystal display device, characterized in that the fruit water etchant uses H 2 O 2 + CH 3 COO- (additive). The method of claim 19, The second metal layer is a method of manufacturing a liquid crystal display device, characterized in that using molybdenum (Mo). The method of claim 19, When the etching is performed using the permeate etchant, all of the second metal layer except for the upper portion of the drain electrode and the storage electrode of the first hole and the first and second contact holes is removed. Method of manufacturing the device. The method of claim 13, The sixth step may include forming a transparent conductive film on the entire surface of the substrate including the photoresist pattern; And removing the photoresist pattern by a lift-off process. The method of claim 13, And the pixel electrode is formed to be in direct contact with the storage electrode on an upper gate line of the drain electrode. The method of claim 23, The transparent conductive film may be formed of indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (Indium Zinc Oxide: IZO). Forming a gate line, a gate electrode, and a gate pad as a single layer on the substrate using a first mask process; A second step of forming an active layer and an ohmic contact layer on one region of the gate electrode by using a second mask process; A data line arranged vertically and horizontally with the gate line to define a pixel region using a third mask process, a source electrode connected to the data line, a drain electrode spaced at a predetermined distance from the source electrode, and at the data line A third step of extending a data pad formed at one end and a storage electrode formed at one region of a previous gate line; Forming a passivation layer on the entire surface of the substrate; A photoresist pattern is formed using a fourth mask process, and a first hole, the gate pad, and the first region are formed in the passivation layer to expose one region and a pixel region of the drain electrode and the storage electrode using the photoresist pattern. A fifth step of forming first and second contact holes to expose one region of the data pad; A sixth step of forming an ohmic metal layer only on one region of the drain electrode and the storage electrode of the first hole and the gate pad and the data pad below the first and second contact holes; And a seventh step of forming a pixel electrode, a gate pad electrode, and a data pad electrode so as to be connected to the first hole, the first contact hole, and the second contact hole, respectively, via an ohmic metal layer. Manufacturing method. The method of claim 26, The data line, the source electrode, the drain electrode, the storage electrode and the data pad are formed of a double layer of AlNd / Mo or a single layer of AlNd. The method of claim 27, In the case of forming a single layer of AlNd, And forming a silicide layer by depositing a metal such as Mo or Cr before forming the AlNd. The method of claim 26, Forming a metal layer on the photoresist pattern including the first hole and the first and second contact holes; And etching the entire surface of the second metal layer by using a fruit-based etchant. The method of claim 29, The method of manufacturing a liquid crystal display device, characterized in that the fruit water etchant uses H 2 O 2 + CH 3 COO- (additive). The method of claim 29, The metal layer is a method of manufacturing a liquid crystal display, characterized in that using molybdenum (Mo). The method of claim 26, The seventh step may include forming a transparent conductive film on the entire surface of the substrate including the photoresist pattern; And removing the photoresist pattern by a lift-off process.