KR20050067502A - Aho capacitor and method for making the same - Google Patents

Abstract

The present invention is to provide a capacitor and a method for manufacturing the capacitor that can prevent the interfacial reaction between the upper electrode and the AHO dielectric film and oxygen diffusion in the AHO dielectric film generated when the CVD TiN is deposited as the upper electrode, the capacitor manufacturing of the present invention The method includes depositing a lower electrode of a capacitor on a semiconductor substrate having a predetermined process, forming an AHO dielectric film on the lower electrode, forming a TiON protective layer on the AHO dielectric film surface, and on the TiON protective layer. Deposition of CVD TiN by depositing CVD TiN to form an upper electrode, the oxygen gas in the CVD TiN chamber in advance in the upper electrode deposition process and then TiCl ₄ gas to form a TiON protective layer Improves the leakage current characteristics of AHO capacitors by suppressing interfacial reactions with AHO dielectric films and preventing oxygen diffusion in AHO dielectric films. There is an effect that can be.

Description

AHIO capacitor and its manufacturing method {AHO CAPACITOR AND METHOD FOR MAKING THE SAME}

TECHNICAL FIELD The present invention relates to semiconductor manufacturing technology, and more particularly, to a capacitor and a manufacturing method thereof.

Recently, as the integration of memory products is accelerated due to the development of miniaturized semiconductor processing technology, the unit cell area is greatly reduced, and the operating voltage is being lowered. However, the charging capacity required for the operation of the memory device, despite the reduction in cell area, sufficient capacity of 25 fF / cell or more is continuously required to prevent the occurrence of soft errors and shortening of the refresh time. have. Therefore, in the case of the NO capacitor element for DRAM that uses a silicon nitride film (Si ₃ N ₄ ) deposited using Di-Chloro-Silane (DCS) gas as a dielectric, it has a three-dimensional electrode surface having a hemispherical structure with a large surface area. Despite the use of a form of charge storage electrode, its height continues to increase.

On the other hand, since NO capacitors have shown a limitation in securing the charge capacity required for next-generation DRAM capacitors of 256M or more, development of capacitor devices employing dielectric films having high dielectric constants such as Ta ₂ O ₅ , Al ₂ O ₃ , and HfO ₂ has been difficult. It is progressing in earnest.

However, Al ₂ O ₃ (ε = 8) has a limited dielectric constant, so there is a limitation in securing the charging capacity. HfO ₂ (ε = 20-25) having a relatively high dielectric constant has a low breakdown field strength. Since it is vulnerable to shock, the durability of the capacitor is inferior.

To solve this problem, a capacitor using a stacked structure of HfO ₂ and Al ₂ O ₃ , that is, an AHO (Al ₂ O ₃ / HfO ₂ ) dielectric film, has been proposed.

1 is a view showing the structure of a semiconductor memory device having an AHO capacitor according to the prior art.

As shown in FIG. 1, a word line 13 having a spacer 14 is formed on a semiconductor substrate 11 on which a field oxide film 12 for isolation between devices is formed, and includes a word line 13. The first interlayer insulating film 15 is formed on the entire surface of the semiconductor substrate 11.

In addition, a bit line 16b connected to the semiconductor substrate 11 between the word line 13 and the bit line contact 16a through the first interlayer insulating layer 15 is formed on the first interlayer insulating layer 15. The second interlayer insulating film 17 is formed on the first interlayer insulating film 15 including the bit line 16b.

A storage node contact (SNC) is formed through the second interlayer insulating layer 17 and the first interlayer insulating layer 15 to be connected to a part of the semiconductor substrate 11. The storage node contact is formed of a polysilicon plug 18. It is a laminated structure of titanium nitride / titanium (20/19) barrier.

An etch barrier film 21 is formed on the storage node contact and the second interlayer insulating film 17, and a capacitor oxide film 22 is formed on the etch barrier film 21, and the etch barrier film 21 and the capacitor are formed. The lower electrode 23 is formed in a storage node hole provided by the oxide layer 22. Here, the lower electrode 23 is electrically connected to the storage node contact.

The AHO dielectric film 24 is formed on the lower electrode 23 and the capacitor oxide film 22, and the upper electrode 25 is formed on the AHO dielectric film 24 to have a capacitor having a concave shape.

As shown in FIG. 1, a capacitor of a conventional semiconductor memory device includes a lower electrode 23 made of a metal material, an AHO dielectric film 24 on a lower electrode 23, and an upper electrode 25 on an AHO dielectric film 24. Being an AHO capacitor.

In the AHO capacitor as shown in FIG. 1, the upper electrode 25 uses a stacked structure of CVD TiN and PVD TiN or the same metal material as the lower electrode 23. When CVD TiN is used as the upper electrode 25 material, there is a problem in that an interfacial reaction between the AHO dielectric film 24 and CVD TiN occurs at a temperature of 500 ° C. or higher. In particular, oxygen in the AHO dielectric layer 24 diffuses into the CVD TiN, resulting in an increase in oxygen defects in the AHO dielectric layer 24, which causes an increase in leakage current.

Therefore, at present, since the substrate temperature is higher than 500 ° C. during CVD TiN deposition, a method capable of suppressing oxygen diffusion in the AHO dielectric film is required prior to depositing TiN.

The present invention has been made to solve the above-mentioned problems of the prior art, a capacitor capable of preventing the interfacial reaction between the upper electrode and the AHO dielectric film and oxygen diffusion in the AHO dielectric film generated when depositing CVD TiN as the upper electrode; Its purpose is to provide a process for its preparation.

The capacitor of the present invention for achieving the above object is characterized in that it comprises a lower electrode, an AHO dielectric film on the lower electrode, a TiON protective layer on the AHO dielectric film, and a CVD TiN upper electrode on the TiON protective layer.

In addition, the method of manufacturing a capacitor according to the present invention comprises the steps of depositing a lower electrode of a capacitor on a semiconductor substrate on which a predetermined process is completed, forming an AHO dielectric layer on the lower electrode, and forming a TiON protective layer on the surface of the AHO dielectric layer. And depositing CVD TiN on the TiON protective layer to form an upper electrode, wherein forming the TiON protective layer comprises depositing the CVD TiN in a deposition chamber of the CVD TiN. It is characterized in that the advance in advance in advance, wherein the forming the TiON protective layer, the step of transferring the semiconductor substrate on which the AHO dielectric film is formed to the deposition chamber of the CVD TiN, oxygen in the deposition chamber of the CVD TiN Flowing a gas, flowing TiCl ₄ , a raw material of the CVD TiN, and flowing NH ₃ , a reaction gas of the CVD TiN; Is characterized in that it comprises a step.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2 is a structural diagram of a semiconductor memory device having an AHO capacitor according to an embodiment of the present invention.

As shown in FIG. 2, a word line 33 having a spacer 34 is formed on a semiconductor substrate 31 on which a field oxide film 32 for separation between devices is formed, and includes a word line 33. The first interlayer insulating film 35 is formed on the entire surface of the semiconductor substrate 31.

A bit line 36b connected to the semiconductor substrate 31 between the word line 33 and the bit line contact 36a through the first interlayer insulating layer 35 is formed on the first interlayer insulating layer 35. The second interlayer insulating film 37 is formed on the first interlayer insulating film 35 including the bit line 36b.

A storage node contact (SNC) is formed through the second interlayer insulating layer 37 and the first interlayer insulating layer 35 to be connected to a part of the semiconductor substrate 31. The storage node contact is formed of a polysilicon plug 38. It is a laminated structure of titanium nitride / titanium (40/39) barrier.

An etch barrier film 41 is formed on the storage node contact and the second interlayer insulating film 37, and a capacitor oxide film 42 is formed on the etch barrier film 41, and the etch barrier film 41 and the capacitor are formed. The lower electrode 44 is formed in a storage node hole provided by the oxide layer 42. Here, the lower electrode 44 is electrically connected to the storage node contact.

An AHO dielectric layer 45 is formed on the lower electrode 44 and the capacitor oxide layer 42, and a TiON protective layer 45 is formed on the AHO dielectric layer 45, and an upper portion is formed on the TiON protective layer 45. An electrode 46 is formed.

As shown in FIG. 2, in the capacitor of the present invention, a TiON passivation layer 45 is inserted between the AHO dielectric layer 45 and the upper electrode 46. The TiON passivation layer 45 is an AHO dielectric layer when the upper electrode 46 is deposited. It is introduced to prevent the diffusion of oxygen in (45).

That is, when the upper electrode 46 is TiN (CVD TiN) using chemical vapor deposition, since the CVD TiN deposition proceeds at a high temperature of 500 ° C. or more, the AHO dielectric film 45 and the CVD TiN interface reaction necessarily occur. Forming the protective layer 45 prevents the interfacial reaction between the AHO dielectric film 45 and the CVD TiN, in particular, the diffusion of oxygen in the AHO dielectric film 45 into the CVD TiN.

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor memory device in accordance with an embodiment of the present invention.

As shown in FIG. 3A, after forming the field oxide film 32 for isolation between devices on the semiconductor substrate 31, a word line 33 having spacers 34 is formed on the semiconductor substrate 31. . At this time, although not shown, ion implantation for forming the source / drain of the transistor is performed in the semiconductor substrate 31 outside the word line 33 according to a known technique.

After the word line 33 is formed, the first interlayer insulating layer ILD 35 is formed on the semiconductor substrate 31, and then the bit line 36b is electrically connected to the semiconductor substrate 31 through the bit line contact 36a. ). First, the bit line contact 36a is formed by etching the first interlayer insulating layer 35 to form a contact hole, and filling the conductive layer in the contact hole, and the bit line 36b is formed on the bit line contact 36a. It is formed by depositing a conductive film for patterning.

The second interlayer insulating film 37 is formed on the first interlayer insulating film 35 on which the bit line 36b is formed, and then planarized.

Next, a storage node contact hole (not shown) exposing a portion (eg, a source and a drain of the transistor) of the semiconductor substrate 31 by etching the second interlayer insulating film 37 and the first interlayer insulating film 35 simultaneously. Form.

Subsequently, the storage node contact hole is filled with the storage node contact. Here, the storage node contact is formed in a stacked structure of a polysilicon plug 38 and a TiN / Ti (40/39) barrier. First, the polysilicon plug 38 is formed to have a structure in which the polysilicon film is deposited on the second interlayer insulating layer 37 until it fills the storage node contact hole, and then etched back to partially fill the storage node contact hole. Next, the TiN / Ti (40/39) barrier sequentially deposits Ti and TiN on the polysilicon plug 38 and then proceeds with chemical mechanical polishing (CMP) or etch back to the storage node contact hole, which is not yet filled. It is formed into a structure that completely fills the top.

As shown in FIG. 3B, after the etching barrier layer 41 is deposited on the second interlayer insulating layer 37 including the storage node contact, the capacitor oxide layer 42 is deposited on the etching barrier layer 41. Here, the etching barrier film 41 uses SiN, and the capacitor oxide film 42 uses BPSG, TEOS, HDP oxide film, USG, or PSG.

Next, the capacitor oxide film 42 is etched from the etching barrier film 41 until the etching stops, and then the etching barrier film 41 is etched to continuously open the upper portion of the TiN / Ti (40/39) barrier. The storage node hole 43 is formed.

As shown in FIG. 3C, after depositing TiN on the capacitor oxide film 42 including the storage node hole 43, the lower electrode 44 remaining in the storage node hole 43 is subjected to chemical mechanical polishing or etch back. ).

In the deposition process of TiN used as the lower electrode 44, TiCl ₄ is used as a raw material, NH ₃ is used as a reaction gas, and the flow rate of each gas is maintained at 10 sccm to 1000 sccm. The pressure in the reaction chamber is 0.1 to 10 torr, the deposition temperature is 500 to 650 ° C., and is deposited at a thickness of 200 kPa to 400 kPa.

Next, an AHO dielectric film 45 is deposited on the capacitor oxide film 42 including the lower electrode 44 by atomic layer deposition (ALD). Here, the AHO dielectric film 45 is a triple layer of HfO ₂ / Al ₂ O ₃ / HfO ₂ or a triple layer of Al ₂ O ₃ / HfO ₂ / Al ₂ O ₃ .

If the AHO dielectric film 45 is a triple layer of HfO ₂ / Al ₂ O ₃ / HfO ₂ , first repeat the cycle of depositing HfO ₂ , repeat the cycle of depositing Al ₂ O ₃ , and again form HfO ₂ . Repeat the deposition cycle. As raw materials of HfO ₂ and Al ₂ O ₃ , Hf (NEtMe) ₄ and TMA [Al (CH ₃ ) ₃ ] were used, respectively. Argon (Ar) and O ₃ were used as a carrier gas and an oxidizing agent, respectively. N ₂ is used as the purge gas.

First, in the AHO dielectric film 45, HfO _{2, which} is a lower layer, is deposited to a thickness of 30 kPa to 40 kPa by maintaining the substrate temperature at 250 ° C to 500 ° C and maintaining the pressure of the reaction chamber at 0.1torr to 1torr by repeating the following cycle. . For example, while maintaining a flow rate of argon (Ar), which is a carrier gas, at 150 sccm to 250 sccm, Hf (NEtMe) ₄ as a raw material is flowed for 0.1 to 10 seconds, and nitrogen (N ₂ ) gas is flowed at 200 sccm to 400 sccm. Maintaining the flow rate to purge for 3 seconds to 10 seconds, maintaining the flow rate of the oxidant O ₃ gas at 200 sccm to 500 sccm flow for 3 seconds to 10 seconds, nitrogen (N ₂ ) gas flow of 200 sccm to 400 sccm The cycle of purging for 3 to 10 seconds is maintained as one cycle, and the cycle is repeated to deposit HfO ₂ of a required thickness.

Next, in the AHO dielectric film 45, Al ₂ O _{3, which} is an intermediate layer, maintains the substrate temperature at 250 ° C. to 500 ° C., maintains the pressure in the reaction chamber at 0.1 to 1 tor, and repeats the following cycle. To be deposited. For example, while maintaining a flow rate of argon (Ar), which is a carrier gas, at 20 sccm to 100 sccm, TMA [Al (CH ₃ ) ₃ ], which is a raw material, is flowed for 0.1 to 5 seconds, and nitrogen (N ₂ ) gas is flowed. Maintaining at a flow rate of 50 sccm to 300 sccm and purging for 0.1 to 5 seconds, maintaining a flow rate of oxidant O ₃ at a flow rate of 200 sccm to 500 sccm for 3 seconds to 10 seconds, and nitrogen (N ₂ ) gas at 300 sccm The step of purging for 0.1 seconds to 5 seconds while maintaining the flow rate at -1000 sccm is performed as one cycle, and this cycle is repeatedly performed to deposit Al ₂ O ₃ having a required thickness (5 kPa to 20 kPa).

Finally, in the AHO dielectric film 45, HfO _{2, which} is an upper layer, is deposited using the same method as that of HfO ₂ , which is a lower layer, and is deposited to have a thickness of 30 kPa to 40 kPa.

As shown in FIG. 3D, after depositing the AHO dielectric layer 45, the semiconductor substrate 31 is transferred to a chamber for depositing TiN as the upper electrode. Here, the chamber for depositing TiN as the upper electrode is a chemical vapor deposition (CVD) chamber. Hereinafter, TiN deposited in the chemical vapor deposition chamber is abbreviated as CVD TiN.

Prior to depositing CVD TiN, oxygen (O ₂ ) gas is flowed in advance in situ at the deposition temperature of CVD TiN into the chemical vapor deposition chamber to prevent oxygen diffusion in the AHO dielectric film 45. The above steps can be described as pre-oxygen flow (O ₂ pre-flow) processes. At this time, the deposition temperature of CVD TiN is 500 ° C to 650 ° C, the flow rate of oxygen gas to be flowed is 10sccm to 30sccm, and the flow time of oxygen gas is 5 seconds to 10 seconds.

After the oxygen gas flows in advance as above, the process of depositing CVD TiN is performed.

First, only TiCl ₄ , which is a raw material of CVD TiN, is flowed in a chamber in which oxygen gas flows for 5 seconds to 20 seconds, and NH ₃ , which is a carrier gas, is then flown to form a TiON protective layer 46 on the surface of the AHO dielectric layer 45. To form. That is, the TiON protective layer 46 is TiON formed by reaction of oxygen gas, TiCl ₄ and NH ₃ .

Subsequently, a chemical vapor deposition (CVD) process of the CVD TiN 47 which becomes the upper electrode is performed. At this time, when the CVD TiN 47 is deposited, TiCl ₄ is used as the raw material, NH ₃ gas is used as the reaction gas, and the flow rates of the raw material and the reactant gas flowing at the same time are maintained at 10 sccm to 1000 sccm, respectively. The deposition temperature is maintained at 500 ° C to 650 ° C, the deposition pressure is maintained at 0.1torr to 2torr, and the final deposition thickness is 100mW to 500mW.

Next, TiN (hereinafter referred to as PVD TiN) is deposited on the CVD TiN 47 by using physical vapor deposition. At this time, the PVD TiN 48 is also an upper electrode and is deposited to have a thickness of 400 mW to 1000 mW.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above is an interface of the AHO dielectric film during CVD TiN deposition by forming a TiON-type protective layer by pre-flowing oxygen gas in the CVD TiN chamber in the upper electrode deposition process of the AHO capacitor manufacturing process and then flowing TiCl ₄ gas. In addition to suppressing the reaction, it is possible to prevent oxygen diffusion in the AHO dielectric film, thereby improving leakage current characteristics of the AHO capacitor.

1 is a view showing the structure of a semiconductor memory device having an AHO capacitor according to the prior art;

2 illustrates a structure of a semiconductor memory device including an AHO capacitor according to an embodiment of the present invention;

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor memory device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 field oxide film

33: wordline 34: spacer

35: first interlayer insulating film 36b: bit line

37: second interlayer insulating film 38: polysilicon plug

40/39: TiN / Ti 41: etching barrier film

42: capacitor oxide film 44: lower electrode

45: AHO dielectric film 46: TiON protective layer

47: CVD TiN 48: PVD TiN

Claims (9)

Lower electrode; AHO dielectric film on the lower electrode: A TiON protective layer on the AHO dielectric layer; And CVD TiN top electrode on the TiON protective layer Capacitor comprising a. The method of claim 1, The AHO dielectric film, A capacitor comprising a triple layer of HfO ₂ / Al ₂ O ₃ / HfO ₂ or a triple layer of Al ₂ O ₃ / HfO ₂ / Al ₂ O ₃ . Depositing a lower electrode of the capacitor on the semiconductor substrate on which the predetermined process is completed; Forming an AHO dielectric layer on the lower electrode; Forming a TiON protective layer on a surface of the AHO dielectric layer; And Depositing CVD TiN on the TiON protective layer to form an upper electrode Capacitor manufacturing method comprising a. The method of claim 3, Forming the TiON protective layer, Before proceeding to deposit the CVD TiN in the deposition chamber of the CVD TiN capacitor manufacturing method. The method of claim 3, Forming the TiON protective layer, Transferring the semiconductor substrate on which the AHO dielectric film is formed to a deposition chamber of the CVD TiN; Flowing oxygen gas into the deposition chamber of the CVD TiN; Flowing TiCl ₄ which is a raw material of the CVD TiN; And Flowing NH ₃ , the reaction gas of the CVD TiN; Capacitor manufacturing method comprising a. The method of claim 5, Forming the TiON protective layer, And the oxygen gas is maintained at a flow rate of 10 sccm to 30 sccm. The method of claim 5, Forming the TiON protective layer, The process of manufacturing a capacitor, characterized in that proceeding at the same temperature as the deposition temperature of the CVD TiN, the deposition temperature is 500 ℃ to 650 ℃. The method of claim 3, The CVD TiN is, A method of manufacturing a capacitor, comprising using TiCl ₄ as a raw material, NH ₃ as a reaction gas, and maintaining the deposition temperature at 500 ° C to 650 ° C. The method of claim 3, And depositing PVD TiN on the CVD TiN.