KR20040059442A - Method of manufacturing capacitor for semiconductor device - Google Patents

Method of manufacturing capacitor for semiconductor device Download PDF

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KR20040059442A
KR20040059442A KR1020020086190A KR20020086190A KR20040059442A KR 20040059442 A KR20040059442 A KR 20040059442A KR 1020020086190 A KR1020020086190 A KR 1020020086190A KR 20020086190 A KR20020086190 A KR 20020086190A KR 20040059442 A KR20040059442 A KR 20040059442A
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film
semiconductor device
capacitor manufacturing
thin film
lower electrode
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KR1020020086190A
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Korean (ko)
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이기정
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to enhance the capacitance and to reduce the leakage current by using a double dielectric film. CONSTITUTION: A lower electrode(13) is formed on a semiconductor substrate(10) with a plug(12). An alumina(Al2O3) thin film(14A) as the first dielectric film is formed on the lower electrode. A titanium oxide(TiO2) layer(14B) as the second dielectric film is formed on the first dielectric film. Then, an upper electrode is formed on the double dielectric film.

Description

반도체 소자의 캐패시터 제조방법{METHOD OF MANUFACTURING CAPACITOR FOR SEMICONDUCTOR DEVICE}METHODS OF MANUFACTURING CAPACITOR FOR SEMICONDUCTOR DEVICE

본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 특히 티타늄산화막/알루미나박막(TiO2/Al2O3) 이중 유전막 구조를 갖는 반도체 소자의 캐패시터 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly to a method for manufacturing a capacitor of a semiconductor device having a titanium oxide film / alumina thin film (TiO 2 / Al 2 O 3 ) double dielectric film structure.

일반적으로, 메모리셀(memory cell)에 사용되는 캐패시터는 스토리지 (storage node)용 하부전극, 유전막, 및 플레이트(plate)용 상부전극으로 이루어지는데, 최근에는 미세화된 반도체 공정기술의 발달로 인한 소자의 고집적화에 따라 단위 셀면적이 크게 감소하고 동작전압의 저전압화가 이루어지고 있다. 그러나, 셀면적 감소에도 불구하고 소프트에러(soft error) 발생 및 리프레시시간(refresh time) 단축 등을 방지하기 위해서는 셀당 약 25fF 이상의 충분한 캐패시터 용량을 확보하여야 한다. 이에 따라, 예컨대 유전막으로서 DCS(Di-Chloro-Silane) 개스를 사용하여 증착하는 실리콘질화막(Si3N4) 등을 사용하는 NO(Nitride-Oxide)-캐패시터의 경우에는, 캐패시터 용량 확보를 위하여 표면적이 큰 반구형 구조의 전극표면을 갖는 3차원 형태로 하부전극을 형성하고 캐패시터 높이를 증가시키고 있다. 그러나, 캐패시터 높이가 증가하게 되면 셀영역과 주변영역 사이의 큰 단차로 인하여 후속 노광공정시 초점심도(depth of forcus)가 확보되지 않아 공정에 악영향을 미치기 때문에 캐패시터 용량확보에 한계가 있다.In general, a capacitor used in a memory cell includes a lower electrode for a storage node, a dielectric layer, and an upper electrode for a plate. Due to the high integration, the unit cell area is greatly reduced and the operating voltage is lowered. However, despite the reduction in cell area, sufficient capacitor capacity of about 25 fF or more per cell should be ensured in order to prevent soft errors and refresh time. Thus, for example, in the case of a nitride-oxide (NO) -capacitor using a silicon nitride film (Si 3 N 4 ) or the like deposited using a Di-Chloro-Silane (DCS) gas as a dielectric film, the surface area is secured to secure a capacitor capacity. The lower electrode is formed in a three-dimensional shape having the electrode surface of the large hemispherical structure, and the capacitor height is increased. However, when the capacitor height is increased, a depth of forcus is not secured during a subsequent exposure process due to a large step between the cell region and the peripheral region, which adversely affects the process, thereby limiting the capacitor capacity.

따라서, 최근에는 유전막으로서 탄탈륨산화막(Ta2O5)과 같은 고유전율을 가지는 산화막을 박막으로 적용한 Ta2O5-캐패시터를 개발하여 사용하고 있다. 그러나,Ta2O5박막은 불안정한 화학양론비(stoichiometry)를 가지기 때문에 Ta와 O의 조성비 차이에 기인한 치환형 Ta 원자(vacancy atom)가 Ta2O5박막내에 국부적으로 존재하는데 이를 완전하게 제거할 수 있는 방법이 없다. 또한, Ta2O5박막은 일반적으로 전구체(precursor)인 Ta(OC2H5)5의 유기물과 O2또는 N2O 개스를 반응시켜 형성하는데, 이러한 반응에 의해 Ta2O5박막 내에 불순물인 탄소(C)원자와 C, CH4, C2H4와 같은 탄소화합물 및 H2O가 함께 존재하게 되어 Ta2O5박막 내에 탄소원자, 이온(ion) 및 라디칼(radical)이 불순물로 존재함으로써, 캐패시터의 누설전류 증가 및 유전특성 열화 등의 문제를 야기시키게 된다. 또한, Ta2O5박막은 비정질상태로 증착이 이루어지기 때문에 결정화를 위하여 후속으로 열처리 공정을 수행하여야 하는데, 이러한 열처리 공정시 하부전극인 폴리실리콘막과의 계면반응에 의해 SiO2(ε= 3.85)와 같은 저유전율의 계면산화막이 형성되어 사실상 등가산화막 두께(Tox)를 30Å 이하로 낮출 수가 없기 때문에 고집적화에 대응하는 충분한 캐패시터 용량을 확보하는데 그 한계가 있다.Therefore, recently, as a dielectric film, a Ta 2 O 5 -capacitor using an oxide film having a high dielectric constant such as a tantalum oxide film (Ta 2 O 5 ) as a thin film has been developed and used. However, since Ta 2 O 5 thin films have unstable stoichiometry, substitutional Ta atoms due to differences in the composition ratios of Ta and O are present locally in the Ta 2 O 5 thin films. There is no way to do it. In addition, a Ta 2 O 5 thin film is generally formed by reacting an organic substance of Ta (OC 2 H 5 ) 5, which is a precursor, with O 2 or N 2 O gas, and impurities in the Ta 2 O 5 thin film by this reaction. Phosphorus carbon (C) atoms, carbon compounds such as C, CH 4 , C 2 H 4 and H 2 O are present together to form carbon atoms, ions and radicals as impurities in the Ta 2 O 5 thin film. By being present, problems such as an increase in the leakage current of the capacitor and deterioration of the dielectric characteristics are caused. In addition, since the Ta 2 O 5 thin film is deposited in an amorphous state, a heat treatment process must be subsequently performed for crystallization. In this heat treatment process, SiO 2 (ε = 3.85 is caused by an interfacial reaction with a polysilicon film as a lower electrode. Since an interfacial oxide film having a low dielectric constant, such as), cannot effectively reduce the equivalent oxide film thickness (Tox) to 30 kPa or less, there is a limit to securing sufficient capacitor capacity corresponding to high integration.

본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 고집적화에 대응하는 충분한 캐패시터 용량을 확보함과 동시에 누설전류 및 유전 특성 등을 향상시킬 수 있는 반도체 소자의 캐패시터 제조방법을 제공하는데 그목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and provides a method of manufacturing a capacitor of a semiconductor device capable of securing sufficient capacitor capacity corresponding to high integration and improving leakage current and dielectric properties. The purpose is.

도 1a 및 도 1b는 본 발명의 실시예에 따른 반도체 소자의 캐패시터 제조방법을 설명하기 위한 단면도.1A and 1B are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with an embodiment of the present invention.

도 2는 본 발명의 실시예에서 원자층증착에 의한 알루미나 박막의 증착과정을 설명하기 위한 도면.2 is a view for explaining the deposition process of the alumina thin film by atomic layer deposition in an embodiment of the present invention.

※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing

10 : 반도체 기판 11 : 층간절연막10 semiconductor substrate 11 interlayer insulating film

12 : 플러그 13 : 하부전극12 plug 13 lower electrode

14 : 유전막 14A : Al2O3박막14: dielectric film 14A: Al 2 O 3 thin film

14B : TiO2막14B: TiO 2 membrane

상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 반도체 기판 상에 하부전극을 형성하는 단계; 하부전극 표면에 제 1 유전막으로서 알루미나 박막을 형성하는 단계; 알루니마 박막 상부에 제 2 유전막으로서 티타늄산화막을 형성하여 티타늄산화막/알루미나 박막의 이중막으로 이루어진 유전막을 형성하는 단계; 및 유전막 상부에 상부전극을 형성하는 단계를 포함하는 반도체 소자의 캐패시터 제조방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, the object of the present invention comprises the steps of forming a lower electrode on a semiconductor substrate; Forming an alumina thin film as a first dielectric layer on the lower electrode surface; Forming a titanium oxide film as a second dielectric film on the alumina thin film to form a dielectric film composed of a double layer of a titanium oxide film / alumina thin film; And forming a top electrode on the dielectric layer.

여기서, 알루미나 박막과 티타늄산화막의 형성은 각각 증착 및 결정화를 위한 열처리의 2단계 공정으로 이루어지는데, 알루미나 박막은 10 내지 20Å의 두께로 증착하고, 알루미나 박막의 증착은 TMA(Al(CH3)3)의 소오스 개스와 O2또는 O3의 반응개스를 사용하여 저압-화학기상증착 또는 원자층증착으로 수행하고, 알루미나 박막의 열처리는 급속열처리로 800 내지 900℃의 온도에서 N2 분위기로 30 내지 120초 동안 수행한다. 또한, 티타늄산화막은 30 내지 100Å의 두께로 형성하고, 티타늄산화막의 증착은 Ti 성분의 소오스 개스와 O2또는 O3의 반응개스를 사용하여 저압-화학기상증착 또는 원자층증착에 의해 300 내지 600℃의 온도 및 0.1 내지 5torr의 압력하에서 수행하고, 티타늄산화막의 열처리는 N2O 또는 O2분위기에서 노어닐링 또는 급속열처리로 수행한다. 바람직하게 노어닐링은 600 내지 800℃의 온도에서 5분 내지 120분 정도 수행하고, 급속열처리는 800 내지 900℃의 온도에서 30 내지 120초 동안 수행한다.Here, the alumina thin film and the titanium oxide film is formed by a two-step process of heat treatment for deposition and crystallization, respectively, the alumina thin film is deposited to a thickness of 10 to 20Å, the deposition of the alumina thin film is TMA (Al (CH 3 ) 3 ) Is performed by low pressure-chemical vapor deposition or atomic layer deposition using a source gas of O 2 or a reaction gas of O 3 , and heat treatment of the alumina thin film is performed by rapid heat treatment at a temperature of 800 to 900 ° C. in an N 2 atmosphere at 30 to 120 degrees. Run for seconds. In addition, the titanium oxide film is formed to a thickness of 30 to 100Å, the deposition of the titanium oxide film is 300 to 600 by low pressure-chemical vapor deposition or atomic layer deposition using a source gas of Ti component and a reaction gas of O 2 or O 3 . It is carried out at a temperature of ℃ and a pressure of 0.1 to 5 torr, heat treatment of the titanium oxide film is carried out by furnace annealing or rapid heat treatment in N 2 O or O 2 atmosphere. Preferably, annealing is performed at a temperature of 600 to 800 ° C. for about 5 to 120 minutes, and rapid heat treatment is performed at a temperature of 800 to 900 ° C. for 30 to 120 seconds.

또한, 하부전극을 형성하는 단계와 알루미나 박막을 형성하는 단계 사이에, 하부전극의 표면을 세정처리하는 단계와 하부전극의 표면을 질화처리하는 단계를 더 포함한다.The method may further include cleaning the surface of the lower electrode and nitriding the surface of the lower electrode between the forming of the lower electrode and the forming of the alumina thin film.

또한, 하부전극은 도핑된 폴리실리콘막 또는 금속막으로 이루어지고, 상부전극은 금속막의 단일막 또는 도핑된 폴리실리콘막/금속막의 이중막으로 이루어지는데, 바람직하게 금속막은 TiN막, TaN막, W막, WN막, Ru막, RuO2막, Ir막, IrO2막 및 Pt막 중 선택되는 하나의 막이다.In addition, the lower electrode is made of a doped polysilicon film or a metal film, and the upper electrode is made of a single film of a metal film or a double film of a doped polysilicon film / metal film. Preferably, the metal film is a TiN film, a TaN film, or a W film. One of the film, the WN film, the Ru film, the RuO 2 film, the Ir film, the IrO 2 film, and the Pt film is selected.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

도 1a 및 도 1b는 본 발명의 실시예에 따른 반도체 소자의 캐패시터 제조방법을 설명하기 위한 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with an embodiment of the present invention.

도 1a를 참조하면, 트랜지스터 및 비트라인 등의 소정의 공정이 완료된 반도체 기판(10) 상에 실리콘산화막(SiO2)으로 층간절연막(11)을 형성하고, 기판(10)의 일부가 노출되도록 층간절연막(11)을 식각하여 스토리지노드용 콘택홀을 형성한다. 그 다음, 콘택홀에 매립되도록 폴리실리콘막 등의 도전막을 증착하고, 층간절연막(11)의 표면이 노출되도록 화학기계연마(Chemical MechanicalPolishing; CMP) 공정으로 도전막을 전면식각하여 서로 분리시켜 기판(10)과 콘택하는 플러그(12)를 형성한다. 여기서, 플러그(12)는 스토리지노드 콘택으로 작용한다. 그 다음, 기판 전면 상에 캐패시터 산화막(미도시)을 형성하고, 플러그(12)가 노출되도록 캐패시터 산화막을 식각하여 캐패시터용 홀을 형성한다. 그 후, 홀 표면 및 캐패시터 산화막 표면 상에 하부전극용 물질로서 도핑된 폴리실리콘막을 저압-화학기상증착(Low Pressure-Chemical Vapor Deposition; LP-CVD)으로 200 내지 500Å의 두께로 형성하고, 캐패시터 산화막의 표면이 노출되도록 CMP 공정이나 에치백 공정으로 폴리실리콘막을 전면식각하여 서로 분리시킨 다음, 캐패시터 산화막을 제거하여 폴리실리콘막으로 이루어진 실린더 구조(cylinder structure)의 하부전극(13)을 형성한다. 여기서, 폴리실리콘막 대신 금속막으로도 하부전극(13)을 형성할 수 있는데, 이때 금속막은 TiN막, TaN막, W막, WN막, Ru막, RuO2막, Ir막, IrO2막 및 Pt막 중 선택되는 하나의 막을 이용하여 CVD, ALD를 포함한 플라즈마보조 (Plasma Enhnaced)-CVD, 또는 RF 자기 스퍼터링(magnetic sputtering)으로 형성한다.Referring to FIG. 1A, an interlayer insulating film 11 is formed of a silicon oxide film (SiO 2 ) on a semiconductor substrate 10 where predetermined processes such as transistors and bit lines are completed, and an interlayer is exposed so that a part of the substrate 10 is exposed. The insulating layer 11 is etched to form contact holes for storage nodes. Subsequently, a conductive film such as a polysilicon film is deposited so as to be filled in the contact hole, and the surface of the interlayer insulating film 11 is exposed to the substrate 10 by etching the entire surface by chemical mechanical polishing (CMP). ) Is formed in contact with the plug 12. Here, plug 12 acts as a storage node contact. Next, a capacitor oxide film (not shown) is formed on the entire surface of the substrate, and the capacitor oxide film is etched to expose the plug 12 to form holes for the capacitor. Thereafter, a polysilicon film doped as a material for the lower electrode on the hole surface and the capacitor oxide film surface was formed to a thickness of 200 to 500 kPa by Low Pressure-Chemical Vapor Deposition (LP-CVD) to form a capacitor oxide film. The polysilicon layers are etched by the CMP process or the etch back process to expose the surface of the polysilicon layer, and then the capacitor oxide layer is removed to form the lower electrode 13 of the cylinder structure made of the polysilicon layer. Here, the lower electrode 13 may be formed of a metal film instead of a polysilicon film, wherein the metal film may be a TiN film, a TaN film, a W film, a WN film, a Ru film, a RuO 2 film, an Ir film, an IrO 2 film, and the like. One of the Pt films is used to form CVD, Plasma Enhnaced-CVD including ALD, or RF magnetic sputtering.

도 1b를 참조하면, 하부전극(13)의 표면을 세정처리하여 하부전극(13) 표면에 발생된 자연산화막(SiO2)을 제거한 후, 하부전극(13) 표면을 질화 (Nitrification) 처리하여 자연산화막 형성을 방지함과 동시에 후속 Al2O3박막의 증착시 발생되는 저유전산화막(SiO2) 등의 형성을 최소화한다. 여기서, 세정처리는인-시튜(in-situ) 또는 엑스-시튜(ex-situ) 방식으로 HF 기체 또는 H2O2와 초순수가 첨가된 희석용액인 HF 용액을 사용하여 수행하거나, H2O2와 초순수가 첨가된 희석용액인 NH4OH 용액이나 H2O2와 초순수가 첨가된 희석용액인 H2SO4용액을 사용하여 수행한다. 또한, 질화처리는 인-시튜 또는 엑스-시튜 방식으로 750 내지 950℃의 온도 및 NH3분위기 하에서 30 내지 120초 동안 RTP를 수행하는 급속열질화(Rapid Thermal Nitrification; RTN)로 수행하거나, 플라즈마를 이용하여 300 내지 500℃의 온도 및 NH3분위기 하에서 열처리를 수행하는 플라즈마 질화로 수행한다.Referring to FIG. 1B, the surface of the lower electrode 13 is cleaned to remove the natural oxide film (SiO 2 ) generated on the surface of the lower electrode 13, and the surface of the lower electrode 13 is nitrified. At the same time to prevent the formation of the oxide film and minimize the formation of a low dielectric oxide film (SiO 2 ) and the like generated during the deposition of the subsequent Al 2 O 3 thin film. Here, the cleaning treatment is carried out using HF gas or HF solution, which is a dilute solution in which H 2 O 2 and ultrapure water are added in-situ or ex-situ, or H 2 O. This is done using NH 4 OH solution, which is a dilute solution with 2 and ultrapure water, or H 2 SO 4 solution, which is diluted solution with H 2 O 2 and ultrapure water. In addition, the nitriding treatment is performed by Rapid Thermal Nitrification (RTN), which performs RTP for 30 to 120 seconds in a temperature of 750 to 950 ° C. and NH 3 atmosphere in an in-situ or ex-situ manner, or plasma It is carried out by plasma nitridation using a heat treatment under a temperature of 300 to 500 ℃ and NH 3 atmosphere.

그 다음, 표면처리된 하부전극(13) 표면 상에 인-시튜 또는 엑스-시튜 방식으로 제 1 유전막으로서 알루미나(Al2O3) 박막(14A, ε= 9∼10)을 10 내지 20Å의 두께로 형성하고, Al2O3박막(14A) 상부에 제 2 유전막으로서 비교적 유전율이 높은 티타늄산화(TiO2)막(14B, ε= 40∼80)을 30 내지 100Å, 바람직하게 50 내지 80Å의 두께로 형성하여 TiO2/Al2O3의 이중막으로 이루어진 캐패시터의 유전막(14)을 형성한다. 즉, 제 1 유전막인 Al2O3박막(14A)은 종래의 Ta2O5박막에 비해 유전율을 낮지만, 페롭스카이트(perovskite)형 구조로 이루어지면서 공유결합되어 있기 때문에 구조적으로 매우 안정하므로, 열처리 공정시 하부전극(13)의 폴리실리콘막과의 계면반응을 방지할 수 있고, Al2O3박막(14A) 상부에 비교적 유전율이 높은 TiO2막(14B)을 형성하기 때문에 고집적화에 대응하는 충분한 캐패시터 용량을 확보할 수 있다.Then, the alumina (Al 2 O 3 ) thin film 14A (ε = 9 to 10) as a first dielectric film was formed on the surface of the surface-treated lower electrode 13 in an in-situ or x-situ manner with a thickness of 10 to 20 kPa. A titanium oxide (TiO 2 ) film 14B (ε = 40 to 80) having a relatively high dielectric constant as a second dielectric film on the Al 2 O 3 thin film 14A and having a thickness of 30 to 100 kPa, preferably 50 to 80 kPa. To form a dielectric film 14 of a capacitor consisting of a double film of TiO 2 / Al 2 O 3 . That is, although the Al 2 O 3 thin film 14A, which is the first dielectric film, has a lower dielectric constant than the conventional Ta 2 O 5 thin film, it is structurally very stable because it is covalently bonded in a perovskite type structure. In the heat treatment process, interfacial reaction with the polysilicon film of the lower electrode 13 can be prevented, and since TiO 2 film 14B having a relatively high dielectric constant is formed on the Al 2 O 3 thin film 14A, high integration is supported. Sufficient capacitor capacity can be ensured.

여기서, Al2O3박막(14A) 및 TiO2막(14B)의 형성은 각각 증착 및 결정화를 위한 열처리의 2단계 공정으로 이루어지는데, 먼저 Al2O3박막(14A)의 증착은 TMA(Al(CH3)3)와 같은 Al 성분의 소오스 개스와 O2또는 O3의 반응개스를 사용하여 LP-CVD 또는 원자층증착(Atomic Layer Deposition; ALD)으로 수행한다. 이때, 소오스 개스로서 Al(OC2H5)3용액과 같이 Al을 함유한 유기금속화합물의 전구체를 사용할 수도 있는데, 이 경우에는 MFC(Mass Flow Controller)와 같은 유량조절기를 통해 증발기(evaporizer) 또는 증발관(evaporation tube)으로 공급된 일정량의 전구체를 150 내지 300℃의 온도에서 증발시켜서 얻는다. 또한, Al2O3박막(14A)의 열처리는 급속열처리(Rapid Thermal Process; RTP)로 800 내지 900℃의 온도에서 N2 분위기로 30 내지 120초 동안 수행하여 Al2O3박막(14A)을 결정화시킨다. 더욱 바람직하게, ALD에 의한 Al2O3박막(14A)의 증착은, 도 2에 도시된 바와 같이, TMA(Al(CH3)3)의 소오스 개스 (A)를 반응로로 플로우(flow)시킨 후, N2 또는 Ar 개스로 반응로를 퍼지한 다음, O2또는 O3의 반응개스(B)를 반응로로 플로우시킨 후, 다시 N2 또는 Ar 개스로 반응로를 퍼지한 다음, 이러한 과정의 주기(cycle)를 소정의 두께까지 반복 수행하는 공정으로 이루어진다. 한편, Al2O3박막(14A)을 증착하기 전에 인-시튜 플라즈마를 사용하여 일차적으로 N2O 또는 O2분위기에서 저온 열처리를 수행하여 하부전극(13)의 댕글링본드(dangling bond)에 기인한 구조적 결함(defect) 내지는 구조적 불균일성(homogeneity)을 개선하여 누설전류 특성을 향상시킬 수도 있다.Here, the formation of the Al 2 O 3 thin film 14A and the TiO 2 film 14B consists of a two-step process of heat treatment for deposition and crystallization, respectively. First, deposition of the Al 2 O 3 thin film 14A is performed by TMA (Al It is carried out by LP-CVD or Atomic Layer Deposition (ALD) using a source gas of Al component such as (CH 3 ) 3 ) and a reaction gas of O 2 or O 3 . In this case, a precursor of an organometallic compound containing Al, such as Al (OC 2 H 5 ) 3 solution, may be used as the source gas. In this case, an evaporator or a flow controller such as a mass flow controller (MFC) may be used. An amount of precursor supplied to the evaporation tube is obtained by evaporation at a temperature of 150 to 300 ° C. In addition, the heat treatment of the Al 2 O 3 thin film 14A is performed by a rapid thermal treatment (RTP) at a temperature of 800 to 900 ° C. for 30 to 120 seconds in an N 2 atmosphere to crystallize the Al 2 O 3 thin film 14A. Let's do it. More preferably, the deposition of the Al 2 O 3 thin film 14A by ALD flows a source gas A of TMA (Al (CH 3 ) 3 ) into the reactor, as shown in FIG. 2. After purging, the reactor is purged with N 2 or Ar gas, and then the reaction gas B of O 2 or O 3 is flowed into the reactor, and the reactor is purged again with N 2 or Ar gas. The cycle is repeated to a predetermined thickness. Meanwhile, before depositing the Al 2 O 3 thin film 14A, a low temperature heat treatment may be performed first in an N 2 O or O 2 atmosphere using an in-situ plasma to dangling bonds of the lower electrode 13. It is also possible to improve the leakage current characteristics by improving the structural defects or structural homogeneity due to.

다음으로, TiO2막(14B)의 증착은 Ti 성분의 소오스 개스와 O2또는 O3의 반응개스를 사용하여 LP-CVD 또는 ALD로 300 내지 600℃의 온도 및 0.1 내지 5torr의 압력하에서 수행한다. 이때, Ti 성분의 소오스 개스는 MFC와 같은 유량조절기를 통해 증발기 또는 증발관으로 공급된 일정량의 Ti[OCH(CH3)2]4용액 또는 기타 Ti함유 유기금속 전구체를 150 내지 200℃의 온도에서 증발시켜서 얻는다. 또한, TiO2막(14B)의 열처리는 N2O 또는 O2분위기에서 노어닐링(furnace annealing) 또는 RTP로 수행하여 TiO2막(14B) 내에 존재하는 탄소 불순물을 제거함과 동시에 결정화를 유도하여 유전성을 향상시킨다. 바람직하게, 노어닐링은 600 내지 800℃의 온도에서 5분 내지 120분 정도 수행하고, RTP는 800 내지 900℃의 온도에서 30 내지 120초 동안 수행한다. 이때, 이미 결정화된 상태로 존재하는 Al2O3박막(14A)이 소정의 확산배리어(diffusion barrier)로서 작용하여 활성산소가 TiO2막(14B)을 관통하여 하부전극(13)으로 확산하는 것을 방지하기 때문에, 하부전극(13)의 폴리실리콘막과의 계면반응을 야기시키지 않으면서 열처리 수행이 용이해짐으로써, TiO2막(14B) 내의 탄소 불순물을 제거하는 것이 가능해진다.Subsequently, the deposition of the TiO 2 film 14B is performed by LP-CVD or ALD at a temperature of 300 to 600 ° C. and a pressure of 0.1 to 5 torr using a source gas of Ti component and a reaction gas of O 2 or O 3 . . At this time, the source gas of the Ti component is a predetermined amount of Ti [OCH (CH 3 ) 2 ] 4 solution or other Ti-containing organometallic precursor supplied to an evaporator or an evaporator via a flow controller such as MFC at a temperature of 150 to 200 ℃ Obtained by evaporation. Further, the heat treatment of the TiO 2 film (14B) is a furnace anneal (furnace annealing), or by performing a RTP dielectric to induce crystallization of carbon impurities present in the TiO 2 film (14B) and at the same time removing from the N 2 O or O 2 atmosphere To improve. Preferably, the annealing is performed for about 5 to 120 minutes at a temperature of 600 to 800 ℃, RTP is carried out for 30 to 120 seconds at a temperature of 800 to 900 ℃. At this time, the Al 2 O 3 thin film 14A, which is already in the crystallized state, acts as a predetermined diffusion barrier, and active oxygen diffuses through the TiO 2 film 14B to the lower electrode 13. Therefore, the heat treatment can be easily performed without causing an interfacial reaction with the polysilicon film of the lower electrode 13, thereby making it possible to remove carbon impurities in the TiO 2 film 14B.

그 후, 도시되지는 않았지만, 유전막(14) 상부에 상부전극을 형성하여 캐패시터를 완성한다. 여기서, 상부전극은 금속막의 단일막으로 형성하거나, 금속막 상부에 완충막으로서 도핑된 폴리실리콘막을 200 내지 1000Å의 두께로 적층한 폴리실리콘막/금속막의 이중막으로 형성하여 구조적인 안정성을 확보하면서 열적 또는 전기적 충격에 대해 상부전극의 내구성을 향상시킬 수 있다. 바람직하게, 금속막은 TiN막, TaN막, W막, WN막, Ru막, RuO2막, Ir막, IrO2막 및 Pt막 중 선택되는 하나의 막을 이용하여 CVD, ALD를 포함한 플라즈마보조(Plasma Enhnaced)-CVD, 또는 RF 자기 스퍼터링(magnetic sputtering)으로 형성한다.Thereafter, although not shown, an upper electrode is formed on the dielectric film 14 to complete the capacitor. Here, the upper electrode is formed of a single film of a metal film or a polysilicon film doped as a buffer film on the metal film as a double film of a polysilicon film / metal film laminated to a thickness of 200 to 1000 Å to ensure structural stability. It is possible to improve the durability of the upper electrode against thermal or electrical shock. Preferably, the metal film is plasma assisted including CVD and ALD using one of TiN film, TaN film, W film, WN film, Ru film, RuO 2 film, Ir film, IrO 2 film and Pt film. Enhnaced) -CVD, or RF magnetic sputtering.

상기 실시예에 의하면, 캐패시터의 유전막을 막구조가 안정한 Al2O3박막과 유전율이 높은 TiO2막의 이중막으로 형성함에 따라, TiO2막에 대한 열처리시 Al2O3박막이 확산배리어로서 작용하기 때문에 하부전극의 폴리실리콘막과 계면반응을 방지할 수 있고, 이에 따라 등가산화막 두께(Tox)를 25Å 이하로 종래의 NO 캐패시터(Tox=50∼55Å)나 Ta2O5캐패시터(Tox=30 내지 40Å) 보다 현저하게 감소시킴으로써 고집적화에 대응하는 충분한 캐패시터 용량을 확보하는 것이 가능하다. 또한, TiO2막 하부에 형성된 Al2O3박막에 의해 TiO2막의 열처리 공정이 용이하게 이루어지기 때문에 TiO2막 내의 탄소 불순물 등을 제거하는 것이 가능해짐으로써 캐패시터의 누설전류 및 유전특성 등을 현저하게 향상시킬 수 있다. 또한, Al2O3박막의 기계적 전기적 강도가 우수한 페롭스카이트형 구조에 의해 유전막의 열적 또는 전기적 강도가 강해지기 때문에 높은 항복전압을 얻을 수 있다.According to the embodiment, as is the dielectric layer of the capacitor film structure forming a stable Al 2 O 3 thin film and the dielectric constant is high TiO 2 film is a double film, heat treatment Al 2 O 3 thin film acts as a diffusion barrier for the TiO 2 film Therefore, the interfacial reaction with the polysilicon film of the lower electrode can be prevented, and accordingly, the equivalent oxide film thickness (Tox) is 25 kΩ or less and the conventional NO capacitor (Tox = 50-55 kPa) or Ta 2 O 5 capacitor (Tox = 30). It is possible to ensure a sufficient capacitor capacity corresponding to high integration by reducing it significantly more). Also, notably the leakage current and the dielectric properties of the capacitor by, since the TiO 2 film, a heat treatment step easily achieved by the Al 2 O 3 thin film formed on the TiO 2 film lower becomes possible to remove and carbon impurities in the TiO 2 film Can be improved. In addition, since the thermal or electrical strength of the dielectric film is increased by the perovskite structure having excellent mechanical and electrical strength of the Al 2 O 3 thin film, high breakdown voltage can be obtained.

한편, 상기 실시예에서는 실린더 구조의 캐패시터에 대해서만 한정하여 설명하였지만, 컨케이브 구조(concave structure) 캐패시터에도 동일하게 적용하여 실시할 수 있다.In the above embodiment, only the capacitor of the cylinder structure has been described. However, the present invention may be similarly applied to a capacitor structure capacitor.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

전술한 본 발명은 캐패시터의 유전막을 막구조가 안정한 Al2O3박막과 유전율이 높은 TiO2막의 이중막으로 형성함에 따라, 고집적화에 대응하는 충분한 캐패시터 용량을 확보함과 동시에 누설전류, 유전 특성 및 항복전압 특성 등을 향상시킬 수 있다.According to the present invention, the dielectric film of the capacitor is formed of a double film of an Al 2 O 3 thin film having a stable film structure and a TiO 2 film having a high dielectric constant, thereby ensuring sufficient capacitor capacity corresponding to high integration, and at the same time, leakage current, dielectric characteristics and The breakdown voltage characteristic can be improved.

Claims (16)

반도체 기판 상에 하부전극을 형성하는 단계;Forming a lower electrode on the semiconductor substrate; 상기 하부전극 표면에 제 1 유전막으로서 알루미나 박막을 형성하는 단계;Forming an alumina thin film as a first dielectric film on the lower electrode surface; 상기 알루니마 박막 상부에 제 2 유전막으로서 티타늄산화막을 형성하여 티타늄산화막/알루미나 박막의 이중막으로 이루어진 유전막을 형성하는 단계; 및Forming a titanium oxide film as a second dielectric film on the alumina thin film to form a dielectric film composed of a double layer of a titanium oxide film / alumina thin film; And 상기 유전막 상부에 상부전극을 형성하는 단계를 포함하는 반도체 소자의 캐패시터 제조방법.Forming an upper electrode on the dielectric layer, Capacitor manufacturing method of a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 알루미나 박막과 상기 티타늄산화막의 형성은 각각 증착 및 결정화를 위한 열처리의 2단계 공정으로 이루어진 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.Forming the alumina thin film and the titanium oxide film is a capacitor manufacturing method of a semiconductor device, characterized in that consisting of a two-step process of heat treatment for deposition and crystallization, respectively. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 알루미나 박막은 10 내지 20Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The alumina thin film is a capacitor manufacturing method of a semiconductor device, characterized in that formed in a thickness of 10 to 20Å. 제 3 항에 있어서,The method of claim 3, wherein 상기 알루미나 박막의 증착은 TMA(Al(CH3)3)의 소오스 개스와 O2또는 O3의 반응개스를 사용하여 저압-화학기상증착 또는 원자층증착으로 수행하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The alumina thin film is deposited by low pressure chemical vapor deposition or atomic layer deposition using a source gas of TMA (Al (CH 3 ) 3 ) and a reaction gas of O 2 or O 3 . Manufacturing method. 제 3 항에 있어서,The method of claim 3, wherein 상기 알루미나 박막의 열처리는 급속열처리로 수행하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.Heat treatment of the alumina thin film is a capacitor manufacturing method of a semiconductor device, characterized in that performed by rapid heat treatment. 제 5 항에 있어서,The method of claim 5, wherein 상기 급속열처리는 800 내지 900℃의 온도에서 N2 분위기로 30 내지 120초 동안 수행하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The rapid heat treatment is a capacitor manufacturing method of a semiconductor device, characterized in that performed for 30 to 120 seconds in an N2 atmosphere at a temperature of 800 to 900 ℃. 제 3 항에 있어서,The method of claim 3, wherein 상기 티타늄산화막은 30 내지 100Å의 두께로 형성하는 것을 특징으로 하는반도체 소자의 캐패시터 제조방법.The titanium oxide film is a capacitor manufacturing method of the semiconductor device, characterized in that formed in a thickness of 30 to 100Å. 제 7 항에 있어서,The method of claim 7, wherein 상기 티타늄산화막의 증착은 Ti 성분의 소오스 개스와 O2또는 O3의 반응개스를 사용하여 저압-화학기상증착 또는 원자층증착에 의해 수행하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The deposition of the titanium oxide film is a capacitor manufacturing method of a semiconductor device, characterized in that the low-pressure chemical vapor deposition or atomic layer deposition using a source gas of Ti component and the reaction gas of O 2 or O 3 . 제 8 항에 있어서,The method of claim 8, 상기 티타늄산화막의 증착은 300 내지 600℃의 온도 및 0.1 내지 5torr의 압력하에서 수행하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.Deposition of the titanium oxide film is a capacitor manufacturing method of a semiconductor device, characterized in that performed at a temperature of 300 to 600 ℃ and a pressure of 0.1 to 5 torr. 제 7 항에 있어서,The method of claim 7, wherein 상기 티타늄산화막의 열처리는 N2O 또는 O2분위기에서 노어닐링 또는 급속열처리로 수행하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.Heat treatment of the titanium oxide film is a capacitor manufacturing method of the semiconductor device, characterized in that performed by the annealing or rapid heat treatment in N 2 O or O 2 atmosphere. 제 10 항에 있어서,The method of claim 10, 상기 노어닐링은 600 내지 800℃의 온도에서 5분 내지 120분 정도 수행하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The furnace annealing is a capacitor manufacturing method of a semiconductor device, characterized in that performed for 5 to 120 minutes at a temperature of 600 to 800 ℃. 제 10 항에 있어서,The method of claim 10, 상기 급속열처리는 800 내지 900℃의 온도에서 30 내지 120초 동안 수행하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The rapid heat treatment is a capacitor manufacturing method of a semiconductor device, characterized in that performed for 30 to 120 seconds at a temperature of 800 to 900 ℃. 제 1 항에 있어서,The method of claim 1, 상기 하부전극을 형성하는 단계와 상기 알루미나 박막을 형성하는 단계 사이에, 상기 하부전극의 표면을 세정처리하는 단계와 상기 하부전극의 표면을 질화처리하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.Between the step of forming the lower electrode and the step of forming the alumina thin film, the step of cleaning the surface of the lower electrode and the step of nitriding the surface of the lower electrode further comprising Capacitor Manufacturing Method. 제 1 항에 있어서,The method of claim 1, 상기 하부전극은 도핑된 폴리실리콘막 또는 금속막으로 이루어진 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.And the lower electrode is formed of a doped polysilicon film or a metal film. 제 1 항에 있어서,The method of claim 1, 상기 상부전극은 금속막의 단일막 또는 도핑된 폴리실리콘막/금속막의 이중막으로 이루어진 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The upper electrode is a capacitor manufacturing method of a semiconductor device, characterized in that consisting of a single film of a metal film or a double film of a doped polysilicon film / metal film. 제 14 또는 제 15 항에 있어서,The method according to claim 14 or 15, 상기 금속막은 TiN막, TaN막, W막, WN막, Ru막, RuO2막, Ir막, IrO2막 및 Pt막 중 선택되는 하나의 막인 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The metal film is a capacitor manufacturing method of a semiconductor device, characterized in that one film selected from TiN film, TaN film, W film, WN film, Ru film, RuO 2 film, Ir film, IrO 2 film and Pt film.
KR1020020086190A 2002-12-30 2002-12-30 Method of manufacturing capacitor for semiconductor device KR20040059442A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7923343B2 (en) 2008-08-28 2011-04-12 Hynix Semiconductor Inc. Capacitor of semiconductor device and method for forming the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7923343B2 (en) 2008-08-28 2011-04-12 Hynix Semiconductor Inc. Capacitor of semiconductor device and method for forming the same

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